JP2015005748A5 - - Google Patents
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- JP2015005748A5 JP2015005748A5 JP2014125069A JP2014125069A JP2015005748A5 JP 2015005748 A5 JP2015005748 A5 JP 2015005748A5 JP 2014125069 A JP2014125069 A JP 2014125069A JP 2014125069 A JP2014125069 A JP 2014125069A JP 2015005748 A5 JP2015005748 A5 JP 2015005748A5
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- JP
- Japan
- Prior art keywords
- substrate
- mold layer
- manufacturing
- forming
- rear surface
- Prior art date
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Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2013-0071775 | 2013-06-21 | ||
| KR1020130071775A KR102077153B1 (ko) | 2013-06-21 | 2013-06-21 | 관통전극을 갖는 반도체 패키지 및 그 제조방법 |
| US14/264,120 US9245771B2 (en) | 2013-06-21 | 2014-04-29 | Semiconductor packages having through electrodes and methods for fabricating the same |
| US14/264,120 | 2014-04-29 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2015005748A JP2015005748A (ja) | 2015-01-08 |
| JP2015005748A5 true JP2015005748A5 (enExample) | 2016-02-25 |
| JP5908030B2 JP5908030B2 (ja) | 2016-04-26 |
Family
ID=52111252
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014125069A Active JP5908030B2 (ja) | 2013-06-21 | 2014-06-18 | 貫通電極を有する半導体パッケージ及びその製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9245771B2 (enExample) |
| JP (1) | JP5908030B2 (enExample) |
| KR (1) | KR102077153B1 (enExample) |
| CN (1) | CN104241229B (enExample) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR102174336B1 (ko) * | 2014-07-08 | 2020-11-04 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
| US20170062240A1 (en) * | 2015-08-25 | 2017-03-02 | Inotera Memories, Inc. | Method for manufacturing a wafer level package |
| JP2017069397A (ja) * | 2015-09-30 | 2017-04-06 | 日立化成株式会社 | 半導体装置及びその製造方法 |
| JP2017073472A (ja) * | 2015-10-07 | 2017-04-13 | 株式会社ディスコ | 半導体装置の製造方法 |
| US10872879B2 (en) | 2015-11-12 | 2020-12-22 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor package and manufacturing method thereof |
| KR101712288B1 (ko) * | 2015-11-12 | 2017-03-03 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
| KR102506697B1 (ko) * | 2016-05-18 | 2023-03-08 | 에스케이하이닉스 주식회사 | 관통 몰드 볼 커넥터를 포함하는 반도체 패키지 |
| US10204893B2 (en) | 2016-05-19 | 2019-02-12 | Invensas Bonding Technologies, Inc. | Stacked dies and methods for forming bonded structures |
| US9922845B1 (en) * | 2016-11-03 | 2018-03-20 | Micron Technology, Inc. | Semiconductor package and fabrication method thereof |
| US10879212B2 (en) | 2017-05-11 | 2020-12-29 | Invensas Bonding Technologies, Inc. | Processed stacked dies |
| US20180358398A1 (en) * | 2017-06-13 | 2018-12-13 | Xintec Inc. | Chip package and manufacturing method thereof |
| US10217720B2 (en) | 2017-06-15 | 2019-02-26 | Invensas Corporation | Multi-chip modules formed using wafer-level processing of a reconstitute wafer |
| US12068246B2 (en) * | 2017-11-30 | 2024-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution layer layouts on integrated circuits and methods for manufacturing the same |
| KR102085654B1 (ko) * | 2017-12-07 | 2020-03-06 | 주식회사 아모텍 | 다이오드 복합소자 및 그의 제조 방법 |
| US11276676B2 (en) | 2018-05-15 | 2022-03-15 | Invensas Bonding Technologies, Inc. | Stacked devices and methods of fabrication |
| US10727204B2 (en) * | 2018-05-29 | 2020-07-28 | Advances Micro Devices, Inc. | Die stacking for multi-tier 3D integration |
| US11158606B2 (en) | 2018-07-06 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Molded direct bonded and interconnected stack |
| US11462419B2 (en) | 2018-07-06 | 2022-10-04 | Invensas Bonding Technologies, Inc. | Microelectronic assemblies |
| CN108831861A (zh) * | 2018-08-09 | 2018-11-16 | 苏州晶方半导体科技股份有限公司 | 堆叠式芯片封装方法及封装结构 |
| US10950529B2 (en) * | 2018-08-30 | 2021-03-16 | Advanced Semiconductor Engineering Korea, Inc. | Semiconductor device package |
| US20220406765A9 (en) * | 2018-10-02 | 2022-12-22 | Micron Technology, Inc. | Semiconductor device packages having stacked semiconductor dice |
| US12198997B2 (en) * | 2018-10-26 | 2025-01-14 | Nepes Co., Ltd. | Semiconductor package comprising first molding layer and second molding layer with different thermal expansion coefficients |
| WO2020150159A1 (en) | 2019-01-14 | 2020-07-23 | Invensas Bonding Technologies, Inc. | Bonded structures |
| US11296053B2 (en) | 2019-06-26 | 2022-04-05 | Invensas Bonding Technologies, Inc. | Direct bonded stack structures for increased reliability and improved yield in microelectronics |
| KR102722905B1 (ko) | 2019-07-25 | 2024-10-30 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
| US12080672B2 (en) | 2019-09-26 | 2024-09-03 | Adeia Semiconductor Bonding Technologies Inc. | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive |
| JP7488116B2 (ja) * | 2020-06-03 | 2024-05-21 | 株式会社ディスコ | 電極形成方法 |
| US11631647B2 (en) | 2020-06-30 | 2023-04-18 | Adeia Semiconductor Bonding Technologies Inc. | Integrated device packages with integrated device die and dummy element |
| KR102805365B1 (ko) | 2020-07-15 | 2025-05-12 | 삼성전자주식회사 | 반도체 패키지, 및 이를 가지는 패키지 온 패키지 |
| US11728273B2 (en) | 2020-09-04 | 2023-08-15 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
| US11764177B2 (en) | 2020-09-04 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structure with interconnect structure |
| US20220165669A1 (en) * | 2020-11-25 | 2022-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure, stacked semiconductor device structure and method of manufacturing semiconductor device structure |
| CN113035825A (zh) * | 2021-02-02 | 2021-06-25 | 日月光半导体制造股份有限公司 | 半导体封装结构及其形成方法 |
Family Cites Families (26)
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|---|---|---|---|---|
| JP3525808B2 (ja) | 1999-06-28 | 2004-05-10 | 松下電器産業株式会社 | 半導体装置の製造方法および半導体装置 |
| JP2001237205A (ja) * | 2000-02-24 | 2001-08-31 | Sumitomo Metal Ind Ltd | 化学機械的研磨装置、ダマシン配線形成装置及びダマシン配線形成方法 |
| US6841883B1 (en) * | 2003-03-31 | 2005-01-11 | Micron Technology, Inc. | Multi-dice chip scale semiconductor components and wafer level methods of fabrication |
| JP4390775B2 (ja) | 2006-02-08 | 2009-12-24 | Ｏｋｉセミコンダクタ株式会社 | 半導体パッケージの製造方法 |
| US8409920B2 (en) * | 2007-04-23 | 2013-04-02 | Stats Chippac Ltd. | Integrated circuit package system for package stacking and method of manufacture therefor |
| US7948095B2 (en) | 2008-02-12 | 2011-05-24 | United Test And Assembly Center Ltd. | Semiconductor package and method of making the same |
| US7955895B2 (en) * | 2008-11-07 | 2011-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and method for stacked wafer fabrication |
| US8487444B2 (en) | 2009-03-06 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Three-dimensional system-in-package architecture |
| US8531015B2 (en) | 2009-03-26 | 2013-09-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming a thin wafer without a carrier |
| KR20100109241A (ko) | 2009-03-31 | 2010-10-08 | 삼성전자주식회사 | 칩 적층 패키지 및 그 제조방법 |
| US8143097B2 (en) | 2009-09-23 | 2012-03-27 | Stats Chippac, Ltd. | Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP |
| KR20110105159A (ko) | 2010-03-18 | 2011-09-26 | 주식회사 하이닉스반도체 | 적층 반도체 패키지 및 그 형성방법 |
| KR101667656B1 (ko) | 2010-03-24 | 2016-10-20 | 삼성전자주식회사 | 패키지-온-패키지 형성방법 |
| KR101142339B1 (ko) * | 2010-06-17 | 2012-05-17 | 에스케이하이닉스 주식회사 | 반도체 칩 |
| US8338939B2 (en) | 2010-07-12 | 2012-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | TSV formation processes using TSV-last approach |
| KR101678539B1 (ko) * | 2010-07-21 | 2016-11-23 | 삼성전자 주식회사 | 적층 패키지, 반도체 패키지 및 적층 패키지의 제조 방법 |
| KR20120045402A (ko) | 2010-10-29 | 2012-05-09 | 에스케이하이닉스 주식회사 | 반도체 집적회로 및 그의 제조 방법 |
| KR20120053332A (ko) | 2010-11-17 | 2012-05-25 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| JP2012209545A (ja) | 2011-03-17 | 2012-10-25 | Sekisui Chem Co Ltd | 半導体積層体の製造方法 |
| KR20120123919A (ko) | 2011-05-02 | 2012-11-12 | 삼성전자주식회사 | 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지 |
| US8642385B2 (en) | 2011-08-09 | 2014-02-04 | Alpha & Omega Semiconductor, Inc. | Wafer level package structure and the fabrication method thereof |
| US8853003B2 (en) * | 2011-08-09 | 2014-10-07 | Alpha & Omega Semiconductor, Inc. | Wafer level chip scale package with thick bottom metal exposed and preparation method thereof |
| US8779599B2 (en) * | 2011-11-16 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages including active dies and dummy dies and methods for forming the same |
| KR101784507B1 (ko) * | 2011-12-14 | 2017-10-12 | 에스케이하이닉스 주식회사 | 반도체 적층 패키지 및 제조 방법, 이를 포함하는 전자 시스템 |
| US9006004B2 (en) * | 2012-03-23 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probing chips during package formation |
| JP5399542B2 (ja) * | 2012-08-08 | 2014-01-29 | 富士通株式会社 | 半導体装置の製造方法 |
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2013
- 2013-06-21 KR KR1020130071775A patent/KR102077153B1/ko active Active
-
2014
- 2014-04-29 US US14/264,120 patent/US9245771B2/en active Active
- 2014-06-18 JP JP2014125069A patent/JP5908030B2/ja active Active
- 2014-06-20 CN CN201410279831.7A patent/CN104241229B/zh active Active