JP2014532862A - 構成可能なインターフェースを有する試験機器 - Google Patents

構成可能なインターフェースを有する試験機器 Download PDF

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Publication number
JP2014532862A
JP2014532862A JP2014538796A JP2014538796A JP2014532862A JP 2014532862 A JP2014532862 A JP 2014532862A JP 2014538796 A JP2014538796 A JP 2014538796A JP 2014538796 A JP2014538796 A JP 2014538796A JP 2014532862 A JP2014532862 A JP 2014532862A
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JP
Japan
Prior art keywords
test
port
test equipment
uut
fpga
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014538796A
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English (en)
Japanese (ja)
Inventor
ブーラッサ、ステファン・ジェイ
マクゴールドリック、マイケル・フランシス
カウシャンスキー、デイビッド
フルート、マイケル・トーマス
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Teradyne Inc
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Teradyne Inc
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Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of JP2014532862A publication Critical patent/JP2014532862A/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31704—Design for test; Design verification
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP2014538796A 2011-10-28 2012-09-20 構成可能なインターフェースを有する試験機器 Pending JP2014532862A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/284,378 US9470759B2 (en) 2011-10-28 2011-10-28 Test instrument having a configurable interface
US13/284,378 2011-10-28
PCT/US2012/056247 WO2013062692A1 (en) 2011-10-28 2012-09-20 Test instrument having a configurable interface

Publications (1)

Publication Number Publication Date
JP2014532862A true JP2014532862A (ja) 2014-12-08

Family

ID=48168296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014538796A Pending JP2014532862A (ja) 2011-10-28 2012-09-20 構成可能なインターフェースを有する試験機器

Country Status (6)

Country Link
US (1) US9470759B2 (cg-RX-API-DMAC7.html)
EP (1) EP2771704A4 (cg-RX-API-DMAC7.html)
JP (1) JP2014532862A (cg-RX-API-DMAC7.html)
KR (1) KR101970290B1 (cg-RX-API-DMAC7.html)
IN (1) IN2014CN02499A (cg-RX-API-DMAC7.html)
WO (1) WO2013062692A1 (cg-RX-API-DMAC7.html)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020165711A (ja) * 2019-03-28 2020-10-08 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置
JP2022517513A (ja) * 2019-01-22 2022-03-09 株式会社アドバンテスト オンチップシステムテストコントローラを使用した自動テスト装置

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EP3213214B1 (fr) 2014-10-30 2021-03-03 SPHEREA Test & Services Banc et logiciel pour tester un appareillage electrique, notamment un calculateur
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US11169203B1 (en) 2018-09-26 2021-11-09 Teradyne, Inc. Determining a configuration of a test system
US11408927B2 (en) 2019-06-18 2022-08-09 Teradyne, Inc. Functional testing with inline parametric testing
JP7317209B2 (ja) 2019-08-06 2023-07-28 株式会社アドバンテスト 処理ユニット並びにプログラム及び／又はデータメモリを含む被試験デバイスをテストするための自動試験機器、テストコントローラ、被試験デバイスへの１又は複数のインターフェース、共有メモリを含む自動試験機器、並びに被試験デバイスをテストするための方法
US11461222B2 (en) 2020-04-16 2022-10-04 Teradyne, Inc. Determining the complexity of a test program
CN112653598B (zh) * 2020-12-18 2022-02-22 迈普通信技术股份有限公司 自动化测试方法、装置、设备及可读存储介质
CN113868038B (zh) * 2021-08-30 2024-06-04 中科可控信息产业有限公司 信号测试方法、装置、计算机设备和存储介质
CN114020554A (zh) * 2021-10-30 2022-02-08 江苏信而泰智能装备有限公司 一种测试仪的端口隔离方法和具有端口隔离功能的测试仪
US20240118339A1 (en) * 2022-10-11 2024-04-11 SK Hynix Inc. System, method for circuit validation, and system and method for facilitating circuit validation

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Cited By (4)

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Publication number Priority date Publication date Assignee Title
JP2022517513A (ja) * 2019-01-22 2022-03-09 株式会社アドバンテスト オンチップシステムテストコントローラを使用した自動テスト装置
JP7295954B2 (ja) 2019-01-22 2023-06-21 株式会社アドバンテスト オンチップシステムテストコントローラを使用した自動テスト装置
JP2020165711A (ja) * 2019-03-28 2020-10-08 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置
JP7316818B2 (ja) 2019-03-28 2023-07-28 株式会社アドバンテスト 波形データ取得モジュールおよび試験装置

Also Published As

Publication number Publication date
IN2014CN02499A (cg-RX-API-DMAC7.html) 2015-06-26
US9470759B2 (en) 2016-10-18
US20130110446A1 (en) 2013-05-02
EP2771704A4 (en) 2015-03-25
WO2013062692A1 (en) 2013-05-02
KR101970290B1 (ko) 2019-04-18
KR20140091719A (ko) 2014-07-22
EP2771704A1 (en) 2014-09-03

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