JP2014531751A - 異なる幅のディジットを有するインターディジタルキャパシタ - Google Patents
異なる幅のディジットを有するインターディジタルキャパシタ Download PDFInfo
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- JP2014531751A JP2014531751A JP2014529709A JP2014529709A JP2014531751A JP 2014531751 A JP2014531751 A JP 2014531751A JP 2014529709 A JP2014529709 A JP 2014529709A JP 2014529709 A JP2014529709 A JP 2014529709A JP 2014531751 A JP2014531751 A JP 2014531751A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/43—Electric condenser making
Abstract
Description
本開示の1つ以上の局面に基づく例示的な実施形態について上に記載した一方で、以下の請求項およびその均等物によって定められる範囲から逸脱することなく本開示の1以上の局面に基づく他のさらなる実施形態が考案されてもよい。ステップを示す請求項は、ステップの順序を暗に定義するものではない。商標はそれぞれの所有者によって所有される。
Claims (15)
- キャパシタであって、
第1の複数の導電ディジットと、
インターディジタル構造が形成されるように、前記第1の複数の導電ディジットとかみ合うようにして位置決めされる第2の複数の導電ディジットとを備え、
前記第1の複数の導電ディジットおよび前記第2の複数の導電ディジットは、全体としてディジットのセットを形成し、
前記ディジットのセットにおける第1のディジットの幅は、前記ディジットのセットにおける第2のディジットに対して不均一である、キャパシタ。 - 前記インターディジタル構造の端部の最も近くに位置決めされる前記ディジットのセットの第1サブセットは、前記インターディジタル構造の中心の最も近くに位置決めされる前記ディジットのセットの第2サブセットよりも広い幅を有する、請求項1に記載のキャパシタ。
- 前記インターディジタル構造の端部の最も近くに位置決めされる前記ディジットのセットの第1サブセットは、前記インターディジタル構造の中心の最も近くに位置決めされる前記ディジットのセットの第2サブセットよりも3倍から5倍広い幅を有する、請求項1に記載のキャパシタ。
- 前記インターディジタル構造の端部の最も近くに位置決めされる前記ディジットのセットにおける第1所定数のサブセットは、第1の幅を有し、
前記ディジットのセットにおけるディジットの残りは、前記第1の幅よりも狭い第2の幅を有する、請求項1に記載のキャパシタ。 - 前記ディジットのセットにおける各ディジットの幅は、前記インターディジタル構造の端部に位置決めされるディジットにおける最も広い幅から、前記インターディジタル構造の中心に位置決めされるディジットにおける最も狭い幅へ徐々に漸減する、請求項1から4のいずれか1項に記載のキャパシタ。
- 前記ディジットのセットにおけるディジットの相対幅は、前記インターディジタル構造における磁界Hの分布に基づいて定められる、請求項1に記載のキャパシタ。
- 前記ディジットのセットにおける特定の1つの幅は、ディジットのセットにおける前記特定の1つによって担持される電流の量に比例する、請求項6に記載のキャパシタ。
- 前記第1の複数の導電ディジットおよび前記第2の複数の導電ディジットは、銅、ドープポリシリコン、アルミニウム、または窒化チタンのうちの少なくとも1つから形成される、請求項1から7のいずれか1項に記載のキャパシタ。
- 前記第1の複数の導電ディジットは、第1の材料から形成され、
前記第2の複数の導電ディジットは、前記第1の材料とは異なる第2の材料から形成される、請求項1から7のいずれか1項に記載のキャパシタ。 - 前記インターディジタル構造に結合される少なくとも1つのバーをさらに備え、
前記少なくとも1つのバーは、少なくとも1つの給電点を有する、請求項1から7のいずれか1項に記載のキャパシタ。 - 前記少なくとも1つの給電点の最も近くに位置決めされる前記ディジットのセットにおける第1サブセットは、前記ディジットのセットの残りよりも広い幅を有する、請求項10に記載のキャパシタ。
- キャパシタを形成する方法であって、前記方法は、
第1の複数の導電ディジットを形成するステップと、
インターディジタル構造が形成されるように、前記第1の複数の導電ディジットとかみ合うようにして位置決めされる第2の複数の導電ディジットを形成するステップとを備え、
前記第1の複数の導電ディジットおよび前記第2の複数の導電ディジットは、全体としてディジットのセットを形成し、
前記ディジットのセットにおける第1のディジットの幅は、前記ディジットのセットにおける第2のディジットに対して不均一である、方法。 - 前記インターディジタル構造に結合されるバーの給電点の最も近くに位置決めされる前記ディジットのセットの第1サブセットは、前記バーの前記給電点から最も遠くに位置決めされる前記ディジットのセットの第2サブセットよりも広い幅を有する、請求項12に記載の方法。
- 前記ディジットのセットにおける各ディジットの幅は、前記インターディジタル構造に結合されるバーの給電点の近くに位置決めされるディジットにおける最も広い幅から、前記バーの前記給電点から最も遠くに位置決めされるディジットにおける最も狭い幅へ徐々に漸減する、請求項12に記載の方法。
- 前記ディジットのセットにおけるディジットの相対幅は、前記インターディジタル構造における磁界Hの分布に基づいて定められ、
前記ディジットのセットにおける特定の1つの幅は、前記ディジットのセットにおける前記特定の1つによって担持される電流の量に比例する、請求項12に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US13/229,207 | 2011-09-09 | ||
US13/229,207 US8941974B2 (en) | 2011-09-09 | 2011-09-09 | Interdigitated capacitor having digits of varying width |
PCT/US2012/039898 WO2013036306A1 (en) | 2011-09-09 | 2012-05-29 | Interdigitated capacitor having digits of varying width |
Publications (2)
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JP2014531751A true JP2014531751A (ja) | 2014-11-27 |
JP6009567B2 JP6009567B2 (ja) | 2016-10-19 |
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JP2014529709A Active JP6009567B2 (ja) | 2011-09-09 | 2012-05-29 | 異なる幅のディジットを有するインターディジタルキャパシタ |
Country Status (8)
Country | Link |
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US (1) | US8941974B2 (ja) |
EP (1) | EP2754189B1 (ja) |
JP (1) | JP6009567B2 (ja) |
KR (1) | KR101871544B1 (ja) |
CN (1) | CN103988328B (ja) |
IN (1) | IN2014CN02337A (ja) |
TW (1) | TWI533340B (ja) |
WO (1) | WO2013036306A1 (ja) |
Families Citing this family (8)
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US9270247B2 (en) | 2013-11-27 | 2016-02-23 | Xilinx, Inc. | High quality factor inductive and capacitive circuit structure |
US9524964B2 (en) | 2014-08-14 | 2016-12-20 | Xilinx, Inc. | Capacitor structure in an integrated circuit |
JP6710161B2 (ja) * | 2014-12-26 | 2020-06-17 | 京セラ株式会社 | 弾性波装置 |
US10409426B2 (en) * | 2015-04-14 | 2019-09-10 | Ford Global Technologies, Llc | Motion based capacitive sensor system |
US20160343796A1 (en) * | 2015-05-22 | 2016-11-24 | Mediatek Inc. | Capacitor structure and method for forming the same |
US9948313B1 (en) * | 2016-12-19 | 2018-04-17 | Silicon Laboratories Inc. | Magnetically differential loop filter capacitor elements and methods related to same |
US20220270830A1 (en) * | 2021-02-19 | 2022-08-25 | Micron Technology, Inc. | Supercapacitors and Integrated Assemblies Containing Supercapacitors |
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Also Published As
Publication number | Publication date |
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CN103988328B (zh) | 2016-12-21 |
US20130063861A1 (en) | 2013-03-14 |
EP2754189B1 (en) | 2020-12-16 |
JP6009567B2 (ja) | 2016-10-19 |
KR20140062493A (ko) | 2014-05-23 |
US8941974B2 (en) | 2015-01-27 |
CN103988328A (zh) | 2014-08-13 |
WO2013036306A1 (en) | 2013-03-14 |
IN2014CN02337A (ja) | 2015-06-19 |
TWI533340B (zh) | 2016-05-11 |
TW201312613A (zh) | 2013-03-16 |
EP2754189A1 (en) | 2014-07-16 |
KR101871544B1 (ko) | 2018-08-02 |
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