JP2014514757A - 化学的に改変されたスペーサ表面を有する集積回路 - Google Patents

化学的に改変されたスペーサ表面を有する集積回路 Download PDF

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Publication number
JP2014514757A
JP2014514757A JP2014502758A JP2014502758A JP2014514757A JP 2014514757 A JP2014514757 A JP 2014514757A JP 2014502758 A JP2014502758 A JP 2014502758A JP 2014502758 A JP2014502758 A JP 2014502758A JP 2014514757 A JP2014514757 A JP 2014514757A
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JP
Japan
Prior art keywords
dielectric material
spacer
gate stack
gate
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014502758A
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English (en)
Japanese (ja)
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JP2014514757A5 (enExample
Inventor
ケイ カークパトリック ブライアン
ジェイン アミターブ
Original Assignee
日本テキサス・インスツルメンツ株式会社
テキサス インスツルメンツ インコーポレイテッド
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Priority claimed from US13/427,062 external-priority patent/US9496359B2/en
Application filed by 日本テキサス・インスツルメンツ株式会社, テキサス インスツルメンツ インコーポレイテッド filed Critical 日本テキサス・インスツルメンツ株式会社
Publication of JP2014514757A publication Critical patent/JP2014514757A/ja
Publication of JP2014514757A5 publication Critical patent/JP2014514757A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP2014502758A 2011-03-28 2012-03-28 化学的に改変されたスペーサ表面を有する集積回路 Pending JP2014514757A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161468308P 2011-03-28 2011-03-28
US61/468,308 2011-03-28
US13/427,062 2012-03-22
US13/427,062 US9496359B2 (en) 2011-03-28 2012-03-22 Integrated circuit having chemically modified spacer surface
PCT/US2012/030977 WO2012135363A2 (en) 2011-03-28 2012-03-28 Integrated circuit having chemically modified spacer surface

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017088445A Division JP6534163B2 (ja) 2011-03-28 2017-04-27 化学的に改変されたスペーサ表面を有する集積回路

Publications (2)

Publication Number Publication Date
JP2014514757A true JP2014514757A (ja) 2014-06-19
JP2014514757A5 JP2014514757A5 (enExample) 2015-05-14

Family

ID=46932319

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Application Number Title Priority Date Filing Date
JP2014502758A Pending JP2014514757A (ja) 2011-03-28 2012-03-28 化学的に改変されたスペーサ表面を有する集積回路
JP2017088445A Active JP6534163B2 (ja) 2011-03-28 2017-04-27 化学的に改変されたスペーサ表面を有する集積回路
JP2019079500A Active JP6916430B2 (ja) 2011-03-28 2019-04-18 化学的に改変されたスペーサ表面を有する集積回路
JP2021017147A Active JP7157835B2 (ja) 2011-03-28 2021-02-05 化学的に改変されたスペーサ表面を有する集積回路

Family Applications After (3)

Application Number Title Priority Date Filing Date
JP2017088445A Active JP6534163B2 (ja) 2011-03-28 2017-04-27 化学的に改変されたスペーサ表面を有する集積回路
JP2019079500A Active JP6916430B2 (ja) 2011-03-28 2019-04-18 化学的に改変されたスペーサ表面を有する集積回路
JP2021017147A Active JP7157835B2 (ja) 2011-03-28 2021-02-05 化学的に改変されたスペーサ表面を有する集積回路

Country Status (2)

Country Link
JP (4) JP2014514757A (enExample)
WO (1) WO2012135363A2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952725B (zh) * 2014-03-24 2018-02-06 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法
JP7019085B1 (ja) 2021-04-26 2022-02-14 Dmg森精機株式会社 工作機械

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005064403A (ja) * 2003-08-20 2005-03-10 Sony Corp 半導体装置の製造方法および半導体装置
JP2007157870A (ja) * 2005-12-02 2007-06-21 Renesas Technology Corp 半導体装置及びその製造方法
JP2008047820A (ja) * 2006-08-21 2008-02-28 Toshiba Corp 半導体装置の製造方法および半導体装置
JP2008117848A (ja) * 2006-11-01 2008-05-22 Nec Electronics Corp 半導体装置の製造方法
JP2009140967A (ja) * 2007-12-03 2009-06-25 Panasonic Corp 半導体装置の製造方法
JP2010118500A (ja) * 2008-11-13 2010-05-27 Toshiba Corp 半導体装置及びその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3811518B2 (ja) * 1995-01-12 2006-08-23 松下電器産業株式会社 半導体装置およびその製造方法
JP2002246463A (ja) * 2001-02-13 2002-08-30 Sony Corp 半導体装置の製造方法及び半導体装置
KR100416628B1 (ko) * 2002-06-22 2004-01-31 삼성전자주식회사 게이트 스페이서를 포함하는 반도체 소자 제조 방법
US6806149B2 (en) * 2002-09-26 2004-10-19 Texas Instruments Incorporated Sidewall processes using alkylsilane precursors for MOS transistor fabrication
JP2004134687A (ja) * 2002-10-15 2004-04-30 Toshiba Corp 半導体装置及びその製造方法
US6812073B2 (en) * 2002-12-10 2004-11-02 Texas Instrument Incorporated Source drain and extension dopant concentration
KR20040051696A (ko) * 2002-12-11 2004-06-19 주식회사 하이닉스반도체 반도체소자의 스페이서 형성방법
JP2004200550A (ja) * 2002-12-20 2004-07-15 Renesas Technology Corp 半導体装置の製造方法
US6991979B2 (en) * 2003-09-22 2006-01-31 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
US7229869B2 (en) * 2005-03-08 2007-06-12 Texas Instruments Incorporated Method for manufacturing a semiconductor device using a sidewall spacer etchback
JP2007053296A (ja) * 2005-08-19 2007-03-01 Elpida Memory Inc 半導体装置及びその製造方法
US7371649B2 (en) * 2005-09-13 2008-05-13 United Microelectronics Corp. Method of forming carbon-containing silicon nitride layer
JP2009170751A (ja) * 2008-01-18 2009-07-30 Fujitsu Ltd 半導体装置の製造方法
US8138045B2 (en) * 2008-05-19 2012-03-20 Texas Instruments Incorporated Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005064403A (ja) * 2003-08-20 2005-03-10 Sony Corp 半導体装置の製造方法および半導体装置
JP2007157870A (ja) * 2005-12-02 2007-06-21 Renesas Technology Corp 半導体装置及びその製造方法
JP2008047820A (ja) * 2006-08-21 2008-02-28 Toshiba Corp 半導体装置の製造方法および半導体装置
JP2008117848A (ja) * 2006-11-01 2008-05-22 Nec Electronics Corp 半導体装置の製造方法
JP2009140967A (ja) * 2007-12-03 2009-06-25 Panasonic Corp 半導体装置の製造方法
JP2010118500A (ja) * 2008-11-13 2010-05-27 Toshiba Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
JP6534163B2 (ja) 2019-06-26
JP2019145825A (ja) 2019-08-29
JP2021073735A (ja) 2021-05-13
JP7157835B2 (ja) 2022-10-20
JP2017143302A (ja) 2017-08-17
WO2012135363A2 (en) 2012-10-04
JP6916430B2 (ja) 2021-08-11
WO2012135363A3 (en) 2012-12-06

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