JP2014053590A - 薄膜トランジスタ基板及びその製造方法 - Google Patents
薄膜トランジスタ基板及びその製造方法 Download PDFInfo
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- JP2014053590A JP2014053590A JP2013105880A JP2013105880A JP2014053590A JP 2014053590 A JP2014053590 A JP 2014053590A JP 2013105880 A JP2013105880 A JP 2013105880A JP 2013105880 A JP2013105880 A JP 2013105880A JP 2014053590 A JP2014053590 A JP 2014053590A
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Abstract
【課題】薄膜トランジスタ基板及びその製造方法を提供すること。
【解決手段】開示した薄膜トランジスタ基板は、ベース基板と、前記ベース基板上に配置され、ソース電極、ドレイン電極及び前記ソース電極と前記ドレイン電極との間に配置されて酸化物半導体を含むチャネルを含むアクティブパターンと、前記アクティブパターン上に配置されたゲート絶縁パターンと、前記ゲート絶縁パターン上に配置され、前記チャネルとオーバーラップするゲート電極と、前記ベース基板と前記アクティブパターンの間に配置される遮光パターンとを含む。
【選択図】図1
Description
前記ソース電極及び前記ドレーン電極は、前記酸化物半導体から還元された金属を含む。
図1は本発明の一実施形態に係る薄膜トランジスタ基板の平面図である。図2は図1のI−I’ラインに沿って切断した断面図である。
110、310、510 ベース基板
GL ゲートライン
DL データライン
GE ゲート電極
PE 画素電極
120、320、520 アクティブパターン
140、340、540 遮光パターン
130 接続電極
113、313、513 データ絶縁層
115、315、515 第1平坦化膜
117、317、517 パッシベーション層
119、319、519 第2平坦化膜
150、350、550 バッファパターン
160、360、560 ゲート絶縁パターン
CH1、CH2、CH3 コンタクトホール
Claims (29)
- ベース基板と、
前記ベース基板上に配置され、ソース電極、ドレイン電極及び前記ソース電極と前記ドレイン電極との間に配置されて酸化物半導体を含むチャネルを含むアクティブパターンと、
前記アクティブパターン上に配置されたゲート絶縁パターンと、
前記ゲート絶縁パターン上に配置され、前記チャネルとオーバーラップするゲート電極と、
前記ベース基板と前記アクティブパターンとの間に配置される遮光パターンと、を含むことを特徴とする薄膜トランジスタ基板。 - 前記ソース電極及び前記ドレイン電極は、酸化物半導体から還元された金属を含むことを特徴とする請求項1に記載の薄膜トランジスタ基板。
- 前記酸化物半導体は酸化亜鉛(ZnO)、亜鉛錫酸化物(ZTO)、亜鉛インジウム酸化物(ZIO)、インジウム酸化物(InO)、チタン酸化物(TiO)、インジウムガリウム亜鉛酸化物(IGZO)及びインジウム亜鉛錫酸化物(IZTO)からなるグループから選択された少なくとも一つを含むことを特徴とする請求項1に記載の薄膜トランジスタ基板。
- 前記ゲート電極と電気的に接続されたゲートラインと、
前記ソース電極と電気的に接続されたデータラインと、
前記ドレイン電極と電気的に接続された画素電極と、をさらに含むことを特徴とする請求項1に記載の薄膜トランジスタ基板。 - 前記ゲートライン及び前記データラインのうち少なくとも一つは、下部キャッピング層、上部キャッピング層及び前記下部キャッピング層と前記上部キャッピング層との間に配置される金属層を含み、前記下部キャッピング層及び前記上部キャッピング層はモース硬度4以上の酸化物を含むことを特徴とする請求項4に記載の薄膜トランジスタ基板。
- 前記金属層は銅を含み、前記下部キャッピング層及び前記上部キャッピング層はインジウム亜鉛酸化物を含むことを特徴とする請求項5に記載の薄膜トランジスタ基板。
- 前記ゲートライン及び前記データラインのうち少なくとも一つは、60度以上のテーパー角を有することを特徴とする請求項6に記載の薄膜トランジスタ基板。
- 前記データラインをカバーするデータ絶縁層と、
前記データ絶縁層上に配置され、前記データラインによる段差を補償する第1平坦化膜と、をさらに含むことを特徴とする請求項4に記載の薄膜トランジスタ基板。 - 前記遮光パターンは前記第1平坦化膜上に配置されることを特徴とする請求項8に記載の薄膜トランジスタ基板。
- 前記ゲート電極、前記ゲートライン、前記アクティブパターン及び前記第1平坦化膜をカバーするパッシベーション層と、
前記パッシベーション層上に配置される第2平坦化膜と、をさらに含むことを特徴とする請求項9に記載の薄膜トランジスタ基板。 - 前記データ絶縁層、前記第1平坦化膜、前記パッシベーション層及び前記第2平坦化膜を貫通する第1コンタクトホールを介して前記データラインに接続され、前記パッシベーション層及び前記第2平坦化膜を貫通する第2コンタクトホールを介して前記ソース電極に接続される接続電極をさらに含むことを特徴とする請求項10に記載の薄膜トランジスタ基板。
- 前記遮光パターンと前記アクティブパターンとの間に配置されるバッファパターンをさらに含むことを特徴とする請求項1に記載の薄膜トランジスタ基板。
- 前記遮光パターンは、シリコン酸化物、シリコンゲルマニウム合金、ゲルマニウム及び酸化チタンからなるグループから選択された少なくとも一つを含むことを特徴とする請求項1に記載の薄膜トランジスタ基板。
- 前記遮光パターンは、平面図上において前記アクティブパターンと同じ形状を有することを特徴とする請求項13に記載の薄膜トランジスタ基板。
- 前記遮光パターンは、平面図上において前記アクティブパターンより大きさが大きなことを特徴とする請求項13に記載の薄膜トランジスタ基板。
- 前記遮光パターンは、前記ゲート電極全体及び前記アクティブパターン全体とオーバーラップすることを特徴とする請求項15に記載の薄膜トランジスタ基板。
- 酸化物半導体層を形成する段階と、
前記酸化物半導体層をパターニングして酸化物半導体パターンを形成する段階と、
前記酸化物半導体パターン上にゲート絶縁層及びゲート金属層を順次に形成する段階と、
前記ゲート金属層をパターニングしてゲート電極を形成する段階と、
前記ゲート絶縁層をパターニングしてゲート絶縁パターンを形成して前記酸化物半導体パターンを露出する段階と、
前記酸化物半導体パターンの露出した部分を還元して、金属を含むソース電極及びドレイン電極を形成する段階と、を含む薄膜トランジスタ基板の製造方法。 - 前記酸化物半導体層は、酸化亜鉛(ZnO)、亜鉛錫酸化物(ZTO)、亜鉛インジウム酸化物(ZIO)、インジウム酸化物(InO)、チタン酸化物(TiO)、インジウムガリウム亜鉛酸化物(IGZO)及びインジウム亜鉛錫酸化物(IZTO)からなるグループから選択された少なくとも一つを含むことを特徴とする請求項17に記載の薄膜トランジスタ基板の製造方法。
- 前記ソース電極及び前記ドレイン電極を形成するために、前記酸化物半導体パターンの露出した部分にプラズマを加えることを特徴とする請求項17に記載の薄膜トランジスタ基板の製造方法。
- 遮光層を形成する段階と、
前記遮光層上にバッファ層を形成する段階と、をさらに含み、
前記酸化物半導体層を形成する段階は、前記バッファ層上に前記酸化物半導体層を形成する段階を含むことを特徴とする請求項17に記載の薄膜トランジスタ基板の製造方法。 - 前記遮光層は、シリコン酸化物、シリコンゲルマニウム合金、ゲルマニウム及び酸化チタンからなるグループから選択された少なくとも一つを含むことを特徴とする請求項20に記載の薄膜トランジスタ基板の製造方法。
- 前記バッファ層をパターニングしてバッファパターンを形成する段階と、
前記遮光層をパターニングして遮光パターンを形成する段階と、をさらに含み、
前記バッファ層及び前記遮光層は前記ゲート絶縁層を形成する前にパターニングされ、平面図上において、前記バッファパターン及び前記遮光パターンは、前記酸化物半導体パターンと同じ形状を有することを特徴とする請求項20に記載の薄膜トランジスタ基板の製造方法。 - 前記バッファ層をパターニングしてバッファパターンを形成する段階と、
前記遮光層をパターニングして遮光パターンを形成する段階と、をさらに含み、
前記バッファ層及び前記遮光層は、前記ゲート絶縁パターンを形成した後にパターニングされ、平面図上において、前記バッファパターン及び前記遮光パターンは前記酸化物半導体パターンより大きさが大きなことを特徴とする請求項20に記載の薄膜トランジスタ基板の製造方法。 - ベース基板上にデータ金属層を形成する段階と、
前記データ金属層をパターニングしてデータラインを形成する段階と、
前記データラインをカバーするデータ絶縁層を形成する段階と、
前記データ絶縁層上に、前記データラインによる段差を補償する第1平坦化膜を形成する段階と、をさらに含み、
前記酸化物半導体層を形成する段階は、前記第1平坦化膜上に前記酸化物半導体層を形成する段階を含むことを特徴とする請求項17に記載の薄膜トランジスタ基板の製造方法。 - 前記データ金属層及び前記ゲート金属層のうち少なくとも一つは、下部キャッピング層、上部キャッピング層及び前記下部キャッピング層と前記上部キャッピング層との間に配置される金属層を含み、前記下部キャッピング層及び前記上部キャッピング層は、モース硬度4以上の酸化物を含むことを特徴とする請求項24に記載の薄膜トランジスタ基板の製造方法。
- 前記金属層は銅を含み、前記下部キャッピング層及び前記上部キャッピング層はインジウム亜鉛酸化物を含むことを特徴とする請求項25に記載の薄膜トランジスタ基板の製造方法。
- 前記金属層、前記下部キャッピング層及び前記上部キャッピング層は、同じエッチャントによってエッチングされ、前記データライン及び前記ゲート電極のうち少なくとも一つは60度以上のテーパー角を有することを特徴とする請求項25に記載の薄膜トランジスタ基板の製造方法。
- 前記ゲート電極、前記ソース電極、前記ドレイン電極及び前記第1平坦化膜をカバーするパッシベーション層を形成する段階と、
前記パッシベーション層上に配置される第2平坦化膜を形成する段階と、をさらに含むことを特徴とする請求項24に記載の薄膜トランジスタ基板の製造方法。 - 前記データ絶縁層、前記第1平坦化膜、前記パッシベーション層及び前記第2平坦化膜をパターニングして、前記データラインを露出する第1コンタクトホール、前記ソース電極を露出する第2コンタクトホール及び前記ドレイン電極を露出する第3コンタクトホールを形成する段階と、
前記第2平坦化膜上に透明導電層を形成する段階と、
前記透明導電層をパターニングして前記データライン及び前記ソース電極と接続される接続電極並びに前記ドレイン電極と接続される画素電極を形成する段階と、をさらに含むことを特徴とする請求項28に記載の薄膜トランジスタ基板の製造方法。
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CN111897168A (zh) * | 2020-08-21 | 2020-11-06 | 京东方科技集团股份有限公司 | 阵列基板及其制备方法、显示装置 |
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Also Published As
Publication number | Publication date |
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KR20140032155A (ko) | 2014-03-14 |
US20140061632A1 (en) | 2014-03-06 |
EP2706575A1 (en) | 2014-03-12 |
EP2706575B1 (en) | 2017-04-05 |
CN103681690A (zh) | 2014-03-26 |
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