JP2013539910A - アンダーフィル付き半導体チップデバイス - Google Patents
アンダーフィル付き半導体チップデバイス Download PDFInfo
- Publication number
- JP2013539910A JP2013539910A JP2013528347A JP2013528347A JP2013539910A JP 2013539910 A JP2013539910 A JP 2013539910A JP 2013528347 A JP2013528347 A JP 2013528347A JP 2013528347 A JP2013528347 A JP 2013528347A JP 2013539910 A JP2013539910 A JP 2013539910A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- underfill
- sidewall
- interposer
- side wall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/26145—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10252—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/878,812 | 2010-09-09 | ||
| US12/878,812 US8691626B2 (en) | 2010-09-09 | 2010-09-09 | Semiconductor chip device with underfill |
| PCT/US2011/051075 WO2012034064A1 (en) | 2010-09-09 | 2011-09-09 | Semiconductor chip device with underfill |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2013539910A true JP2013539910A (ja) | 2013-10-28 |
| JP2013539910A5 JP2013539910A5 (enExample) | 2014-10-30 |
Family
ID=44652038
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013528347A Pending JP2013539910A (ja) | 2010-09-09 | 2011-09-09 | アンダーフィル付き半導体チップデバイス |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US8691626B2 (enExample) |
| EP (1) | EP2614521B1 (enExample) |
| JP (1) | JP2013539910A (enExample) |
| KR (1) | KR101571837B1 (enExample) |
| CN (1) | CN103098190A (enExample) |
| WO (1) | WO2012034064A1 (enExample) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016098594A1 (ja) * | 2014-12-16 | 2016-06-23 | ソニー株式会社 | 半導体装置、固体撮像素子、撮像装置、および電子機器 |
| JP2017507495A (ja) * | 2014-03-04 | 2017-03-16 | クアルコム,インコーポレイテッド | 高密度インターコネクトおよび再分配層を備える集積デバイス |
| WO2017199278A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社日立製作所 | 半導体装置 |
| JP2023109410A (ja) * | 2022-01-27 | 2023-08-08 | エスケーハイニックス株式会社 | Tsv用モールドアンダーフィル組成物 |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20110099556A (ko) * | 2010-03-02 | 2011-09-08 | 삼성전자주식회사 | 반도체 패키지 테스트장치 |
| TWI496254B (zh) * | 2010-11-01 | 2015-08-11 | 欣興電子股份有限公司 | 嵌埋半導體元件之封裝結構及其製法 |
| US8363418B2 (en) * | 2011-04-18 | 2013-01-29 | Morgan/Weiss Technologies Inc. | Above motherboard interposer with peripheral circuits |
| US8952540B2 (en) | 2011-06-30 | 2015-02-10 | Intel Corporation | In situ-built pin-grid arrays for coreless substrates, and methods of making same |
| US9006004B2 (en) * | 2012-03-23 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probing chips during package formation |
| TWI508249B (zh) | 2012-04-02 | 2015-11-11 | 矽品精密工業股份有限公司 | 封裝件、半導體封裝結構及其製法 |
| US10192810B2 (en) | 2013-06-28 | 2019-01-29 | Intel Corporation | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
| US9412674B1 (en) * | 2013-10-24 | 2016-08-09 | Xilinx, Inc. | Shielded wire arrangement for die testing |
| US9721852B2 (en) * | 2014-01-21 | 2017-08-01 | International Business Machines Corporation | Semiconductor TSV device package to which other semiconductor device package can be later attached |
| KR101622453B1 (ko) * | 2014-01-22 | 2016-05-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
| US9373559B2 (en) * | 2014-03-05 | 2016-06-21 | International Business Machines Corporation | Low-stress dual underfill packaging |
| US9437576B1 (en) * | 2015-03-23 | 2016-09-06 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US9798088B2 (en) * | 2015-11-05 | 2017-10-24 | Globalfoundries Inc. | Barrier structures for underfill blockout regions |
| US9627784B1 (en) | 2015-12-01 | 2017-04-18 | International Business Machines Corporation | Method and apparatus for strain relieving surface mount attached connectors |
| US10701800B2 (en) * | 2016-01-28 | 2020-06-30 | Hewlett Packard Enterprise Development Lp | Printed circuit boards |
| US10249515B2 (en) * | 2016-04-01 | 2019-04-02 | Intel Corporation | Electronic device package |
| US10475766B2 (en) * | 2017-03-29 | 2019-11-12 | Intel Corporation | Microelectronics package providing increased memory component density |
| US10304800B2 (en) * | 2017-06-23 | 2019-05-28 | Taiwan Semiconductor Manufacturing Company Ltd. | Packaging with substrates connected by conductive bumps |
| US10529693B2 (en) | 2017-11-29 | 2020-01-07 | Advanced Micro Devices, Inc. | 3D stacked dies with disparate interconnect footprints |
| US10727204B2 (en) | 2018-05-29 | 2020-07-28 | Advances Micro Devices, Inc. | Die stacking for multi-tier 3D integration |
| US10937755B2 (en) | 2018-06-29 | 2021-03-02 | Advanced Micro Devices, Inc. | Bond pads for low temperature hybrid bonding |
| JP2020150145A (ja) * | 2019-03-14 | 2020-09-17 | キオクシア株式会社 | 半導体装置 |
| KR102689648B1 (ko) | 2020-02-03 | 2024-07-30 | 삼성전자주식회사 | 댐 구조물을 갖는 반도체 패키지 |
| CN113571430B (zh) * | 2020-04-28 | 2025-10-31 | 桑迪士克科技股份有限公司 | 具有减小的底部填充面积的倒装芯片封装体 |
| KR102825809B1 (ko) * | 2020-07-10 | 2025-06-27 | 삼성전자주식회사 | 언더필이 구비된 반도체 패키지 및 이의 제조 방법 |
| KR102853612B1 (ko) | 2020-07-15 | 2025-09-03 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| KR20230032592A (ko) * | 2021-08-31 | 2023-03-07 | 삼성전자주식회사 | 반도체 패키지 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074868A (ja) * | 1996-08-30 | 1998-03-17 | Oki Electric Ind Co Ltd | 半導体実装装置及び半導体装置の封止方法 |
| JP2008283004A (ja) * | 2007-05-11 | 2008-11-20 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JP2009043765A (ja) * | 2007-08-06 | 2009-02-26 | Denso Corp | 電子装置 |
| JP2009158623A (ja) * | 2007-12-26 | 2009-07-16 | Panasonic Corp | 半導体装置の製造方法 |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3065753B2 (ja) | 1991-12-04 | 2000-07-17 | イビデン株式会社 | 半導体集積回路ベアチップの樹脂封止方法、半導体装置 |
| US5901041A (en) * | 1997-12-02 | 1999-05-04 | Northern Telecom Limited | Flexible integrated circuit package |
| JP2000311905A (ja) | 1999-04-28 | 2000-11-07 | Nippon Inter Electronics Corp | 複合半導体装置の製造方法 |
| JP2000357768A (ja) | 1999-06-17 | 2000-12-26 | Hitachi Ltd | 半導体装置及びその製造方法 |
| US6589802B1 (en) * | 1999-12-24 | 2003-07-08 | Hitachi, Ltd. | Packaging structure and method of packaging electronic parts |
| US6949822B2 (en) * | 2000-03-17 | 2005-09-27 | International Rectifier Corporation | Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance |
| US6537482B1 (en) | 2000-08-08 | 2003-03-25 | Micron Technology, Inc. | Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography |
| JP2002124654A (ja) * | 2000-10-13 | 2002-04-26 | Mitsubishi Electric Corp | 固体撮像装置 |
| US6906415B2 (en) | 2002-06-27 | 2005-06-14 | Micron Technology, Inc. | Semiconductor device assemblies and packages including multiple semiconductor devices and methods |
| TW569416B (en) | 2002-12-19 | 2004-01-01 | Via Tech Inc | High density multi-chip module structure and manufacturing method thereof |
| US7122906B2 (en) | 2004-01-29 | 2006-10-17 | Micron Technology, Inc. | Die-wafer package and method of fabricating same |
| US7208342B2 (en) * | 2004-05-27 | 2007-04-24 | Intel Corporation | Package warpage control |
| JP2006261566A (ja) * | 2005-03-18 | 2006-09-28 | Alps Electric Co Ltd | 電子部品用ホルダ及び電子部品用保持シート、これらを用いた電子モジュール、電子モジュールの積層体、電子モジュールの製造方法並びに検査方法 |
| CN1949487A (zh) * | 2005-10-10 | 2007-04-18 | 南茂科技股份有限公司 | 可防止密封材料溢流的膜上倒装片封装结构 |
| JP2007183164A (ja) * | 2006-01-06 | 2007-07-19 | Fujitsu Ltd | 半導体集積回路装置及びその試験方法 |
| JP4391508B2 (ja) * | 2006-09-29 | 2009-12-24 | Okiセミコンダクタ株式会社 | 半導体装置、及び半導体装置の製造方法 |
| CN101777502B (zh) * | 2009-01-13 | 2011-12-07 | 日月光半导体制造股份有限公司 | 倒装芯片封装方法 |
-
2010
- 2010-09-09 US US12/878,812 patent/US8691626B2/en active Active
-
2011
- 2011-09-09 EP EP11757730.4A patent/EP2614521B1/en active Active
- 2011-09-09 WO PCT/US2011/051075 patent/WO2012034064A1/en not_active Ceased
- 2011-09-09 CN CN2011800433411A patent/CN103098190A/zh active Pending
- 2011-09-09 JP JP2013528347A patent/JP2013539910A/ja active Pending
- 2011-09-09 KR KR1020137007013A patent/KR101571837B1/ko active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074868A (ja) * | 1996-08-30 | 1998-03-17 | Oki Electric Ind Co Ltd | 半導体実装装置及び半導体装置の封止方法 |
| JP2008283004A (ja) * | 2007-05-11 | 2008-11-20 | Matsushita Electric Ind Co Ltd | 半導体装置 |
| JP2009043765A (ja) * | 2007-08-06 | 2009-02-26 | Denso Corp | 電子装置 |
| JP2009158623A (ja) * | 2007-12-26 | 2009-07-16 | Panasonic Corp | 半導体装置の製造方法 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017507495A (ja) * | 2014-03-04 | 2017-03-16 | クアルコム,インコーポレイテッド | 高密度インターコネクトおよび再分配層を備える集積デバイス |
| WO2016098594A1 (ja) * | 2014-12-16 | 2016-06-23 | ソニー株式会社 | 半導体装置、固体撮像素子、撮像装置、および電子機器 |
| US10153314B2 (en) | 2014-12-16 | 2018-12-11 | Sony Corporation | Semiconductor apparatus, solid-state image pickup device, image pickup apparatus, and electronic apparatus |
| WO2017199278A1 (ja) * | 2016-05-16 | 2017-11-23 | 株式会社日立製作所 | 半導体装置 |
| JP2023109410A (ja) * | 2022-01-27 | 2023-08-08 | エスケーハイニックス株式会社 | Tsv用モールドアンダーフィル組成物 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012034064A1 (en) | 2012-03-15 |
| KR101571837B1 (ko) | 2015-11-25 |
| US20120061853A1 (en) | 2012-03-15 |
| US8691626B2 (en) | 2014-04-08 |
| CN103098190A (zh) | 2013-05-08 |
| EP2614521A1 (en) | 2013-07-17 |
| KR20130109116A (ko) | 2013-10-07 |
| EP2614521B1 (en) | 2018-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2013539910A (ja) | アンダーフィル付き半導体チップデバイス | |
| KR102541861B1 (ko) | 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지 | |
| US8736065B2 (en) | Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same | |
| KR102039710B1 (ko) | 유기 인터포저를 포함하는 반도체 패키지 | |
| JP5654067B2 (ja) | アンダーバンプ配線層の方法および装置 | |
| CN112385022B (zh) | 包括芯层的嵌入式迹线基板(ets)中的高密度互连 | |
| KR102428876B1 (ko) | 패키지 기판을 제조하기 위한 방법 및 패키지. | |
| EP2754175B1 (en) | Solder mask with anchor structures | |
| CN107993987B (zh) | 具有内置参考平面结构的封装对板互连结构 | |
| JP2006261311A (ja) | 半導体装置及びその製造方法 | |
| JP2018530160A (ja) | 集積回路(IC)パッケージの間にギャップコントローラを備えるパッケージオンパッケージ(PoP)デバイス | |
| CN105580135A (zh) | 具有通孔条的半导体器件 | |
| KR20130102052A (ko) | 열 관리를 갖춘 적층형 반도체 칩 장치 | |
| KR20200024502A (ko) | 팬-아웃 반도체 패키지 | |
| TWI850290B (zh) | 封裝裝置及其製造方法 | |
| KR20100123664A (ko) | 매입형 상호접속체를 구비하는 보강 봉입체를 포함하는 집적회로 패키징 시스템 및 그 제조 방법 | |
| JP6551750B2 (ja) | ファン−アウト半導体パッケージ | |
| US7160757B2 (en) | Gap control between interposer and substrate in electronic assemblies | |
| KR102049255B1 (ko) | 팬-아웃 반도체 패키지 | |
| US20250309171A1 (en) | Semiconductor package with ball grid array connection having improved reliability | |
| KR101952861B1 (ko) | 팬-아웃 반도체 패키지 | |
| EP2962535B1 (en) | Package substrate with testing pads on fine pitch traces | |
| TW202326962A (zh) | 與玻璃核心基板耦接的多個晶粒 | |
| CN115732341A (zh) | 一种三维半导体器件的制备方法及三维半导体器件 | |
| US20250364386A1 (en) | Electronic device and layout checking method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20140909 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140909 |
|
| A871 | Explanation of circumstances concerning accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A871 Effective date: 20140909 |
|
| A975 | Report on accelerated examination |
Free format text: JAPANESE INTERMEDIATE CODE: A971005 Effective date: 20141105 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141118 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150217 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150318 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20150623 |