KR101571837B1 - 언더필을 갖는 반도체 칩 디바이스 - Google Patents

언더필을 갖는 반도체 칩 디바이스 Download PDF

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KR101571837B1
KR101571837B1 KR1020137007013A KR20137007013A KR101571837B1 KR 101571837 B1 KR101571837 B1 KR 101571837B1 KR 1020137007013 A KR1020137007013 A KR 1020137007013A KR 20137007013 A KR20137007013 A KR 20137007013A KR 101571837 B1 KR101571837 B1 KR 101571837B1
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semiconductor chip
underfill
interposer
sidewall
cover
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KR20130109116A (ko
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마이클 제트. 수
레이 푸
자말 레파이-아메드
브라이언 블랙
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
에이티아이 테크놀로지스 유엘씨
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12100635B2 (en) 2020-07-15 2024-09-24 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110099556A (ko) * 2010-03-02 2011-09-08 삼성전자주식회사 반도체 패키지 테스트장치
TWI496254B (zh) * 2010-11-01 2015-08-11 欣興電子股份有限公司 嵌埋半導體元件之封裝結構及其製法
US8363418B2 (en) * 2011-04-18 2013-01-29 Morgan/Weiss Technologies Inc. Above motherboard interposer with peripheral circuits
US8952540B2 (en) * 2011-06-30 2015-02-10 Intel Corporation In situ-built pin-grid arrays for coreless substrates, and methods of making same
US9006004B2 (en) 2012-03-23 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Probing chips during package formation
TWI508249B (zh) * 2012-04-02 2015-11-11 矽品精密工業股份有限公司 封裝件、半導體封裝結構及其製法
US10192810B2 (en) 2013-06-28 2019-01-29 Intel Corporation Underfill material flow control for reduced die-to-die spacing in semiconductor packages
US9412674B1 (en) * 2013-10-24 2016-08-09 Xilinx, Inc. Shielded wire arrangement for die testing
US9721852B2 (en) 2014-01-21 2017-08-01 International Business Machines Corporation Semiconductor TSV device package to which other semiconductor device package can be later attached
KR101622453B1 (ko) * 2014-01-22 2016-05-31 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9230936B2 (en) * 2014-03-04 2016-01-05 Qualcomm Incorporated Integrated device comprising high density interconnects and redistribution layers
US9373559B2 (en) * 2014-03-05 2016-06-21 International Business Machines Corporation Low-stress dual underfill packaging
JP2016115840A (ja) * 2014-12-16 2016-06-23 ソニー株式会社 半導体装置、固体撮像素子、撮像装置、および電子機器
US9437576B1 (en) * 2015-03-23 2016-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9798088B2 (en) * 2015-11-05 2017-10-24 Globalfoundries Inc. Barrier structures for underfill blockout regions
US9627784B1 (en) 2015-12-01 2017-04-18 International Business Machines Corporation Method and apparatus for strain relieving surface mount attached connectors
US10701800B2 (en) * 2016-01-28 2020-06-30 Hewlett Packard Enterprise Development Lp Printed circuit boards
US10249515B2 (en) * 2016-04-01 2019-04-02 Intel Corporation Electronic device package
WO2017199278A1 (ja) * 2016-05-16 2017-11-23 株式会社日立製作所 半導体装置
US10475766B2 (en) * 2017-03-29 2019-11-12 Intel Corporation Microelectronics package providing increased memory component density
US10304800B2 (en) * 2017-06-23 2019-05-28 Taiwan Semiconductor Manufacturing Company Ltd. Packaging with substrates connected by conductive bumps
US10529693B2 (en) 2017-11-29 2020-01-07 Advanced Micro Devices, Inc. 3D stacked dies with disparate interconnect footprints
US10727204B2 (en) 2018-05-29 2020-07-28 Advances Micro Devices, Inc. Die stacking for multi-tier 3D integration
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
JP2020150145A (ja) * 2019-03-14 2020-09-17 キオクシア株式会社 半導体装置
KR102689648B1 (ko) 2020-02-03 2024-07-30 삼성전자주식회사 댐 구조물을 갖는 반도체 패키지
CN113571430B (zh) * 2020-04-28 2025-10-31 桑迪士克科技股份有限公司 具有减小的底部填充面积的倒装芯片封装体
KR102825809B1 (ko) * 2020-07-10 2025-06-27 삼성전자주식회사 언더필이 구비된 반도체 패키지 및 이의 제조 방법
KR20230032592A (ko) * 2021-08-31 2023-03-07 삼성전자주식회사 반도체 패키지
JP2023109410A (ja) * 2022-01-27 2023-08-08 エスケーハイニックス株式会社 Ｔｓｖ用モールドアンダーフィル組成物

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009043765A (ja) * 2007-08-06 2009-02-26 Denso Corp 電子装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3065753B2 (ja) 1991-12-04 2000-07-17 イビデン株式会社 半導体集積回路ベアチップの樹脂封止方法、半導体装置
JPH1074868A (ja) * 1996-08-30 1998-03-17 Oki Electric Ind Co Ltd 半導体実装装置及び半導体装置の封止方法
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
JP2000311905A (ja) 1999-04-28 2000-11-07 Nippon Inter Electronics Corp 複合半導体装置の製造方法
JP2000357768A (ja) 1999-06-17 2000-12-26 Hitachi Ltd 半導体装置及びその製造方法
US6589802B1 (en) * 1999-12-24 2003-07-08 Hitachi, Ltd. Packaging structure and method of packaging electronic parts
US6949822B2 (en) * 2000-03-17 2005-09-27 International Rectifier Corporation Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance
US6537482B1 (en) 2000-08-08 2003-03-25 Micron Technology, Inc. Underfill and encapsulation of carrier substrate-mounted flip-chip components using stereolithography
JP2002124654A (ja) * 2000-10-13 2002-04-26 Mitsubishi Electric Corp 固体撮像装置
US6906415B2 (en) 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
TW569416B (en) 2002-12-19 2004-01-01 Via Tech Inc High density multi-chip module structure and manufacturing method thereof
US7122906B2 (en) 2004-01-29 2006-10-17 Micron Technology, Inc. Die-wafer package and method of fabricating same
US7208342B2 (en) * 2004-05-27 2007-04-24 Intel Corporation Package warpage control
JP2006261566A (ja) * 2005-03-18 2006-09-28 Alps Electric Co Ltd 電子部品用ホルダ及び電子部品用保持シート、これらを用いた電子モジュール、電子モジュールの積層体、電子モジュールの製造方法並びに検査方法
CN1949487A (zh) * 2005-10-10 2007-04-18 南茂科技股份有限公司 可防止密封材料溢流的膜上倒装片封装结构
JP2007183164A (ja) * 2006-01-06 2007-07-19 Fujitsu Ltd 半導体集積回路装置及びその試験方法
JP4391508B2 (ja) * 2006-09-29 2009-12-24 Ｏｋｉセミコンダクタ株式会社 半導体装置、及び半導体装置の製造方法
JP2008283004A (ja) * 2007-05-11 2008-11-20 Matsushita Electric Ind Co Ltd 半導体装置
JP2009158623A (ja) 2007-12-26 2009-07-16 Panasonic Corp 半導体装置の製造方法
CN101777502B (zh) * 2009-01-13 2011-12-07 日月光半导体制造股份有限公司 倒装芯片封装方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009043765A (ja) * 2007-08-06 2009-02-26 Denso Corp 電子装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12100635B2 (en) 2020-07-15 2024-09-24 Samsung Electronics Co., Ltd. Semiconductor package and method of fabricating the same

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