JP2013539601A - 共振トランジスタゲートを有するパワーfet - Google Patents
共振トランジスタゲートを有するパワーfet Download PDFInfo
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- JP2013539601A JP2013539601A JP2013526109A JP2013526109A JP2013539601A JP 2013539601 A JP2013539601 A JP 2013539601A JP 2013526109 A JP2013526109 A JP 2013526109A JP 2013526109 A JP2013526109 A JP 2013526109A JP 2013539601 A JP2013539601 A JP 2013539601A
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- resonant gate
- power management
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Abstract
Description
本出願は、2010年8月23日に出願された「完全集積型高出力シリコン・チップ・キャリア」と題する米国仮特許出願第61/375,894号の優先権を主張するものである。
ヨシモチの「高速パワーMOSFET」と題する米国特許第7,459,749号明細書は、パワーFETのスイッチング速度を高めるために、チャネル内蔵ゲート構造体に低抵抗層を装着する。
本明細書において、「能動素子」という用語は、動作するための電力を必要としかつ電力利得を生み出すことができる電気回路の一素子としてのその従来の定義を指すものと理解される。
を用いて特徴づけられる。
式中、
Lgateはゲートの長さであり、
Wgateはゲートの幅であり、
Cgateはゲートのキャパシタンスであり、
μelecは、真性半導体層68の電子移動度であり、
VGおよびVGS(sh)は各々、ゲート電圧およびゲート−ソース短絡電圧であり、
κは、電極ジオメトリに関連する形態係数であり、
かつ、
ρDrainは、真性半導体層68および直列に追加されるドレイン層69の抵抗率である。
ゲートの長さLgateは、断面図で見ると、図2C(図1B)に描かれているように、ゲート電極の幅87(表面FETの場合は37)である。同様に、ゲートの幅Wgateは、図1Bおよび図2Cに提供された断面図における平面に対して上下に広がり、共振トランジスタゲート内に含まれる全てのアクティブなゲート構造体セグメント72(19)を組み合わせた幅の総合計である。
A=π(Rout−Rin 2) (式2)
として決定され、ここで、中心に穴がない場合、Rin=0である。通常、真性半導体層75の厚さは5μm(5×10−4cm)以下である。ソース電極が約1cmの外半径を有し、内半径が0.4cmである場合、真性半導体75の層厚さを5μmであると仮定すると、ドーナツの総表面積は2.51cm2であり、形態係数κ=2×10−4となる。層厚さを2μmまで減らすことができ、かつソース電極がドーナツ穴なしで半径2cmまで広げられる設計では、形態係数はκ=1.6×10−5になる。結果的に、システム全体を半導体上に完全に集積することにより、より大きい経済的価値を半導体リアルエステートに追加して有効化されるソース電極63の大幅に拡張されたサイズは、On抵抗(RON)を劇的に低減する。拡張されるソース電極、およびその下で伸張されるゲート幅はシステム損失を減らし、よって、このより大きいシステムに冷却材ループ等の追加的なシステムコストを組み込む必要性が低減される。この1つの完全集積型回路によって高まる全体効率は、電力管理システムが最終的に適用され得る電気モータ、無線基地局または電源分配回路網等の多様なシステムのコストを下げ、かつ本質的価値を高める。また、これらの概念は、ハンドヘルド式無線機器等の低電力システムにも、デバイスの規模をこれらのシステムの低電力要件に合わせて減らすことにより適用されてもよい。
x=Aest (式4a)
として表され、ここで、
であり、かつ回路の自然周波数ω0は、
によって決定され、xは、直列RLC回路が考察される場合にはゲート電圧に適用され、並列RLC回路の場合にはソース電流に適用される。能動素子および受動素子内に導電電極素子を含む抵抗素子は、回路への鈍化力として作用する。並列RLC回路では、減衰係数は、
によって与えられ、かつ直列RLC回路では、減衰係数は、
によって与えられる。
によって与えられる。多くの例では、設計目標として、図3Gに示されているように、終端抵抗器160を用いて共振ゲートトランジスタ11、59に余分な抵抗を追加することにより、帯域幅を広げることが望ましい。終端抵抗器160は、共振ゲート縦型FET59内の最も内側の周方向ゲート構造体セグメント71の終端162に付着され、または、共振ゲート表面FET11を終端処理するために使用される。これは、接地(ソース電極)と電気接触する厳密公差誘電体または導電体であってもよい抵抗素子164から成る。共振ゲート縦型FETの場合、抵抗素子164は終端処理用電極166と電気連通し、終端処理用電極166は、終端処理用電極166がオーバーレイするソース電極63と電気接触することができるように任意の絶縁物質(不図示)から突き出す部分168を有する。
によって与えられることが可能である。ここで、lは結合の長さであり、dはワイヤ間の間隙であり、rはワイヤの半径であって、単位は全てメートルであり、μ0は自由空間透磁率であり、μrは平行するワイヤを分離する物質の透磁率である。
によって与えられることが可能である。ここで、lは結合の長さであり、dはワイヤ間の間隙であり、rはワイヤの半径であって、単位は全てメートルであり、ε0は自由空間の誘電率であり、εrは平行するワイヤを分離する物質の比誘電率である。
Claims (22)
- 共振ゲートとソース電極およびドレイン電極とを備える半導体FETであって、前記共振ゲートは、1つまたは複数の予め決められた周波数で電磁的に共振することを特徴とする半導体FET。
- 前記共振ゲートは、共振ゲートセグメントと直列または並列に接続される、一体式に構築されるリアクティブ素子を含むことを特徴とする請求項1に記載のFET。
- 前記リアクティブ素子は、セラミック誘電体を含むことを特徴とする請求項2に記載のFET。
- 前記誘電体は、−40℃から+120℃までの温度範囲に渡って≦±1%で変わる誘電特性を有することを特徴とする請求項3に記載のFET。
- 前記共振ゲートの全体的な入力キャパシタンスを減らす集中キャパシタンスを形成するために、1つまたは複数の共振ゲートセグメントと直列に電気接続される複数の埋込み式容量回路素子をさらに含むことを特徴とする請求項1に記載のFET。
- 前記共振ゲートは、互いに反応的に結合する隣接して位置決めされたセグメントを有することを特徴とする請求項1に記載のFET。
- 前記共振ゲートの隣接して位置決めされるセグメント間のリアクティブ結合に影響を与えるように一体式に構築される誘電体をさらに備えることを特徴とする請求項6に記載のFET。
- 前記共振ゲートは、細長い共振伝送線路を形成することを特徴とする請求項1に記載のFET。
- 前記共振ゲートのセグメントと共同して前記細長い共振伝送線路を形成するために、前記共振ゲート内に一体式に構築されるリアクティブ素子および抵抗素子をさらに備え、前記細長い伝送線路は、予め決められた1つまたは複数の周波数において共振することを特徴とする請求項8に記載のFET。
- 前記抵抗素子は、前記共振伝送線路を終端処理するために位置決めされることを特徴とする請求項9に記載のFET。
- 前記共振ゲート内部の1つまたは複数の抵抗素子は、前記共振ゲートの帯域幅を制御するように適合化されることを特徴とする請求項9に記載のFET。
- ゲート電極は、ゲート幅対ゲート長比≧100を有することを特徴とする請求項1に記載のFET。
- 前記ゲート幅対ゲート長比は、千対1、1万対1、10万対1または100万対1の何れかより大きいことを特徴とする請求項1に記載のFET。
- 前記共振ゲートは、蛇行路を有するように構築されることを特徴とする請求項1に記載のFET。
- 前記蛇行路は、前記共振ゲートの隣接するセグメント間の電磁結合を誘導することを特徴とする請求項13に記載のFET。
- 前記蛇行路はフラクタル幾何学に従うことを特徴とする請求項14に記載のFET。
- 前記FETと共にモノリシック構造体に集積される電力管理モジュールをさらに備えることを特徴とする請求項1に記載のFET。
- 前記集積されるFETおよびモノリシック電力管理モジュールは、シリコン、シリコンゲルマニウムまたはIII−V族化合物半導体上に形成されることを特徴とする請求項1に記載のFET。
- 前記FETは、DDMOS、超接合もしくはIGBT縦型FETまたは表面FETであることを特徴とする請求項1に記載のFET。
- 請求項1に記載のFETを備えることを特徴とする電力管理モジュール。
- 前記共振ゲートの共振周波数は、前記電力管理モジュールにおいて使用されるスイッチング周波数に一致することを特徴とする請求項22に記載の電力管理モジュール。
- 請求項1に記載のFETを備えることを特徴とするシリコンキャリア。
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PCT/US2011/048870 WO2012027412A1 (en) | 2010-08-23 | 2011-08-23 | Power fet with a resonant transistor gate |
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