JP2013513971A5 - - Google Patents

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Publication number
JP2013513971A5
JP2013513971A5 JP2012544551A JP2012544551A JP2013513971A5 JP 2013513971 A5 JP2013513971 A5 JP 2013513971A5 JP 2012544551 A JP2012544551 A JP 2012544551A JP 2012544551 A JP2012544551 A JP 2012544551A JP 2013513971 A5 JP2013513971 A5 JP 2013513971A5
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JP
Japan
Prior art keywords
wafer
opening
width
forming
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012544551A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013513971A (ja
JP5721742B2 (ja
Filing date
Publication date
Priority claimed from US12/638,424 external-priority patent/US8138062B2/en
Application filed filed Critical
Publication of JP2013513971A publication Critical patent/JP2013513971A/ja
Publication of JP2013513971A5 publication Critical patent/JP2013513971A5/ja
Application granted granted Critical
Publication of JP5721742B2 publication Critical patent/JP5721742B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2012544551A 2009-12-15 2010-11-22 ウェハ構造の電気的結合 Expired - Fee Related JP5721742B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/638,424 2009-12-15
US12/638,424 US8138062B2 (en) 2009-12-15 2009-12-15 Electrical coupling of wafer structures
PCT/US2010/057624 WO2011081741A2 (en) 2009-12-15 2010-11-22 Electrical coupling of wafer structures

Publications (3)

Publication Number Publication Date
JP2013513971A JP2013513971A (ja) 2013-04-22
JP2013513971A5 true JP2013513971A5 (enExample) 2014-01-16
JP5721742B2 JP5721742B2 (ja) 2015-05-20

Family

ID=44143393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012544551A Expired - Fee Related JP5721742B2 (ja) 2009-12-15 2010-11-22 ウェハ構造の電気的結合

Country Status (5)

Country Link
US (1) US8138062B2 (enExample)
JP (1) JP5721742B2 (enExample)
CN (1) CN102656673B (enExample)
TW (1) TWI555069B (enExample)
WO (1) WO2011081741A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8637981B2 (en) 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
US8633088B2 (en) 2012-04-30 2014-01-21 Freescale Semiconductor, Inc. Glass frit wafer bond protective structure
US10246322B2 (en) 2013-03-15 2019-04-02 Versana Micro Inc. Distributed sensor system
CN103466541B (zh) * 2013-09-12 2016-01-27 上海矽睿科技有限公司 晶圆级封装方法以及晶圆
US9630832B2 (en) * 2013-12-19 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US9826630B2 (en) 2014-09-04 2017-11-21 Nxp Usa, Inc. Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof
KR20180032985A (ko) 2016-09-23 2018-04-02 삼성전자주식회사 집적회로 패키지 및 그 제조 방법과 집적회로 패키지를 포함하는 웨어러블 디바이스
CN107827079B (zh) * 2017-11-17 2019-09-20 烟台睿创微纳技术股份有限公司 一种mems芯片的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613838B2 (ja) 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
US6762072B2 (en) * 2002-03-06 2004-07-13 Robert Bosch Gmbh SI wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method
SG111972A1 (en) 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
JP3905041B2 (ja) * 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
US20040166662A1 (en) 2003-02-21 2004-08-26 Aptos Corporation MEMS wafer level chip scale package
JP4551638B2 (ja) * 2003-08-01 2010-09-29 富士フイルム株式会社 固体撮像装置の製造方法
DE10350460B4 (de) * 2003-10-29 2006-07-13 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von mikromechanische und/ oder mikroelektronische Strukturen aufweisenden Halbleiterbauelementen, die durch das feste Verbinden von mindestens zwei Halbleiterscheiben entstehen, und entsprechende Anordnung
US7034393B2 (en) 2003-12-15 2006-04-25 Analog Devices, Inc. Semiconductor assembly with conductive rim and method of producing the same
TWI236111B (en) * 2004-06-30 2005-07-11 Ind Tech Res Inst Apparatus and method for wafer level packaging
US7495462B2 (en) 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
TWI295081B (en) * 2006-01-12 2008-03-21 Touch Micro System Tech Method for wafer level package and fabricating cap structures
US20080131662A1 (en) * 2006-12-05 2008-06-05 Jordan Larry L Alignment of a cap to a MEMS wafer
US20080191334A1 (en) 2007-02-12 2008-08-14 Visera Technologies Company Limited Glass dam structures for imaging devices chip scale package
US20080290430A1 (en) * 2007-05-25 2008-11-27 Freescale Semiconductor, Inc. Stress-Isolated MEMS Device and Method Therefor

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