JP2010538463A5 - - Google Patents

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Publication number
JP2010538463A5
JP2010538463A5 JP2010522993A JP2010522993A JP2010538463A5 JP 2010538463 A5 JP2010538463 A5 JP 2010538463A5 JP 2010522993 A JP2010522993 A JP 2010522993A JP 2010522993 A JP2010522993 A JP 2010522993A JP 2010538463 A5 JP2010538463 A5 JP 2010538463A5
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JP
Japan
Prior art keywords
forming
connector block
polymer layer
semiconductor element
support structure
Prior art date
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Application number
JP2010522993A
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English (en)
Japanese (ja)
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JP5397962B2 (ja
JP2010538463A (ja
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Publication date
Priority claimed from US11/846,874 external-priority patent/US7838420B2/en
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Publication of JP2010538463A publication Critical patent/JP2010538463A/ja
Publication of JP2010538463A5 publication Critical patent/JP2010538463A5/ja
Application granted granted Critical
Publication of JP5397962B2 publication Critical patent/JP5397962B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2010522993A 2007-08-29 2008-07-09 半導体素子パッケージを形成する方法 Active JP5397962B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/846,874 2007-08-29
US11/846,874 US7838420B2 (en) 2007-08-29 2007-08-29 Method for forming a packaged semiconductor device
PCT/US2008/069516 WO2009032398A1 (en) 2007-08-29 2008-07-09 Interconnect in a multi-element package

Publications (3)

Publication Number Publication Date
JP2010538463A JP2010538463A (ja) 2010-12-09
JP2010538463A5 true JP2010538463A5 (enExample) 2011-09-01
JP5397962B2 JP5397962B2 (ja) 2014-01-22

Family

ID=40406108

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010522993A Active JP5397962B2 (ja) 2007-08-29 2008-07-09 半導体素子パッケージを形成する方法

Country Status (7)

Country Link
US (1) US7838420B2 (enExample)
EP (1) EP2195840A4 (enExample)
JP (1) JP5397962B2 (enExample)
KR (1) KR20100065305A (enExample)
CN (1) CN101790788A (enExample)
TW (1) TWI451551B (enExample)
WO (1) WO2009032398A1 (enExample)

Families Citing this family (23)

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Publication number Priority date Publication date Assignee Title
JP2010245107A (ja) * 2009-04-01 2010-10-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8407890B2 (en) 2010-01-25 2013-04-02 Freescale Semiconductor Inc. Method of manufacting an electronic device module with integrated antenna structure
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8916421B2 (en) 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
US8597983B2 (en) 2011-11-18 2013-12-03 Freescale Semiconductor, Inc. Semiconductor device packaging having substrate with pre-encapsulation through via formation
JP5834907B2 (ja) * 2011-12-28 2015-12-24 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US8810024B2 (en) * 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
CN103311141B (zh) * 2013-07-05 2016-01-20 北京理工大学 一种同轴垂直互连导电体的制作方法
US8822268B1 (en) 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof
US9362234B2 (en) 2014-01-07 2016-06-07 Freescale Semiconductor, Inc. Shielded device packages having antennas and related fabrication methods
US10354958B2 (en) 2014-10-01 2019-07-16 Nxp Usa, Inc. Through package circuit in fan-out wafer level package
US9666930B2 (en) 2014-10-23 2017-05-30 Nxp Usa, Inc. Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound
TWI652775B (zh) 2016-01-11 2019-03-01 矽品精密工業股份有限公司 電子封裝件
US10236260B2 (en) 2016-06-30 2019-03-19 Nxp Usa, Inc. Shielded package with integrated antenna
WO2019039335A1 (ja) 2017-08-21 2019-02-28 株式会社村田製作所 電子部品の製造方法及び電子部品
US11557565B2 (en) 2020-10-06 2023-01-17 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US11502054B2 (en) 2020-11-11 2022-11-15 Nxp Usa, Inc. Semiconductor device assembly and method therefor
CN114243287B (zh) * 2021-12-10 2025-08-29 上海微波技术研究所（中国电子科技集团公司第五十研究所） 毫米波相控阵天线阵列集成转换接头
US20240088068A1 (en) * 2022-09-08 2024-03-14 Nxp Usa, Inc. Semiconductor device with through package via and method therefor
US20250218977A1 (en) * 2023-12-29 2025-07-03 International Business Machines Corporation Coaxial through insulator via between chiplets

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