CN101790788A - 多元件封装中的互连 - Google Patents

多元件封装中的互连 Download PDF

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Publication number
CN101790788A
CN101790788A CN200880104602.4A CN200880104602A CN101790788A CN 101790788 A CN101790788 A CN 101790788A CN 200880104602 A CN200880104602 A CN 200880104602A CN 101790788 A CN101790788 A CN 101790788A
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CN
China
Prior art keywords
connector block
semiconductor device
layer
polymer layer
forming
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Pending
Application number
CN200880104602.4A
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English (en)
Chinese (zh)
Inventor
唐金榜
D·R·福莱亚
W·H·莱特尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
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Freescale Semiconductor Inc
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Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN101790788A publication Critical patent/CN101790788A/zh
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Details Of Aerials (AREA)
CN200880104602.4A 2007-08-29 2008-07-09 多元件封装中的互连 Pending CN101790788A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/846,874 2007-08-29
US11/846,874 US7838420B2 (en) 2007-08-29 2007-08-29 Method for forming a packaged semiconductor device
PCT/US2008/069516 WO2009032398A1 (en) 2007-08-29 2008-07-09 Interconnect in a multi-element package

Publications (1)

Publication Number Publication Date
CN101790788A true CN101790788A (zh) 2010-07-28

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Application Number Title Priority Date Filing Date
CN200880104602.4A Pending CN101790788A (zh) 2007-08-29 2008-07-09 多元件封装中的互连

Country Status (7)

Country Link
US (1) US7838420B2 (enExample)
EP (1) EP2195840A4 (enExample)
JP (1) JP5397962B2 (enExample)
KR (1) KR20100065305A (enExample)
CN (1) CN101790788A (enExample)
TW (1) TWI451551B (enExample)
WO (1) WO2009032398A1 (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010245107A (ja) * 2009-04-01 2010-10-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US8407890B2 (en) * 2010-01-25 2013-04-02 Freescale Semiconductor Inc. Method of manufacting an electronic device module with integrated antenna structure
US8916421B2 (en) 2011-08-31 2014-12-23 Freescale Semiconductor, Inc. Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits
US9142502B2 (en) 2011-08-31 2015-09-22 Zhiwei Gong Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits
US8597983B2 (en) 2011-11-18 2013-12-03 Freescale Semiconductor, Inc. Semiconductor device packaging having substrate with pre-encapsulation through via formation
JP5834907B2 (ja) * 2011-12-28 2015-12-24 富士通株式会社 半導体装置、半導体装置の製造方法及び電子装置
US8810024B2 (en) * 2012-03-23 2014-08-19 Stats Chippac Ltd. Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
US9842798B2 (en) 2012-03-23 2017-12-12 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
US9837303B2 (en) 2012-03-23 2017-12-05 STATS ChipPAC Pte. Ltd. Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units
US10049964B2 (en) 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
CN103311141B (zh) * 2013-07-05 2016-01-20 北京理工大学 一种同轴垂直互连导电体的制作方法
US8822268B1 (en) 2013-07-17 2014-09-02 Freescale Semiconductor, Inc. Redistributed chip packages containing multiple components and methods for the fabrication thereof
US9362234B2 (en) 2014-01-07 2016-06-07 Freescale Semiconductor, Inc. Shielded device packages having antennas and related fabrication methods
US10354958B2 (en) 2014-10-01 2019-07-16 Nxp Usa, Inc. Through package circuit in fan-out wafer level package
US9666930B2 (en) 2014-10-23 2017-05-30 Nxp Usa, Inc. Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound
TWI652775B (zh) 2016-01-11 2019-03-01 矽品精密工業股份有限公司 電子封裝件
US10236260B2 (en) 2016-06-30 2019-03-19 Nxp Usa, Inc. Shielded package with integrated antenna
CN111034376B (zh) 2017-08-21 2023-02-21 株式会社村田制作所 电子部件的制造方法以及电子部件
US11557565B2 (en) 2020-10-06 2023-01-17 Nxp Usa, Inc. Semiconductor device assembly and method therefor
US11502054B2 (en) 2020-11-11 2022-11-15 Nxp Usa, Inc. Semiconductor device assembly and method therefor
CN114243287B (zh) * 2021-12-10 2025-08-29 上海微波技术研究所(中国电子科技集团公司第五十研究所) 毫米波相控阵天线阵列集成转换接头
US20240088068A1 (en) * 2022-09-08 2024-03-14 Nxp Usa, Inc. Semiconductor device with through package via and method therefor
US20250218977A1 (en) * 2023-12-29 2025-07-03 International Business Machines Corporation Coaxial through insulator via between chiplets

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56115553A (en) * 1980-02-18 1981-09-10 Fujitsu Ltd Method of mounting integrated circuit
JPH10303363A (ja) * 1997-04-30 1998-11-13 Sony Corp 電子部品及びその製造方法
US5949030A (en) * 1997-11-14 1999-09-07 International Business Machines Corporation Vias and method for making the same in organic board and chip carriers
US6054389A (en) * 1997-12-29 2000-04-25 Vanguard International Semiconductor Corporation Method of forming metal conducting pillars
US6081989A (en) * 1998-04-30 2000-07-04 Lockheed Martin Corporation Fabrication of circuit modules with a transmission line
JP2000252407A (ja) * 1999-03-04 2000-09-14 Hitachi Ltd マルチチップモジュール
JP2001094034A (ja) * 1999-09-27 2001-04-06 Nec Eng Ltd ハイブリッドicパッケージ
US6538210B2 (en) * 1999-12-20 2003-03-25 Matsushita Electric Industrial Co., Ltd. Circuit component built-in module, radio device having the same, and method for producing the same
US6444576B1 (en) 2000-06-16 2002-09-03 Chartered Semiconductor Manufacturing, Ltd. Three dimensional IC package module
JP2002343927A (ja) * 2000-07-12 2002-11-29 Hitachi Maxell Ltd 半導体モジュール及びその製造方法
US7190080B1 (en) 2000-10-13 2007-03-13 Bridge Semiconductor Corporation Semiconductor chip assembly with embedded metal pillar
JP2002184934A (ja) * 2000-12-13 2002-06-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
US6593644B2 (en) 2001-04-19 2003-07-15 International Business Machines Corporation System of a package fabricated on a semiconductor or dielectric wafer with wiring on one face, vias extending through the wafer, and external connections on the opposing face
JP2003188340A (ja) * 2001-12-19 2003-07-04 Matsushita Electric Ind Co Ltd 部品内蔵モジュールとその製造方法
US6753600B1 (en) 2003-01-28 2004-06-22 Thin Film Module, Inc. Structure of a substrate for a high density semiconductor package
JP4141857B2 (ja) * 2003-02-18 2008-08-27 日立マクセル株式会社 半導体装置
US6838776B2 (en) 2003-04-18 2005-01-04 Freescale Semiconductor, Inc. Circuit device with at least partial packaging and method for forming
US6921975B2 (en) 2003-04-18 2005-07-26 Freescale Semiconductor, Inc. Circuit device with at least partial packaging, exposed active surface and a voltage reference plane
JP2004327641A (ja) * 2003-04-24 2004-11-18 Tdk Corp 電子部品モジュール
DE10320646A1 (de) * 2003-05-07 2004-09-16 Infineon Technologies Ag Elektronisches Bauteil, sowie Systemträger und Nutzen zur Herstellung desselben
JP2005033141A (ja) * 2003-07-11 2005-02-03 Sony Corp 半導体装置及びその製造方法、疑似ウェーハ及びその製造方法、並びに半導体装置の実装構造
US7369718B2 (en) 2004-01-23 2008-05-06 Intel Corporation Package substrate pattern to accommodate optical waveguide
US20050167797A1 (en) 2004-01-29 2005-08-04 Advanpack Solutions Pte Ltd Structure package
JP4615962B2 (ja) * 2004-10-22 2011-01-19 ルネサスエレクトロニクス株式会社 半導体装置
US7476918B2 (en) * 2004-11-22 2009-01-13 Panasonic Corporation Semiconductor integrated circuit device and vehicle-mounted radar system using the same
CN101263752B (zh) * 2005-09-20 2010-06-09 株式会社村田制作所 内装元器件的组件的制造方法及内装元器件的组件

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US7838420B2 (en) 2010-11-23
EP2195840A4 (en) 2011-01-19
TWI451551B (zh) 2014-09-01
WO2009032398A1 (en) 2009-03-12
EP2195840A1 (en) 2010-06-16
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JP5397962B2 (ja) 2014-01-22
JP2010538463A (ja) 2010-12-09

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