ATE528796T1 - Elektrische verbindungsstruktur und verfahren zu ihrer bildung - Google Patents

Elektrische verbindungsstruktur und verfahren zu ihrer bildung

Info

Publication number
ATE528796T1
ATE528796T1 AT08718206T AT08718206T ATE528796T1 AT E528796 T1 ATE528796 T1 AT E528796T1 AT 08718206 T AT08718206 T AT 08718206T AT 08718206 T AT08718206 T AT 08718206T AT E528796 T1 ATE528796 T1 AT E528796T1
Authority
AT
Austria
Prior art keywords
solder
conductive pad
electrically conductive
electrically
forming
Prior art date
Application number
AT08718206T
Other languages
English (en)
Inventor
Stephen Buchwalter
Bruce Furman
Peter Gruber
Jae-Woong Nah
Da-Yuan Shih
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE528796T1 publication Critical patent/ATE528796T1/de

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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/50—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for positioning, orientation or alignment
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
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    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
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    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
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    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Combinations Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
AT08718206T 2007-04-11 2008-03-26 Elektrische verbindungsstruktur und verfahren zu ihrer bildung ATE528796T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/733,840 US7786001B2 (en) 2007-04-11 2007-04-11 Electrical interconnect structure and method
PCT/EP2008/053527 WO2008125440A1 (en) 2007-04-11 2008-03-26 Electrical interconnect structure and method of forming the same

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Publication Number Publication Date
ATE528796T1 true ATE528796T1 (de) 2011-10-15

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EP (1) EP2156465B1 (de)
JP (1) JP5186550B2 (de)
KR (1) KR20090103886A (de)
CN (1) CN101652847B (de)
AT (1) ATE528796T1 (de)
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Publication number Publication date
CN101652847A (zh) 2010-02-17
KR20090103886A (ko) 2009-10-01
US20100230475A1 (en) 2010-09-16
US8476773B2 (en) 2013-07-02
US20080251281A1 (en) 2008-10-16
EP2156465A1 (de) 2010-02-24
JP2010525558A (ja) 2010-07-22
WO2008125440A1 (en) 2008-10-23
TWI459505B (zh) 2014-11-01
US8541299B2 (en) 2013-09-24
US20100230474A1 (en) 2010-09-16
JP5186550B2 (ja) 2013-04-17
US8242010B2 (en) 2012-08-14
TW200849470A (en) 2008-12-16
US20100230143A1 (en) 2010-09-16
US7786001B2 (en) 2010-08-31
CN101652847B (zh) 2011-11-02
EP2156465B1 (de) 2011-10-12

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