JP5045688B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5045688B2 JP5045688B2 JP2009017479A JP2009017479A JP5045688B2 JP 5045688 B2 JP5045688 B2 JP 5045688B2 JP 2009017479 A JP2009017479 A JP 2009017479A JP 2009017479 A JP2009017479 A JP 2009017479A JP 5045688 B2 JP5045688 B2 JP 5045688B2
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- semiconductor element
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- insulating layer
- solder
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description
2・・・絶縁層
3・・・半導体素子側ランド
4・・・コア
5・・・はんだ
6・・・基板
7・・・基板側ランド
8・・・封止樹脂
9・・・半導体素子側突起部
10・・・ペースト
Claims (6)
- 内部に配線を含む絶縁層を表面に形成した半導体素子と該半導体素子を実装する基板と
を有し、前記半導体素子の絶縁層表面と前記基板表面に一定ピッチで設けられた複数の接
続用端子を有し、前記半導体素子の絶縁層表面の接続用端子と前記基板の接続用端子をは
んだ接合して前記半導体素子を前記基板に実装し、前記半導体素子と前記基板との接続部
を封止樹脂で封止した半導体装置において、
前記半導体素子と基板の接続部のはんだの内部に略球形のコアを設け、前記コアを前記はんだよりも大きな剛性をもつ材料から構成し、半導体素子の絶縁層表面に設けられた接続用端子と前記コアの間に配置されるはんだの厚さを絶縁層表面の接続用端子の端子ピッチの1/10以下とすると共に、前記半導体素子と基板の間に充填される封止樹脂のヤング率、線膨張係数および室温におけるはんだの降伏応力を各々、1GPa<封止樹脂のヤング率<9GPa、20ppm/k<封止樹脂の線膨張係数<60ppm/k、18MPa<室温におけるはんだの降伏応力<30MPaとしたことを特徴とする半導体装置。 - 請求項1に記載された半導体装置において、前記コアがニッケルメッキされた銅で構成されていることを特徴とする半導体装置。
- 請求項1に記載された半導体装置において、前記コアがニッケルで構成されていることを特徴とする半導体装置。
- 請求項1に記載された半導体装置において、前記コアがモリブデンで構成されていることを特徴とする半導体装置。
- 請求項1に記載された半導体装置において、前記半導体素子の絶縁層表面における接続用端子の接続方向厚さが基板側の接続用端子の接続方向厚さよりも厚いことを特徴とする半導体装置。
- 請求項5に記載された半導体装置において、前記半導体素子の絶縁層表面における接続用端子の接続方向厚さが幅方向厚さより小さい長方形断面を有することを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2009017479A JP5045688B2 (ja) | 2009-01-29 | 2009-01-29 | 半導体装置 |
US12/694,298 US8053908B2 (en) | 2009-01-29 | 2010-01-27 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
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US9978656B2 (en) * | 2011-11-22 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming fine-pitch copper bump structures |
US9219030B2 (en) | 2012-04-16 | 2015-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package on package structures and methods for forming the same |
DE102012109922B4 (de) | 2012-04-16 | 2020-04-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package-on-Package-Struktur und Verfahren zur Herstellung derselben |
US8928134B2 (en) | 2012-12-28 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package bonding structure and method for forming the same |
JP7251951B2 (ja) * | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
US20220108965A1 (en) * | 2020-10-06 | 2022-04-07 | Jabil Inc. | Low temperature, reworkable, and no-underfill attach process for fine pitch ball grid arrays having solder balls with epoxy and solder material |
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JP3250498B2 (ja) | 1997-09-26 | 2002-01-28 | イビデン株式会社 | 半田ボール及びプリント配線板 |
JP3897596B2 (ja) * | 2002-01-07 | 2007-03-28 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置と配線基板との実装体 |
JP2006344624A (ja) * | 2005-06-07 | 2006-12-21 | Hitachi Metals Ltd | 電子部品の製造方法 |
JP2007103737A (ja) * | 2005-10-05 | 2007-04-19 | Sharp Corp | 半導体装置 |
JP4986523B2 (ja) * | 2006-07-20 | 2012-07-25 | 三洋電機株式会社 | 半導体装置およびその製造方法 |
US7786001B2 (en) * | 2007-04-11 | 2010-08-31 | International Business Machines Corporation | Electrical interconnect structure and method |
JP2008277631A (ja) * | 2007-05-01 | 2008-11-13 | Renesas Technology Corp | 半導体装置 |
US7868457B2 (en) * | 2007-09-14 | 2011-01-11 | International Business Machines Corporation | Thermo-compression bonded electrical interconnect structure and method |
JP5212118B2 (ja) * | 2009-01-05 | 2013-06-19 | 日立金属株式会社 | 半導体装置およびその製造方法 |
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US20100193936A1 (en) | 2010-08-05 |
US8053908B2 (en) | 2011-11-08 |
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