JP5721742B2 - ウェハ構造の電気的結合 - Google Patents

ウェハ構造の電気的結合 Download PDF

Info

Publication number
JP5721742B2
JP5721742B2 JP2012544551A JP2012544551A JP5721742B2 JP 5721742 B2 JP5721742 B2 JP 5721742B2 JP 2012544551 A JP2012544551 A JP 2012544551A JP 2012544551 A JP2012544551 A JP 2012544551A JP 5721742 B2 JP5721742 B2 JP 5721742B2
Authority
JP
Japan
Prior art keywords
wafer
conductive
opening
forming
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012544551A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013513971A (ja
JP2013513971A5 (enExample
Inventor
リウ、リエンジュン
エイチ． カーリン、リサ
エイチ． カーリン、リサ
ジェイ． マグナス、アラン
ジェイ． マグナス、アラン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2013513971A publication Critical patent/JP2013513971A/ja
Publication of JP2013513971A5 publication Critical patent/JP2013513971A5/ja
Application granted granted Critical
Publication of JP5721742B2 publication Critical patent/JP5721742B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/0032—Packages or encapsulation
    • B81B7/007—Interconnections between the MEMS and external electrical signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H10W42/261—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions
    • H10W42/276—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons characterised by their shapes or dispositions the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2207/00—Microstructural systems or auxiliary parts thereof
    • B81B2207/09—Packages
    • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
    • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/17—Containers or parts thereof characterised by their materials
    • H10W76/18—Insulating materials, e.g. resins, glasses or ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Micromachines (AREA)
  • Dicing (AREA)
JP2012544551A 2009-12-15 2010-11-22 ウェハ構造の電気的結合 Expired - Fee Related JP5721742B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/638,424 2009-12-15
US12/638,424 US8138062B2 (en) 2009-12-15 2009-12-15 Electrical coupling of wafer structures
PCT/US2010/057624 WO2011081741A2 (en) 2009-12-15 2010-11-22 Electrical coupling of wafer structures

Publications (3)

Publication Number Publication Date
JP2013513971A JP2013513971A (ja) 2013-04-22
JP2013513971A5 JP2013513971A5 (enExample) 2014-01-16
JP5721742B2 true JP5721742B2 (ja) 2015-05-20

Family

ID=44143393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012544551A Expired - Fee Related JP5721742B2 (ja) 2009-12-15 2010-11-22 ウェハ構造の電気的結合

Country Status (5)

Country Link
US (1) US8138062B2 (enExample)
JP (1) JP5721742B2 (enExample)
CN (1) CN102656673B (enExample)
TW (1) TWI555069B (enExample)
WO (1) WO2011081741A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8637981B2 (en) * 2011-03-30 2014-01-28 International Rectifier Corporation Dual compartment semiconductor package with temperature sensor
US8633088B2 (en) * 2012-04-30 2014-01-21 Freescale Semiconductor, Inc. Glass frit wafer bond protective structure
US10246322B2 (en) 2013-03-15 2019-04-02 Versana Micro Inc. Distributed sensor system
CN103466541B (zh) * 2013-09-12 2016-01-27 上海矽睿科技有限公司 晶圆级封装方法以及晶圆
US9630832B2 (en) * 2013-12-19 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacturing
US9826630B2 (en) 2014-09-04 2017-11-21 Nxp Usa, Inc. Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof
KR20180032985A (ko) * 2016-09-23 2018-04-02 삼성전자주식회사 집적회로 패키지 및 그 제조 방법과 집적회로 패키지를 포함하는 웨어러블 디바이스
CN107827079B (zh) * 2017-11-17 2019-09-20 烟台睿创微纳技术股份有限公司 一种mems芯片的制作方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3613838B2 (ja) * 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
US6762072B2 (en) * 2002-03-06 2004-07-13 Robert Bosch Gmbh SI wafer-cap wafer bonding method using local laser energy, device produced by the method, and system used in the method
SG111972A1 (en) * 2002-10-17 2005-06-29 Agency Science Tech & Res Wafer-level package for micro-electro-mechanical systems
JP3905041B2 (ja) * 2003-01-07 2007-04-18 株式会社日立製作所 電子デバイスおよびその製造方法
US20040166662A1 (en) * 2003-02-21 2004-08-26 Aptos Corporation MEMS wafer level chip scale package
JP4551638B2 (ja) * 2003-08-01 2010-09-29 富士フイルム株式会社 固体撮像装置の製造方法
DE10350460B4 (de) * 2003-10-29 2006-07-13 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von mikromechanische und/ oder mikroelektronische Strukturen aufweisenden Halbleiterbauelementen, die durch das feste Verbinden von mindestens zwei Halbleiterscheiben entstehen, und entsprechende Anordnung
US7034393B2 (en) * 2003-12-15 2006-04-25 Analog Devices, Inc. Semiconductor assembly with conductive rim and method of producing the same
TWI236111B (en) * 2004-06-30 2005-07-11 Ind Tech Res Inst Apparatus and method for wafer level packaging
US7495462B2 (en) * 2005-03-24 2009-02-24 Memsic, Inc. Method of wafer-level packaging using low-aspect ratio through-wafer holes
TWI295081B (en) * 2006-01-12 2008-03-21 Touch Micro System Tech Method for wafer level package and fabricating cap structures
US20080131662A1 (en) * 2006-12-05 2008-06-05 Jordan Larry L Alignment of a cap to a MEMS wafer
US20080191334A1 (en) * 2007-02-12 2008-08-14 Visera Technologies Company Limited Glass dam structures for imaging devices chip scale package
US20080290430A1 (en) * 2007-05-25 2008-11-27 Freescale Semiconductor, Inc. Stress-Isolated MEMS Device and Method Therefor

Also Published As

Publication number Publication date
WO2011081741A2 (en) 2011-07-07
US8138062B2 (en) 2012-03-20
US20110143476A1 (en) 2011-06-16
CN102656673A (zh) 2012-09-05
TW201128691A (en) 2011-08-16
CN102656673B (zh) 2015-05-20
WO2011081741A3 (en) 2011-09-09
JP2013513971A (ja) 2013-04-22
TWI555069B (zh) 2016-10-21

Similar Documents

Publication Publication Date Title
CN102569194B (zh) 保护芯片级封装的t型接触免受潮
US9362139B2 (en) Method of making a semiconductor device having a functional capping
EP2727136B1 (en) Process for a sealed mems device with a portion exposed to the environment
TWI619669B (zh) 製造混合整合構件的方法，包含至少兩 mems 元件的混合整合構件
CN102656673B (zh) 晶片结构的电耦合
TWI628784B (zh) 應力釋放影像感測器封裝結構及方法
JP2001068580A (ja) ウエハパッケージの製造方法
CN104716050B (zh) 具有模塑通孔的半导体器件
US9972554B2 (en) Wafer level chip scale package having continuous through hole via configuration and fabrication method thereof
US9919915B2 (en) Method and system for MEMS devices with dual damascene formed electrodes
US10988373B2 (en) MEMS component having low-resistance wiring and method for manufacturing it
US8252695B2 (en) Method for manufacturing a micro-electromechanical structure
CN103523745A (zh) 基于Si导电柱的圆片级封装方法及其单片集成式MEMS芯片
CN115215290B (zh) Mems器件晶圆级封装方法及mems器件
CN107697882B (zh) 用于制造半导体器件的工艺以及相应半导体器件
CN108807197B (zh) 具有侧壁金属化部的芯片封装
US7911043B2 (en) Wafer level device package with sealing line having electroconductive pattern and method of packaging the same
US20040166662A1 (en) MEMS wafer level chip scale package
CN100463172C (zh) 半导体器件和半导体晶片及其制造方法
JP2011523203A (ja) 相互接続を伴うウェハレベルインテグレーションモジュール
US20080283989A1 (en) Wafer level package and wafer level packaging method
CN104112659B (zh) 晶片封装体、晶圆级晶片阵列及其制造方法
EP1199744A1 (en) Microcap wafer-level package
US7985697B2 (en) Wafer level package and method of fabricating the same
CN108417591B (zh) 高电性能的芯片封装结构及制作方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20131121

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140428

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140527

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140827

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140903

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140926

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150224

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150324

R150 Certificate of patent or registration of utility model

Ref document number: 5721742

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees