CN108807197B - 具有侧壁金属化部的芯片封装 - Google Patents
具有侧壁金属化部的芯片封装 Download PDFInfo
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- CN108807197B CN108807197B CN201810420220.8A CN201810420220A CN108807197B CN 108807197 B CN108807197 B CN 108807197B CN 201810420220 A CN201810420220 A CN 201810420220A CN 108807197 B CN108807197 B CN 108807197B
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Classifications
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Abstract
本发明公开了具有侧壁金属化部的芯片封装。一种制作方法,包括:形成具有多个沟槽(102)的载体晶片(100),每个沟槽(102)至少部分地覆盖有导电侧壁涂层(104);将半导体晶片(106)接合在载体晶片(100)的正侧(108)上,使得半导体晶片(106)的多个电子芯片(110)中的每个相对于沟槽(102)中的相应一个对准;形成导电连接结构(112),所述导电连接结构(112)至少部分地桥接导电侧壁涂层(104)和电子芯片(110)中的相应一个的集成电路元件(114)之间的间隙;以及去除载体晶片(100)的背侧(116)上的材料,以由此在沟槽(102)处将接合晶片(100、106)单一化为多个半导体器件(118)。
Description
技术领域
本发明涉及制作方法、中间产品、半导体器件和电子器件。
背景技术
用于电子芯片的诸如模制结构的常规半导体器件已经发展到封装不再显著妨碍电子芯片的性能的水平。而且,在晶片层级上处理电子芯片是用于高效产生电子芯片的已知程序。刻蚀电子芯片是用于从其去除材料的常规技术。在封装制作期间密封电子芯片可以保护它们免受环境影响。
在另一技术中,使用未密封的半导体器件,所述未密封的半导体器件包括其中具有集成电路的半导体主体。
仍然潜在地存在以下空间:在保持高处理准确性的同时,降低电子芯片的制作成本并且简化电子芯片的处理。而且,在诸如印刷电路板之类的器件载体上电气安装越来越小的半导体器件变得越来越具有挑战性。
发明内容
可能存在对一种制作能够适当地安装在器件载体上的紧凑半导体器件的可靠方法的需要。
根据示例性实施例,提供了一种制作方法,其包括:形成具有多个沟槽的载体晶片,每个沟槽至少部分地覆盖有导电侧壁涂层;将半导体晶片接合在载体晶片的正侧上,使得半导体晶片的多个电子芯片中的每个相对于沟槽中的相应一个对准;形成导电连接结构,该导电连接结构至少部分地桥接导电侧壁涂层和电子芯片中的相应一个的集成电路元件之间的间隙;以及去除载体晶片的背侧上的材料,以由此在沟槽处将接合晶片单一化为多个半导体器件。
根据另一示例性实施例,提供了一种中间产品,其包括:具有多个沟槽的载体晶片,每个沟槽至少部分地覆盖有导电侧壁涂层;半导体晶片,其接合在载体晶片的正侧上,使得半导体晶片的多个电子芯片中的每个相对于沟槽中的相应一个对准;以及导电连接结构,其至少部分地桥接导电侧壁涂层和电子芯片中的相应一个的集成电路元件之间的间隙。
根据又另一示例性实施例,提供了一种未密封的半导体器件,其包括:载体主体,所述载体主体具有至少部分地覆盖有导电侧壁涂层的侧壁;接合在载体主体的基壁(basewall)上的电子芯片;以及导电连接结构,其至少部分地桥接导电侧壁涂层和电子芯片的集成电路元件之间的间隙。
根据仍然另一示例性实施例,提供了一种电子器件,其包括器件载体和未密封的半导体器件,该未密封的半导体器件具有上面提及的特征,并且至少部分地通过导电连接结构的布置在侧壁涂层上的一部分(特别是通过焊接)安装在器件载体上。
根据示例性实施例,提供了一种用于未密封的半导体器件的制作架构,其允许以高度紧凑的方式产生这样的器件,而没有与在诸如印刷电路板之类的器件载体上安装这样的半导体器件有关的问题。为了实现这些有利效果,半导体器件可以由具有导电侧壁涂层的载体主体构成。在载体主体上安装具有至少一个集成电路元件的电子芯片。电子芯片和侧壁涂层之间的电连接至少部分地通过形成在中间的表面区域中的导电接触结构来完成。结果,获得了半导体器件,所述半导体器件能够也使用用于建立电接触的侧壁金属化部来安装在器件载体上。由于侧壁涂层的尺寸能够由形成在载体晶片(作为载体主体的预成型件)中的沟槽的深度自由限定,所以侧壁涂层的尺寸不会干扰器件载体上的电子芯片的横向尺寸的进一步小型化。由此,能够制作高度紧凑的半导体器件,而不涉及与在器件载体上安装这样的小半导体器件有关的问题。
有利地,这样的半导体器件可以以高效的分批程序形成,即基于载体晶片和半导体晶片。载体晶片可以限定由沟槽定界的各种载体主体。半导体主体可以包括多个电子芯片。通过形成沟槽,不仅能够容易地且在规模上不受约束地形成导电侧壁涂层,而且附加地,对载体晶片进行的直至沟槽底部的背侧减薄允许在接合晶片的沟槽处将各个半导体器件单一化。
考虑到单独提供载体晶片和半导体晶片的示例性实施例的概念,获得用于单独地关于两个晶片的特定特性和功能对所述两个晶片进行优化的高设计自由度。示例性实施例的另外的优点是提供如下半导体器件的机会:该半导体器件能够部分地在半导体器件的底表面上且部分地在半导体器件的侧壁表面上与器件载体焊料连接以用于提高电可靠性。考虑到半导体器件的连续小型化(特别是当被具体化为未密封的半导体片(例如为CSP封装)时),这是特别有利的,因为当封装的尺寸变小时仅在这样的封装的底表面上的焊料区能够变得极低。
另外的示例性实施例的描述
在本申请的上下文中,术语“未密封的半导体器件”可以特别地表示其中半导体芯片(即,其中能够形成至少一个单片集成电路的裸管芯)设有电耦合结构但不被模制化合物、层压件或另一密封剂密封的半导体芯片。然而,未密封的半导体器件可以覆盖有一层清漆等(其可以例如在单一化之后通过喷涂来施加)。还可能的是,未密封的半导体器件覆盖有(例如黑色)背侧保护箔(BSP箔)。
在下文中,将解释方法、中间产品、半导体器件和电子器件的另外的示例性实施例。
在实施例中,该方法包括通过以下步骤形成载体晶片:形成第一辅助沟槽并且使第一辅助沟槽至少部分地填充有电绝缘材料;形成与第一辅助沟槽横向相邻的第二辅助沟槽并且使第二辅助沟槽至少部分地填充有导电侧壁涂层;以及随后在相应两个相邻的第二辅助沟槽之间形成沟槽,使得相应沟槽的两个相对侧壁至少部分地覆盖有导电侧壁涂层。通过形成辅助沟槽的概念,能够确保沟槽的导电侧壁涂层被布置在导电侧壁隔离物的顶部上。由此,可以安全地防止从侧壁涂层到载体主体内部的不期望的电路径,由此改善电子性能。当载体主体的材料不完全是电介质(例如由半导体材料制成)时,这特别适用。
在实施例中,该方法包括形成比第一辅助沟槽和第二辅助沟槽到载体晶片中延伸得更深的主沟槽或分离沟槽。当形成比辅助沟槽更深的沟槽时,能够确保沟槽到载体晶片中的延伸比导电侧壁涂层的延伸更深。通过采取这种措施,能够确保的是,在随后的对载体晶片进行用于使各个半导体器件单一化的背侧减薄期间,不必须研磨导电侧壁涂层的导电材料,而是仅必须研磨载体晶片的同质材料。由此,可以形成高度可靠且可再生的导电侧壁涂层。
在实施例中,通过氧化载体晶片的暴露的壁、之后沉积另外的电绝缘材料,使第一辅助沟槽填充有电绝缘材料。辅助沟槽的侧壁的氧化可以通过热处理来完成,例如将硅氧化成氧化硅。为了进一步改善导电侧壁涂层和载体主体内部之间的电去耦合,可以实施例如由氮化硅制成的电绝缘材料的随后沉积。
在实施例中,通过氧化载体晶片的暴露的壁,使第二辅助沟槽部分地填充有电绝缘材料。因此,第二沟槽也可以通过其表面的热处理而被电绝缘,由此将载体晶片的材料转换成电绝缘氧化物(例如,硅到氧化硅)。
在实施例中,该方法包括:将半导体晶片接合在载体晶片的正侧上,使得集成电路元件暴露在半导体晶片的与半导体晶片的接合表面相对的主表面上。通过采取这种措施,能够确保集成电路元件不由于接合程序(其可能涉及某种粘合剂材料等)而损害、损坏或恶化。而且,这确保集成电路元件保持暴露在接合晶片的外表面处,这简化了仅沿接合晶片的表面的导电接触结构的形成。
在实施例中,该方法包括,特别地在形成导电连接结构之前,在半导体晶片中形成通孔,使得通孔与沟槽齐平。在晶片接合之后在半导体晶片中的通孔的这种形成确保了接合晶片到各个半导体器件的单一化能够在不采取任何另外的措施的情况下通过对接合晶片进行的简单背侧减薄(例如通过研磨)来完成。
在实施例中,该方法包括通过种子金属沉积、之后进行无电镀覆来形成导电连接结构。利用这样的程序,可能首先通过形成导电种子金属层来制备接合晶片的用于无电镀覆的表面。在这样的种子层上,能够促进通过无电镀覆形成足够厚的导电连接结构。这样的足够厚的导电连接结构允许电子芯片的集成电路元件与其上安装有半导体器件的器件载体的低欧姆耦合。
在实施例中,该方法包括通过胶合将半导体晶片接合在载体晶片上。因此,一层电绝缘胶或粘合剂可以夹在载体晶片和半导体晶片之间。这确保了载体主体和电子芯片之间的可靠连接,由此防止半导体器件的构成部分的不期望的层离。
在实施例中,该方法包括通过研磨去除载体晶片的材料。研磨是允许均匀地从接合晶片的背侧去除材料的机械磨耗技术。由此,能够确保均匀厚度的半导体器件的形成。作为研磨的替换方案,可以使用其他单一化技术,诸如锯开、切割、刻蚀、激光分离等。
在实施例中,半导体器件被配置为芯片级封装(CSP封装)。为了具有芯片级的资格,封装应该具有不大于管芯或电子芯片的面积的1.2倍的面积,并且其应该是单管芯直接表面贴装封装。可以应用于使封装具有CPS封装的资格的另一准则是其球间距应该不大于1mm。特别地,CSP封装可以具有比其电子芯片的尺寸大不多于20%的尺寸。CSP封装通常是未密封的,并且因此能够被设有非常小的厚度。因此,CSP封装高度适合于诸如可穿戴物、便携式装置、手表、智能眼镜等之类的应用。
在实施例中,载体主体的两个相对的侧壁至少部分地覆盖有导电侧壁涂层。通过使用半导体器件的两个相对侧壁来形成导电接触结构,可以实现与器件载体的低欧姆电耦合。而且,在使用两个相对的主表面用于电接触目的的情况下,甚至可以使复杂的电子功能成为可能。
在实施例中,半导体器件包括夹在导电侧壁涂层和载体主体之间的圆周电绝缘环形件。利用围绕半导体器件的整个周边的这样的环形电绝缘屏障,可以安全地防止半导体器件的不期望的电路径的可靠防止。由此,可以改善半导体器件的电性能。
在实施例中,半导体器件的表面具有不大于0.3 mm×0.15 mm的面积。因此,能够在单位半导体晶片面积的极高半导体器件产量的情况下,形成高度紧凑的半导体器件。同时,没有发生就在诸如PCB的器件载体上组装这样的半导体器件而言的问题,因为侧壁涂层能够支持这种安装。能够致使侧壁涂层相对较大,并且能够通过简单调整沟槽的深度来使侧壁涂层按比例缩放。
在实施例中,导电连接结构不间断地桥接导电侧壁涂层和集成电路元件之间的间隙。这样的实施例,其例如在图1至图12和图14中示出,具有建立非常可靠的电连接的优点。
在另一实施例中,导电连接结构仅桥接导电侧壁涂层和集成电路元件之间的间隙的一部分,使得中间(特别地,在不由导电材料而是由电绝缘材料构成的表面部分)保留不导电空间。这样的实施例,其例如在图13中示出,不需要调整工艺使得镀覆材料可靠地封闭剩余空间。然后可以通过焊料材料等来建立足够的电接触,所述焊料材料等在组装期间将器件载体与导电侧壁涂层和导电连接结构两者耦合。因此,即使不需要精确调整形成导电连接结构的工艺,也可以获得高电性能。
在实施例中,导电连接结构至少包括至少一个侧壁区段和垂直于至少一个侧壁区段延伸的至少一个基壁区段(其中在本申请的上下文中,基壁可以是正交于侧壁延伸、特别地水平延伸的顶壁和/或底壁)。因此,导电连接结构可以是成角度的结构并且可以具有可以直接连接到电子芯片的水平基壁区段。竖直侧壁区段可以连接到侧壁区段并且可以至少部分地位于侧壁涂层上。
在实施例中,器件载体是印刷电路板(见图13)。印刷电路板是半导体器件的适当安装基底,其中PCB的焊盘能够(至少也)电连接到半导体器件的侧壁涂层。然而,其他器件载体也是可能的,例如引线框架(见图14)。
在实施例中,电子器件包括将器件载体至少与导电连接结构的在侧壁涂层上的部分连接的焊料结构。因此,导电表面金属化部可以被配置为适于与器件载体的相对区建立焊料连接。
在实施例中,半导体器件部分地通过导电连接结构的没有布置在侧壁涂层上的一部分而安装在器件载体上。在这样的实施例中,半导体器件以非常稳定的方式机械地部分地安装在连接结构的侧壁部分上并且部分地安装在连接结构的基壁部分上。高度有利地,半导体器件的电连接也可以部分地通过侧壁金属化部并且部分地通过基壁金属化部来完成。这确保了所制作的电子器件就机械稳定性和电可靠性而言的高可靠性。
在实施例中,电子芯片被配置为控制器芯片、处理器芯片、存储器芯片、传感器芯片或微机电系统(MEMS)。在替换的实施例中,还可能的是,电子芯片被配置为功率半导体芯片。因此,电子芯片(诸如半导体芯片)可以用于例如汽车领域中的功率应用,并且例如可以具有至少一个集成绝缘栅双极型晶体管(IGBT)和/或至少一个另一类型的晶体管(诸如MOSFET、JFET等)和/或至少一个集成二极管。这样的集成电路元件可以例如以硅技术制成或基于宽带隙半导体(诸如碳化硅、氮化镓或硅上氮化镓)。半导体功率芯片可以包括一个或多个场效应晶体管、二极管、反相器电路、半桥、全桥、驱动器、逻辑电路、另外的器件等。
在一个实施例中,器件载体可以被配置为印刷电路板(PCB)。然而,也可以使用其他种类的器件载体。例如,半导体器件也可以安装在诸如芯片卡的其他器件载体上和/或其中。这样的芯片卡可以例如包括芯片或半导体器件和天线等。
作为形成电子芯片的基础的衬底或晶片,可以使用半导体衬底,优选地,硅衬底。替换地,可以提供氧化硅或另一绝缘体衬底。还可能实施锗衬底或III-V半导体材料。例如,示例性实施例可以以GaN或SiC技术来实施。
此外,示例性实施例可以利用标准半导体处理技术,诸如适当的刻蚀技术(包含各向同性和各向异性刻蚀技术,特别地,等离子体刻蚀、干法刻蚀、湿法刻蚀)、图案化技术(其可能涉及光刻掩模)、沉积技术(诸如化学气相沉积(CVD)、等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD),溅射等)。
根据结合附图得到的以下描述和所附权利要求,本发明的以上和其他目标、特征和优点将变得明显,在附图中,同样的部分或元件由同样的参考数字表示。
附图说明
附图,其被包含以提供对示例性实施例的进一步理解并且构成说明书的一部分,图示了示例性实施例。
在附图中:
图1至图4示出了在执行根据示例性实施例的制作半导体器件的方法期间获得的载体晶片的横截面视图。
图5至图10示出了在继续根据示例性实施例的制作半导体器件的方法期间获得的由接合在根据图4的载体晶片上的半导体晶片构成的中间产品的横截面视图。
图11示出了作为根据图1至图10的制作方法的结果而获得的根据示例性实施例的半导体器件的顶视图。
图12示出了根据图11的半导体器件的侧视图。
图13示出了根据示例性实施例的由作为表面贴装半导体器件的芯片级封装和作为用于半导体器件的器件载体的印刷电路板(PCB)构成的电子器件的横截面视图。
图14示出了根据另一示例性实施例的由芯片级封装半导体器件和作为用于半导体器件的器件载体的引线框架构成的电子器件的横截面视图。
具体实施方式
绘图中的图示是示意性的。
在更详细地描述另外的示例性实施例之前,将总结本发明人的一些基本考虑,已经基于所述基本考虑开发了提供能够处置和组装非常紧凑的半导体器件的制作概念的示例性实施例。
根据示例性实施例,未密封半导体器件(其也可以被配置为芯片级封装,CSP)除了基壁金属化部之外还设有侧壁金属化部,以用于简化半导体器件和器件载体之间的可靠导电连接的形成,在所述器件载体上可以安装半导体器件以用于形成电子器件。
电子设备的持续小型化需要更小的封装。常规地,用于半导体器件的最小封装具有约0.4 mm×0.2 mm的尺寸。对于无源器件,甚至考虑高达0.3 mm x 0.15 mm的尺寸。然而,存在对0.3 mm×0.15 mm的范围内的更小尺寸的有源半导体器件的需求。
然而,随着持续的进一步小型化,在诸如印刷电路板(PCB)的器件载体上可靠地安装和电连接半导体器件变得越来越困难。
为了甚至在半导体器件的持续小型化的情况下也满足以上描述的需求,示例性实施例在以芯片级封装(CSP)技术制作的封装的正面提供金属化部。更具体地,示例性实施例提供了允许形成侧壁金属化部的制作架构,该侧壁金属化部能够被引入以改善超小的有源半导体器件的安装。示例性实施例的要点是将封装生产部分与有源器件生产部分分离。这能够通过将半导体器件的生产划分为接合在一起的封装部分和器件部分来实现。这可以在将载体晶片-半导体晶片复合物单一化为多个未密封的半导体器件之前在晶片层级上执行。这导致仍然允许与诸如PCB的器件载体的可靠电连接和机械连接的进一步小型化的封装或半导体器件。因此,简单的PCB组装程序可以与进一步小型化以及因此更紧凑的半导体器件组合。
所提及的晶片-晶片复合物到各个半导体器件的分离以及用于电连接目的的侧壁金属化部可以基于用于侧壁金属化部以及用于限定单一化位置的金属填充沟槽的生产来执行。
在示例性实施例中,能够执行以下制作过程:
- 产生含有带有侧壁钝化部和侧壁金属化部的沟槽的载体晶片
- 组装载体晶片与半导体晶片(其也能够表示为有源器件晶片)
- 研磨半导体晶片
- 将侧壁金属化部与集成电路元件电连接
- 将载体晶片-半导体晶片复合物单一化为各个未密封的半导体器件。
这样的制作架构具有如下优点:所制作的半导体器件能够容易地安装在诸如PCB的器件载体上。而且,由于PCB或其他器件载体上的可见侧壁焊料,所描述的制作工艺允许容易的光学焊接检查。除此之外,所描述的制作工艺使得可能产生极小的封装,因为能够克服封装焊盘尺寸和距离的焊料限制。除此之外,由于每个半导体晶片的半导体芯片的可能大量增加(特别地,半导体晶片的每个半导体器件约0.3 mm×0.1 mm的面积消耗明显低于常规的0.6 mm×0.3 mm配置),因此能够实现非常低的生产工作。
图1至图4示出了在执行根据示例性实施例的制作半导体器件118的方法期间获得的载体晶片100的横截面视图。因为硅材料非常适合于诸如刻蚀、氧化等的处理,所以载体晶片100可以是硅晶片。替换地,载体晶片100可以由诸如玻璃的另一材料制成。后一个实施例具有如下优点:玻璃是可靠地电绝缘的,这简化了处理。
在所示出的实施例中,载体晶片100的处理包含辅助沟槽刻蚀、辅助沟槽氧化、辅助沟槽中的氮化硅沉积、利用氧化硅的辅助沟槽填充、附加辅助沟槽刻蚀、附加辅助沟槽氧化、以及金属沟槽填充程序。而且,可以使用金属填充的辅助沟槽中的氧化硅作为硬掩模来执行分离沟槽刻蚀。将在下文中更详细地描述所提及的程序。
参考图1,在(这里:硅)载体晶片100中(特别地通过刻蚀)形成多个第一辅助沟槽122,并且随后使第一辅助沟槽122填充有电绝缘材料120。更具体地,通过首先氧化载体晶片100的暴露的壁以用于在第一辅助沟槽122的暴露表面部分上形成氧化硅层,来使第一辅助沟槽122填充有电绝缘材料120。随后,可以将另外的电绝缘材料(优选地,氮化硅)沉积在氧化硅材料上。然后可以使第一辅助沟槽122的剩余的空的空间填充有另外的氧化硅材料。例如,第一辅助沟槽122的深度d可以在50 μm与300 μm之间的范围内,特别地,在175 μm与220 μm之间的范围内。
尽管在图1中未示出,但是第一辅助沟槽122及其利用电绝缘材料120的填充形成圆周封闭的环形结构(对照图11),该圆周封闭的环形结构在半导体器件118的操作期间防止不期望的电流路径。
参考图2,可以在根据图1的载体晶片100中形成(特别地,通过附加的刻蚀程序)第二辅助沟槽124。第二辅助沟槽124中的每个与第一辅助沟槽122中的相应一个横向相邻并且可以形成具有相同的深度d。随后使第二辅助沟槽124中的每个部分地填充有(例如,由铜材料制成的)导电侧壁涂层104并且部分地填充有另外的电绝缘材料。更精确地,通过氧化载体晶片100的暴露的壁(或通过沉积电介质材料),由此将载体晶片100的暴露的硅材料转换为氧化硅材料,来使第二辅助沟槽124填充有电绝缘材料120。与第一辅助沟槽122其电绝缘材料120相反,第二辅助沟槽124及其相应的电绝缘材料120不是以环形圆周环绕的方式布置的,而是具体地在其中期望导电连接的那些部分处被布置为隔离的侧壁涂层区域(对照图11)。如从图2能够得到的,第二辅助沟槽124被形成为使得两个邻近的侧壁涂层104被定位成彼此面对。如用参考数字196指示的,可选的电绝缘覆盖层(例如,氮化硅层)可以沉积在经处理的载体晶片100的外部上主表面上。
仍然参考图2,第二辅助沟槽124被形成为与先前介质填充的第一辅助沟槽122相邻。第二辅助沟槽124首先例如通过热处理将载体晶片100的暴露材料转换成相应的氧化物(例如将硅氧化成电介质氧化硅)而被电绝缘。随后,可以使剩余的第二辅助沟槽124填充有诸如铜的导电材料,由此形成侧壁涂层104。
参考图3,在图2的经处理的载体晶片100中形成多个沟槽102(其可以表示为分离沟槽或主沟槽)。这些沟槽102被形成为在两个相应地邻近的第二辅助沟槽124之间延伸,并且暴露它们的电绝缘材料120的横向端部部分(对照电绝缘表面层179)。相应的程序可以表示为切口刻蚀。沟槽102的深度D可以大于辅助沟槽122、124的深度d(D> d)。因此,沟槽102被形成为比第一辅助沟槽122和第二辅助沟槽124到载体晶片100中延伸得更深。例如,D可以比d深10 μm到20 μm。差异D-d应该足够大以确保在通过研磨程序进行划片期间各个半导体器件118的可靠分离(对照从图9到图10的转变),而不影响侧壁涂层104的导电材料。每个沟槽102至少部分地覆盖有导电侧壁涂层104,随后在相应两个相邻的第二辅助沟槽124之间形成沟槽102,使得相应沟槽102的两个相对侧壁至少部分地覆盖有导电侧壁涂层104。
如从图3能够得到的,主沟槽102形成在如根据图2处理的载体晶片100中,使得沟槽102桥接先前填充的辅助沟槽122、124。如从图1至图3能够得到的,沟槽102的深度D比辅助沟槽122、124的深度d更深,以便防止在下面参考图10描述的随后的单一化程序时导电侧壁涂层104的材料的不期望的去除。尽管在图3中未示出,但是主沟槽或分离沟槽102形成圆周环形结构(对照图11)并且限定了在制作的各个半导体器件118的外界限。
如图4所示出的,通过先前的辅助沟槽填充程序形成并且通过形成主沟槽102而暴露的电绝缘表面层179能够例如通过刻蚀移除。然而,替换地,还可能的是,电绝缘表面层179或氧化硅保护层到后来才被去除。结果,如此处理的沟槽102的两个相对的竖直壁由导电侧壁涂层104定界。
图5至图10示出了在继续根据示例性实施例的制作半导体器件118的方法期间获得的并且由接合在根据图4的载体晶片100上的半导体晶片106构成的中间产品134的横截面视图。
如将在下文中更详细描述的,半导体器件118的进一步生产包含:
- 在根据图4的载体晶片100的在其上要接合半导体晶片106的侧表面或主表面上进行胶合剂沉积和结构化
- 将半导体晶片106接合到载体晶片100
- 对半导体晶片106进行背侧研磨
- 从背侧进行硅结构化
- 从背侧进行氧化硅结构化
- 在背侧上进行种子金属沉积和结构化
- 从半导体晶片106去除钝化部以敞开载体晶片100的沟槽102
- 半导体晶片106(其也可以表示为器件晶片)和载体晶片100的金属上进行无电镀覆
- 使用通过研磨进行的划片分离载体晶片100-半导体晶片106复合物的各个半导体器件118。
参考图5,将半导体晶片106接合在载体晶片100的正侧108(即,根据图5的上主表面)上,使得半导体晶片106的多个电子芯片110中的每个相对于主沟槽或分离沟槽102中的相应一个对准,或者布置在沟槽102中的两个邻近沟槽之间。完成半导体晶片106在载体晶片100的正侧108上的接合,使得半导体晶片106的集成电路元件114可经由集成电路元件114的导电元件144从外部访问。集成电路元件114的导电元件144暴露在半导体晶片106的主表面126上,所述主表面126与半导体晶片106的在其处半导体晶片106被接合到载体晶片100的接合表面128相对。在所示出的实施例中,集成电路元件114包括与晶闸管串联的二极管。
电子芯片110的集成电路元件114的详细配置取决于电子应用,但是将针对参考图12的所描述的实施例更详细地解释。然而,应该说,半导体晶片106的电子芯片110包括电绝缘层140(在所描述的实施例中包括氧化硅)并且包括半导体层142(在所描述的实施例中包括硅)。出于电连接目的,在电绝缘层140以及半导体层142两者中提供导电元件144(例如钨插头)。
如已经提及的,容易产生的半导体晶片106通过经由粘合剂材料132粘合晶片100、106而晶片接合到根据图4准备的载体晶片100。所提及的在半导体晶片106和载体晶片100之间的接合通过该层电介质粘合剂材料132来完成。例如,粘合剂材料132可以在接合之前施加在载体晶片100的正侧108上或者半导体晶片106的接合表面128上。尽管不是强制性的,但是有利的是,该层粘合剂材料132在接合之前被图案化。可能的是,在与载体晶片100接合之后,例如通过研磨去除在半导体晶片106的上主表面126上的硅材料,以便暴露并且接近半导体晶片106的集成电路元件114。这样的厚度减小在接合之后能够更容易地完成,因为处置已经非常薄的半导体晶片106是困难的。
半导体晶片106的厚度L可以小于载体晶片100的深度D。例如,L可以在1 μm与50 μm之间的范围内,特别地,在12 μm与15 μm之间的范围内。
参考图6,在半导体晶片106中形成通孔130,使得通孔130与主沟槽或分离沟槽102齐平或对准。相应的刻蚀工艺可以是两阶段工艺,首先去除暴露的半导体层142的硅材料,之后去除电绝缘层140的氧化硅材料。例如,根据图6的通孔130的形成能够通过光刻和刻蚀程序来完成。替换地,这些通孔130也可以通过激光钻孔来形成。通孔130的形成可以去除半导体晶片106的在沟槽102的位置处的硅材料和氧化硅材料。该程序能够被认为是对接合晶片100、106至单独的半导体器件118的随后单一化的准备。所提及的单一化程序稍后将通过载体晶片100的背侧研磨来完成(对照图9到图10的转变)。
参考图7,执行导电材料的(例如由AlCu材料制成的)种子层146的种子金属沉积。这种种子金属沉积制备或形成随后的无电镀覆程序的基础(对照图9)。换句话说,图7示出了种子金属沉积的结果,其能够被认为是形成下面描述的导电接触结构112的第一部分工艺。如从图7能够得到的,在半导体晶片106的暴露的表面部分上执行种子层146的形成。
如在图7中用点线和参考数字195示意性地指示的,代替本实施例的所描述的工艺流程,在其他示例性实施例中可能的是,在用载体晶片100和半导体晶片106的沟槽102和通孔130连接载体晶片100和半导体晶片106的工艺期间,电绝缘膜(诸如氮化硅膜)保持存在于沟槽102上面。这样的电绝缘膜可以支持图案化种子层146的工艺。特别地,这样的电绝缘膜可以允许使用抗蚀剂执行图案化程序,所述抗蚀剂通过覆盖沟槽102的膜被可靠地防止流入沟槽102中。在形成通孔130期间,这样的氮化硅膜还可以用作用于氧刻蚀工艺的层。
图8中示出的结构是在可选的氮化硅去除工艺之后获得的。
参考图9,通过执行无电镀覆工艺来完成已经通过形成金属种子层146部分地完成的导电连接结构112的形成。通过这样的无电镀覆工艺,可以沉积诸如NiP/Pd/Au之类的导电材料。如从图9能够得到的,导电连接结构112被形成为将导电侧壁涂层104与电子芯片110的集成电路元件114电连接(特别地,用于完成到在制作的半导体器件118的背侧的电连接)。在所示出的实施例中,导电连接结构112完全桥接导电侧壁涂层104和电子芯片110的集成电路元件114之间的间隙。更精确地,导电连接结构112不间断地桥接或封闭导电侧壁涂层104和集成电路元件114之间的先前存在的间隙。描述性地说,生长导电连接结构112的材料以还延伸超过薄间隙,所述薄间隙先前已经存在于一方面侧壁涂层104与一方面金属种子层146之间。然而,替换地,还可能的是,通过无电镀覆生长的导电连接结构112的部分仅存在于侧壁涂层104和金属种子层146上,而不桥接所提及的间隙。图13中所图示的这样的实施例从电气视角来看也工作,因为当在容易制作的半导体器件118和(例如PCB类型)器件载体147之间建立焊料连接时,导电焊料结构148可以桥接这样的间隙(对照图13中的参考数字190)。例如,所提及的间隙可以具有若干微米的宽度,典型地2 μm至3 μm,在一些实施例中10 μm至15 μm。
如所描述的,在本实施例中,通过种子金属沉积(对照参考数字146)、之后进行无电镀覆来形成导电连接结构112(参见图9)。作为替换方案,导电连接结构112也可以在单个工艺中形成。因此,为了获得图9所示出的结构,执行无电镀覆程序。由此,将导电材料沉积在种子层146和导电侧壁涂层104以及中间的表面部分上,使得在所示出的实施例中,半导体晶片106的电子芯片110的集成电路元件114经由导电连接结构112与导电侧壁涂层104电耦合。
作为所描述的制作方法的结果,获得了如图9所示出的中间产品134。中间产品134包含具有多个沟槽102的载体晶片100。沟槽102中的每个部分地覆盖有相应的导电侧壁涂层104。半导体晶片106接合在载体晶片100的正侧108上,使得半导体晶片106的多个电子芯片110中的每个相对于沟槽102中的相应沟槽对准。导电连接结构112将导电侧壁涂层104与电子芯片110的集成电路元件114电连接。
参考图10,图9中所示出的中间产品134被分离成多个单独的半导体器件118,由此完成了所描述的在晶片层级上制作大量半导体器件118的高效高吞吐量分批程序。
在所描述的分离程序方面,从载体晶片100的背侧116去除载体晶片100的材料,以由此在沟槽102和相应的通孔130处将接合晶片100、106单一化为各个半导体器件118。在所示出的实施例中,通过研磨去除材料。因此,通过经由研磨程序执行划片而获得图10所示出的各个半导体器件118。
结果,获得根据示例性实施例的被配置为芯片级封装(CSP)的多个未密封的半导体器件118。半导体器件118中的每个包括先前的载体晶片100的区段,该区段可以表示为载体主体136。预见相应的载体主体136具有部分地覆盖有导电侧壁涂层104的侧壁,所述导电侧壁涂层104能够有利地用于将半导体器件118焊接在器件载体147上(对照图13和图14)。描述性地说,当在半导体器件118和器件载体147之间建立焊料连接时,导电连接结构112的侧壁部分可以用作助焊剂。当导电连接结构112的底侧部分跟随半导体器件118的持续小型化的趋势而变得相对较小时,这特别地保持。电子芯片110中的相应一个(半导体晶片106的先前形成部分)通过粘合剂材料132的相应区段接合在载体主体136的基壁(其可以特别地是垂直于侧壁的壁,诸如底壁或顶壁)上。导电连接结构112的相应部分还形成每个半导体器件118的一部分并且将导电侧壁涂层104与集成电路元件114中的相应一个电连接。如从图10能够得到的,载体主体136的两个相对的侧壁部分地覆盖有导电侧壁涂层104。
图11示出了作为根据图1至图10的制作方法的结果获得的根据图10的半导体器件118的顶视图。图12示出了根据图11的半导体器件118的侧视图。图11和图12因此示出了如从上面参考图1至图10描述的程序获得的单一化的半导体器件118。
如图11所示出的,半导体器件118包括由电绝缘材料120形成并且夹在导电侧壁涂层104与载体主体136之间的圆周封闭的电绝缘环形件138。导电连接结构112以及导电侧壁涂层104仅覆盖半导体器件118的两个相对的侧壁区域,而不是圆周地围绕整个载体主体136。然而,替换地,导电连接结构112以及导电侧壁涂层104也可以仅覆盖半导体器件118的一个侧壁区域或其三个或四个侧壁区域。通过在导电侧壁涂层104和导电连接结构112下方的圆周封闭的电绝缘环形件138确保的半导体器件118的完全圆周隔离高效地防止不期望的电路径,并且由此改善电可靠性。
如在图11中能够看到的,半导体器件118的表面面积能够小至0.3 mm×0.15 mm,而不损害半导体器件108的要通过焊接安装在器件载体147上的能力。
参考图12,将描述关于电子芯片110及其集成电路元件114的构造的另外的细节。应该强调的是,所描述的制作概念与关于电子芯片110和相应的集成电路元件114的非常不同的构造相兼容。如从图12能够得到的,提供p掺杂硅结构170和n掺杂硅结构172。此外,提供金属连接层174。
图12示出了:导电连接结构112包括竖直延伸的侧壁区段和水平延伸的基壁区段,基壁区段垂直于侧壁区段且随侧壁区段连续地延伸。导电连接结构112因此是成角度的连续结构。
图13示出根据示例性实施例的电子器件143的横截面视图。电子器件143由具体化为表面贴装的未密封的半导体器件118的芯片级封装和作为用于承载半导体器件118的器件载体147的印刷电路板(PCB)构成。半导体器件118与器件载体147之间的电耦合和机械耦合通过导电连接结构112将半导体器件118与板状器件载体147的暴露的顶部主表面上的器件载体焊盘150互连而完成。
根据图13,导电连接结构112仅桥接导电侧壁涂层104和集成电路元件114之间的间隙的部分,使得中间保留不导电空间190。然而,在建立器件载体147和半导体器件118之间的焊料连接期间,导电焊料结构148提供导电侧壁涂层104与一方面导电连接结构112的在间隙190上面的部分和导电连接结构112的在间隙190下面的部分之间的电耦合。换句话说,半导体器件118的底壁以及侧壁两者在这里用于提供用于建立半导体器件118和器件载体147之间的焊料连接的表面部分。当使半导体器件118进一步小型化时这促进了设计自由度,而不使当半导体器件118焊接在器件载体147上时的电可靠性恶化。根据图13,未密封的半导体器件118部分地通过导电连接结构112的覆盖侧壁涂层104并因此形成半导体器件118的侧表面的部分的部分,并且部分地通过导电连接结构112的在半导体器件118的底表面上的部分,机械安装在器件载体147上并且与器件载体147电耦合。在半导体器件118的侧表面和底表面两者上,焊料结构148将器件载体147与导电接触结构112连接。
如从图13能够得到的,半导体器件118在PCB类型器件载体147上的安装经由导电侧壁涂层104所支撑的导电接触结构112建立。因此,可能提供具有足够大的耦合面积的器件载体147,因为半导体器件118的侧壁接触的尺寸可以自由地确定并且经由沟槽102的深度D限定。同时,半导体器件118可以形成得高度紧凑,因为不需要保持硅面积大于制作技术必需的面积。
图14示出了根据另一示例性实施例的电子器件143和引线框架类型器件载体147的横截面视图。图14的实施例与图13的实施例的不同之处在于:图14的器件载体147被具体化为具有中心通孔152的铜引线框架。示出在图14的左手侧和右手侧的连接结构112的不同的分离区段分别通过焊料结构148(替换地,通过导电胶合剂连接)与引线框架类型器件载体147的不同区段连接。此外,如参考数字192所指示的,导电连接结构112不间断地将导电侧壁涂层104与相应的集成电路元件114电连接(而不是涉及间隙190)。
应该注意的是,术语“包括”不排除其他元件或特征,并且“一”或“一个”不排除多个。与不同实施例相关联地描述的元件也可以组合。还应该注意的是,参考符号不应该被解释为限制权利要求的范围。而且,本申请的范围不旨在限于说明书中描述的工艺、机器、制作和物质组成、手段、方法和步骤的特定实施例。因此,所附权利要求旨在将这样的工艺、机器、制作、物质组成、手段、方法或步骤包含在它们的范围内。
Claims (24)
1.一种用于制作半导体器件(118)的方法,包括:
·形成具有多个沟槽(102)的载体晶片(100),每个沟槽(102)至少部分地覆盖有导电侧壁涂层(104);
·将半导体晶片(106)接合在所述载体晶片(100)的正侧(108)上,使得所述半导体晶片(106)的多个电子芯片(110)中的每个相对于所述沟槽(102)中的相应一个对准;
·形成导电连接结构(112),所述导电连接结构(112)至少部分地桥接所述导电侧壁涂层(104)和所述电子芯片(110)中的相应一个的集成电路元件(114)之间的间隙;
·去除所述载体晶片(100)的背侧(116)上的材料,以由此在所述沟槽(102)处将接合晶片(100、106)单一化为多个半导体器件(118)。
2.根据权利要求1所述的方法,其中,所述方法包括通过以下步骤来形成所述载体晶片(100):
·形成第一辅助沟槽(122),并且使所述第一辅助沟槽(122)至少部分地填充有电绝缘材料(120);
·形成与所述第一辅助沟槽(122)横向相邻的第二辅助沟槽(124),并且使所述第二辅助沟槽(124)至少部分地填充有所述导电侧壁涂层(104);
·随后在相应两个相邻的第二辅助沟槽(124)之间形成所述沟槽(102),使得相应沟槽(102)的两个相对侧壁至少部分地覆盖有所述导电侧壁涂层(104)。
3.根据权利要求2所述的方法,其中,所述方法包括形成比所述第一辅助沟槽(122)和所述第二辅助沟槽(124)到所述载体晶片(100)中延伸得更深的所述沟槽(102)。
4.根据权利要求2或3所述的方法,其中,通过氧化所述载体晶片(100)的暴露的壁、之后沉积另外的电绝缘材料,来使所述第一辅助沟槽(122)填充有所述电绝缘材料(120)。
5.根据权利要求2或3所述的方法,其中,通过氧化所述载体晶片(100)的暴露的壁来使所述第二辅助沟槽(124)部分地填充有电绝缘材料(120)。
6.根据权利要求1至3中任一项所述的方法,其中,所述方法包括:将所述半导体晶片(106)接合在所述载体晶片(100)的正侧(108)上,使得所述集成电路元件(114)暴露在所述半导体晶片(106)的与所述半导体晶片(106)的接合表面(128)相对的主表面(126)上。
7.根据权利要求1至3中任一项所述的方法,其中,所述方法包括在所述半导体晶片(106)中形成通孔(130),使得所述通孔(130)与所述沟槽(102)齐平。
8.根据权利要求1至3中任一项所述的方法,其中,所述方法包括通过种子金属沉积、之后进行无电镀覆来形成所述导电连接结构(112)。
9.根据权利要求1至3中任一项所述的方法,其中,所述方法包括通过粘合剂材料(132)、特别是通过电绝缘粘合剂材料(132)将所述半导体晶片(106)接合在所述载体晶片(100)上。
10.根据权利要求1至3中任一项所述的方法,其中,所述方法包括通过研磨去除所述载体晶片(100)的材料。
11.根据权利要求1至3中任一项所述的方法,其中,所述导电连接结构(112)被形成为不间断地将所述导电侧壁涂层(104)与所述集成电路元件(114)电连接。
12.一种用于制作半导体器件的中间产品(134),包括:
·具有多个沟槽(102)的载体晶片(100),每个沟槽(102)至少部分地覆盖有导电侧壁涂层(104);
·半导体晶片(106),接合在所述载体晶片(100)的正侧(108)上,使得所述半导体晶片(106)的多个电子芯片(110)中的每个相对于所述沟槽(102)中的相应一个对准;
·导电连接结构(112),至少部分地桥接所述导电侧壁涂层(104)和所述电子芯片(110)中的相应一个的集成电路元件(114)之间的间隙。
13.一种根据权利要求1所述的方法制作的半导体器件(118),其中所述半导体器件(118)未密封,所述半导体器件(118)包括:
·载体主体(136),具有至少部分地覆盖有导电侧壁涂层(104)的侧壁;
·接合在所述载体主体(136)的基壁上的电子芯片(110);
·导电连接结构(112),至少部分地桥接所述导电侧壁涂层(104)和所述电子芯片(110)的集成电路元件(114)之间的间隙。
14.根据权利要求13所述的半导体器件(118),被配置为芯片级封装。
15.根据权利要求13或14所述的半导体器件(118),其中,所述载体主体(136)的两个相对侧壁至少部分地覆盖有所述导电侧壁涂层(104)。
16.根据权利要求13或14所述的半导体器件(118),包括布置在所述导电侧壁涂层(104)和所述载体主体(136)之间的圆周电绝缘环形件(138)。
17.根据权利要求13或14所述的半导体器件(118),其中,所述半导体器件(118)的表面具有不大于0.3mm×0.15mm的面积。
18.根据权利要求13或14所述的半导体器件(118),包括以下特征中的一个:
·所述导电连接结构(112)不间断地桥接所述导电侧壁涂层(104)和所述集成电路元件(114)之间的间隙;
·所述导电连接结构(112)仅桥接所述导电侧壁涂层(104)和所述集成电路元件(114)之间的间隙的部分,使得中间保留有不导电空间(190)。
19.根据权利要求13或14所述的半导体器件(118),其中,所述导电连接结构(112)至少包括垂直于所述导电侧壁涂层(104)延伸的基壁区段。
20.根据权利要求13或14所述的半导体器件(118),其中,所述导电连接结构(112)至少包括至少一个侧壁区段和垂直于至少一个侧壁区段延伸的至少一个基壁区段。
21.一种电子器件(143),包括:
·器件载体(147);以及
·根据权利要求13至20中任一项所述的未密封的半导体器件(118),所述未密封的半导体器件(118)至少部分地通过所述导电连接结构(112)的布置在所述侧壁涂层(104)上的一部分而安装在所述器件载体(147)上。
22.根据权利要求21所述的电子器件(143),其中,所述器件载体(147)包括由印刷电路板和引线框架组成的组中的一个。
23.根据权利要求21或22所述的电子器件(143),包括将所述器件载体(147)与所述导电连接结构(112)连接的焊料结构(148)。
24.根据权利要求21或22所述的电子器件(143),其中,所述半导体器件(118)部分地通过所述导电连接结构(112)的不布置在所述侧壁涂层(104)上的一部分而安装在所述器件载体(147)上。
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