Classifications

• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
  • B81B7/0032—Packages or encapsulation
  • B81B7/007—Interconnections between the MEMS and external electrical signals
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  • H01L24/93—Batch processes
  • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B2207/00—Microstructural systems or auxiliary parts thereof
  • B81B2207/09—Packages
  • B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
  • B81B2207/097—Interconnects arranged on the substrate or the lid, and covered by the package seal
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  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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  • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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  • H01L2924/16788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

• This invention relates in general to semiconductor devices and in particular to the electrical coupling of structures of two wafers.
• MEMS devices utilize cap wafers for providing a protective cavity for the MEMS device during operation.
• a MEMS device is a micro-electrical mechanical device that is typically manufactured, in some embodiments, with semiconductor device processes. Examples of MEMS devices include accelerometers, sensors, micro motors, and switches. In some examples, MEMS devices include parts (e.g. proof masses) that move during operation. Because of this movement, a cavity is used to protect the part while allowing for movement of the part.
• a cavity can be implemented by forming an opening in a cap wafer and bonding the cap wafer to the device wafer where the opening overlies the MEMS device. Afterwards, the cap wafer and device wafer are singulated to form the MEMS die.
• grounding coupling is made with wire bonds from the cap wafer to the device wafer, conductive vias through the cap wafer to the device wafer, or conductive bonding material between the cap wafer and the device wafer.
• Figures 1 -6 set forth views of various stages in the manufacture of a semiconductor device having a cap wafer structure according to an embodiment of the present invention.
• an electrical coupling from a cap wafer structure to a device wafer structure is made by forming an opening in the cap wafer in a scribe area to a conductive structure of the device wafer and then forming a conductive layer over the cap wafer including in the opening and on the sidewalls of the opening, where the conductive layer contacts the conductive structure of the device wafer. Afterwards, the cap and device wafers are singulated in the scribe area such that conductive material on the opening sidewalls remains for electrically coupling the cap wafer structure and the device wafer structure.
• Figure 1 is a partial cross sectional side view of a resultant wafer 101 that includes a device wafer 102 bonded to the cap wafer 105 with a bonding material 121 .
• bonding material 121 is a glass frit that is non conductive.
• other types of bonding material such as a conductive glass frit (e.g. with a conductive material such as lead) or solder may be used.
• the wafers are bonded together under temperature and pressure for a period of time to provide for a mechanically solid bond between the two wafers.
• the bond is a hermetic bond.
• Device wafer 1 02 includes a number of semiconductor devices (107, 109, 1 10) located on substrate 103 that were formed prior to the bonding of wafer 102 with wafer 105.
• these devices include structures made of semiconductor, conductive, and/or dielectric material formed by semiconductor manufacturing processes.
• Devices 107, 109, and 1 1 0 may include multiple layers of different materials that have been processed to form different structures.
• devices 107, 109, and 1 10 are multi axis accelerometers but in other embodiments, devices 107, 109, and 1 1 0 may be other types of MEMS devices such as other types of accelerometers, sensors, motors, or switches.
• devices 107, 109, and 1 10 may be other types of semiconductor devices such as integrated circuits, stand alone devices, or sensors.
• devices 107, 109, and 1 10 are formed by forming and processing different layers on substrate 1 03.
• Wafer 102 includes pads (1 13 and 1 15) for externally coupling devices
• Pads 1 13 and 1 15 are made of a conductive material (e.g. copper, aluminum, gold) that in one embodiment is wire bondable. Pads 1 13 and 1 1 5 are located on and in electrical contact with poly silicon structures 1 14 and 1 16 respectively.
• substrate 103 includes multiple conductive structures (not shown) for electrically coupling conductive structures of the semiconductor devices (107, 109, and 1 10) with pad support structures (1 14 and 1 16). For example, device 107 is electrically coupled to structure 1 14 and device 109 is electrically coupled to structure 1 1 6.
• substrate 103 includes a semiconductive material e.g. silicon with conductive structures and dielectric structures located in layers therein. In some embodiments, portions of the semiconductor material are selectively doped to be conductive. However, wafer 102 may have other configurations in other embodiments.
• a semiconductive material e.g. silicon with conductive structures and dielectric structures located in layers therein.
• portions of the semiconductor material are selectively doped to be conductive.
• wafer 102 may have other configurations in other embodiments.
• Device wafer 1 02 includes scribe conductive structures 1 08 and 1 12 that include portions located in scribe areas 141 and 143.
• a scribe area is an area of a wafer that is located between device areas of the wafer that will separated during singulation and includes a separation path.
• Structures 108 and 1 12 are made of a conductive material such as poly silicon or a metal.
• Each scribe structure (108 and 1 12) is electrically coupled to two devices (of devices 107, 109, and 1 10) by electrically conductive structures (not shown) located in substrate 103.
• conductive structure 1 12 is electrically coupled to device 109 and device 1 1 0.
• Wafer 102 also includes conductive structures 124 and 126 that are
• cap wafer 105 is made of a semiconductor material
• wafer 105 (e.g. silicon) and includes openings 131 , 133, 135, and 137 (e.g. formed by etching) for forming cavities for the structures of device wafer 1 02.
• the top side of wafer 105 is ground and polished to reduce the thickness of wafer 105.
• wafer 105 is ground to a reduced thickness in the range of 100-400 ⁇ .
• the cap may be ground to other thicknesses or may not be ground at all.
• cap wafer 105 may include devices such as MEMS devices or other semiconductor devices formed thereon.
• wafer 105 does not include openings 131 , 1 33, 135, and 137.
• Figure 2 is a partial cross sectional side view of resultant wafer 101 after openings (201 and 203) are made in wafer 105 to expose conductive structures (108 and 1 12) in scribe areas of wafer 102.
• the openings are made to a depth to ensure that wafer 105 and bonding material 121 are removed from locations over structures 108 and 1 1 2 to expose the conductive structures. Such a cut may include removing a top portion of structures 108 and 1 12.
• the openings are formed with a saw.
• openings 201 and 203 have widths 205 and 207 of 80 microns, but may be of other widths in other embodiments.
• bonding material 121 would not be formed in the areas of openings 201 and 203. In these areas, there would be a void between the cap wafer 105 and scribe conductive structures (108 and 1 12).
• bonding material in these areas may provide for a flush sidewall of the openings, as bonding material is located between the scribe conductive structure (1 08 and 1 12) and cap wafer 105.
• a flush side wall provides for a better subsequently formed of a conductive layer on the sidewall.
• openings 201 and 203 may be formed by other methods such as by a double saw cut, by laser, or by etching.
• Figure 3 is a partial cross sectional side view of resultant wafer 101 after a conductive layer 301 is formed over wafer 101 .
• layer 301 is made of a metal (e.g. copper aluminum, or gold). In one embodiment, layer has a thickness of 2 microns, but may have other thicknesses in other embodiments.
• Layer 301 is formed to have good step coverage on the sidewalls of openings 201 and 203 to provide a path for good electrical conductivity.
• layer 301 is formed by a metal deposition process such as a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, or other metal forming process.
• layer 301 may include multiple layers of different materials.
• FIG 4 is a partial cross sectional side view of resultant wafer 101 after openings (401 ) are formed over the pads (1 13 and 1 15) to expose the pads for subsequent testing.
• opening 401 is made with a double saw cut, but could be made by other methods in other embodiments (e.g. such as etching).
• wafer 101 is subjected to cleaning processes such as ashing to remove unwanted organic materials.
• the devices (107, 1 09, and 1 1 0) are tested for operability using test probes that contact the exposed pads (1 13 and 1 15).
• FIG. 5 is a partial cross sectional side view after resultant wafer 101 is singulated into separate die (529, 521 , 523, and 527).
• singulation is achieved by cutting wafer 101 in the scribe areas (141 and 143) and between the pads (e.g. 1 14 and 1 16).
• the wafer is cut with a saw, laser, or other wafer cutting tool.
• singulation can be performed by etching wafer 101 in the scribe areas.
• Each die (529, 521 , 523, and 527) includes a
• semiconductor device located in a cavity (formed from openings 131 , 135, and 137). In one embodiment, these cavities are hermetically sealed when wafer 102 was bonded to wafer 105.
• the saw paths (501 , 503, and 515) have widths
• the remaining portions of the scribe conductive structures (1 12, 108) form a seal ring along with conductive structures such as structures 124 and 126 for sealing the cavity of each die.
• Figure 6 is a top view of die 523 after singulation.
• layer 301 covers all of the top of die 523 except for that portion formed by opening 401 that exposes pads 1 15, 605, and 607.
• layer 301 covers three side walls (541 , 603, and 601 ) that were formed by the openings (e.g. 201 and 203) over the scribe areas. Consequently, for the embodiment shown, the there is a relatively large amount of conductive material coupling the two wafer portions together.
• the shape and coverage of layer 301 may be different. For example, it may only cover part of the side walls of the cap wafer structure or cover all four sides of the cap wafer structure. Also, there may be an opening in the top side of layer 301 for other external conductors.
• the resultant die can then be further packaged (e.g. in encapulant) either by itself or with other integrated circuit die.
• Layer 301 may be electrically coupled to a grounding terminal of the package.
• the resultant package can then be utilized in various electronic systems.
• the wafer bonding material 121 can be chosen for its bonding properties and without regard to its electrical conductivity properties.
• wire bonds are not needed for the ground coupling between the two wafers. This may also reduce the total height of a subsequent package in that cap wafer grounding wire bonds are typically made to the top surface of the cap wafer.
• forming a conductive layer on the side wall of a relatively large opening is technically easier than forming conductive vias through relatively smaller openings in a cap wafer.
• layer 301 can be configured to cover a large portion of the scribe area surrounding a die (e.g. 3 sides as shown in Figure 6), interior device area is not needed as with wire bonding or via formation.
• multiple wire bonds and conductive vias would be needed to get the same amount of conductive material as located on the sidewalls of the cap wafer structure for electrically coupling the wafers.
• the initial scribe openings could be made from the bottom of the device wafer 102 to expose conductive surfaces of the cap wafer 105.
• the conductive layer 301 would then be formed on the bottom side of device wafer 102 and would extend in the openings to contact the exposed conductive surfaces of cap wafer 105.
• the bottom of device wafer 102 may be ground down to reduce thickness after wafer bonding.
• One embodiment of the present invention includes a method for
• the method includes bonding the first wafer with the second wafer, forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer, and forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.
• Another embodiment includes a method for electrically coupling a cap wafer with a device wafer.
• the method includes bonding the cap wafer with the device wafer using a bonding material.
• the device wafer includes a substrate.
• the method includes forming an opening in the cap wafer and the bonding material in a scribe area of the device wafer to expose a surface of a conductive structure of the device wafer.
• the forming the opening through the cap wafer and the bonding material includes sawing through the cap wafer and the bonding material in the scribe area of the device wafer.
• the method includes forming a conductive layer overlying the cap wafer and the opening in the cap wafer such that the conductive layer forms an electrical contact with the conductive structure of the device wafer thereby electrically coupling the cap wafer with the device wafer.
• Another embodiment includes a method for electrically coupling a first wafer with a second wafer.
• the method includes bonding the first wafer with the second wafer using a bonding material, forming an opening in the first wafer and the bonding material in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer, and forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.
• the method includes separating the bonded wafers into a plurality of die.
• the separating includes removing material of a separation path of the second wafer, the separation path having a first width.
• the opening has a second width, and the first width and the second width are selected such that at least one portion of the conductive layer remains on at least one sidewall of a separated die and thereby provides electrical coupling between the first wafer and the second wafer.

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• 2009
  • 2009-12-15 US US12/638,424 patent/US8138062B2/en not_active Expired - Fee Related
• 2010
  • 2010-11-22 CN CN201080056932.8A patent/CN102656673B/zh not_active Expired - Fee Related
  • 2010-11-22 WO PCT/US2010/057624 patent/WO2011081741A2/en not_active Ceased
  • 2010-11-22 JP JP2012544551A patent/JP5721742B2/ja not_active Expired - Fee Related
  • 2010-12-06 TW TW099142440A patent/TWI555069B/zh not_active IP Right Cessation

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