JP2013254918A - 半導体パッケージ及びその製造方法 - Google Patents
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Abstract
【解決手段】本半導体パッケージは、半導体チップの回路形成面及び側面を封止する第1最外絶縁層と、前記第1最外絶縁層の前記回路形成面側の面である第1面上に交互に所定数積層された配線層及び絶縁層と、前記第1面上に最後に積層された絶縁層上に形成された最外配線層と、前記最後に積層された絶縁層上に形成され、前記最外配線層を選択的に被覆する第2最外絶縁層と、を有し、前記最外配線層は、補強用配線パターンと、前記補強用配線パターンと電気的に接続されたビア配線と、を含み、前記ビア配線は、前記補強用配線パターン及び前記最後に積層された絶縁層を貫通するように設けられ、前記補強用配線パターンよりも前記半導体チップ側に配置された配線層と電気的に接続されており、前記補強用配線パターンの主成分の熱膨張係数は、前記配線層の主成分の熱膨張係数と前記半導体チップの主成分の熱膨張係数との間の値とされている。
【選択図】図1
Description
[第1の実施の形態に係る半導体パッケージの構造]
図1は、第1の実施の形態に係る半導体パッケージを例示する断面図である。図1を参照するに、半導体パッケージ10は、半導体チップ20と、配線層30と、絶縁層33と、配線層34と、絶縁層35と、配線層36と、絶縁層37と、配線層40と、ソルダーレジスト層48と、外部接続端子49とを有する。
次に、第1の実施の形態に係る半導体パッケージの製造方法について説明する。図3〜図5は、第1の実施の形態に係る半導体パッケージの製造工程を例示する図である。
第1の実施の形態の変形例1では、補強用配線パターンをソルダーレジスト層48側の最外配線層の一部にのみ設ける例を示す。なお、第1の実施の形態の変形例1において、既に説明した実施の形態と同一構成部品についての説明は省略する。
第1の実施の形態の変形例2では、半導体チップ20側に露出する第1電極パッドの主成分の熱膨張係数を、配線層36等の主成分の熱膨張係数と半導体チップ20の主成分の熱膨張係数との間の値にする例を示す。なお、第1の実施の形態の変形例2において、既に説明した実施の形態と同一構成部品についての説明は省略する。
図1において配線層34と絶縁層35との間に、更に絶縁層と配線層を交互に1層ずつ挿入し、全部で4つの配線層及び5つの絶縁層(1つのソルダーレジスト層を含む)を有する半導体パッケージについて、反りのシミュレーションを実行した。但し、配線パターン41の材料は42アロイとした。このパッケージを、便宜上、半導体パッケージ10Cとする。
0Cは、配線パターン41の主成分を銅とした半導体パッケージ10Dと比べて、パッケージ全体及びチップ搭載エリアの何れにおいても、反りを低減できることが確認された。又、配線パターン41の厚さが30μmでも反りを低減できることが確認された。配線パターン41の厚さを30μmよりも厚くすることにより、更に反りを低減できることが予想される。なお、表1の反りのイメージにおいて、色の濃い部分が大きく反っている部分である。
20 半導体チップ
21 半導体基板
22 電極パッド
23 突起電極
30、34、36、40、60、70 配線層
31、42、72 第1層
32、43、73 第2層
33、35、37 絶縁層
33x、33y、35x、37x、37y ビアホール
41、61 配線パターン
44、63 ビア配線
48 ソルダーレジスト層
48x、52x 開口部
49 外部接続端子
51 支持体
52 レジスト層
410 部材
420 板状体
430 金属層
Claims (8)
- 半導体チップの回路形成面及び側面を封止する第1最外絶縁層と、
前記第1最外絶縁層の前記回路形成面側の面である第1面上に交互に所定数積層された配線層及び絶縁層と、
前記第1面上に最後に積層された絶縁層上に形成された最外配線層と、
前記最後に積層された絶縁層上に形成され、前記最外配線層を選択的に被覆する第2最外絶縁層と、を有し、
前記最外配線層は、補強用配線パターンと、前記補強用配線パターンと電気的に接続されたビア配線と、を含み、
前記ビア配線は、前記補強用配線パターン及び前記最後に積層された絶縁層を貫通するように設けられ、前記補強用配線パターンよりも前記半導体チップ側に配置された配線層と電気的に接続されており、
前記補強用配線パターンの主成分の熱膨張係数は、前記配線層の主成分の熱膨張係数と前記半導体チップの主成分の熱膨張係数との間の値とされている半導体パッケージ。 - 前記補強用配線パターンは、第1層と、前記第1層の上面及び下面を被覆する第2層と、を有し、
前記第1層を構成する成分の熱膨張係数は、前記配線層の主成分の熱膨張係数と前記半導体チップの主成分の熱膨張係数との間の値とされており、
前記第2層は、前記第1層とは異なる成分を含む請求項1記載の半導体パッケージ。 - 前記第2層の主成分は、前記配線層の主成分と同一である請求項2記載の半導体パッケージ。
- 前記最外配線層は、前記補強用配線パターンの周囲に配置された配線パターンを含み、
前記配線パターンの主成分は、前記配線層の主成分と同一である請求項1乃至3の何れか一項記載の半導体パッケージ。 - 前記第1最外絶縁層の第1面の反対面である第2面から露出する電極パッドを有し、
前記電極パッドの主成分の熱膨張係数は、前記配線層の主成分の熱膨張係数と前記半導体チップの主成分の熱膨張係数との間の値とされている請求項1乃至4の何れか一項記載の半導体パッケージ。 - 前記補強用配線パターンの主成分のヤング率は、前記配線層の主成分のヤング率と前記半導体チップの主成分のヤング率との間の値とされている請求項1乃至5の何れか一項記載の半導体パッケージ。
- 支持体の一方の面に半導体チップを回路形成面を上にして配置する工程と、
前記半導体チップの回路形成面及び側面を封止するように、前記支持体の一方の面に第1最外絶縁層を形成する工程と、
前記第1最外絶縁層の前記回路形成面側の面である第1面上に、配線層及び絶縁層を交互に所定数積層する工程と、
前記第1面上に最後に積層された絶縁層上に、補強用配線パターンと、前記補強用配線パターンと電気的に接続されたビア配線と、を含む最外配線層を形成する工程と、
前記最後に積層された絶縁層上に、前記最外配線層を選択的に被覆する第2最外絶縁層を形成する工程と、を有し、
前記最外配線層を形成する工程は、
前記補強用配線パターン及び前記最後に積層された絶縁層を貫通し、前記補強用配線パターンよりも前記半導体チップ側に配置された配線層の上面を露出する貫通孔を形成する工程と、
前記貫通孔内に前記ビア配線を形成する工程と、を含み、
前記補強用配線パターンの主成分の熱膨張係数は、前記配線層の主成分の熱膨張係数と前記半導体チップの主成分の熱膨張係数との間の値とされている半導体パッケージの製造方法。 - 前記最外配線層を形成する工程は、
前記最後に積層された絶縁層を硬化する前に、前記最後に積層された絶縁層上に前記補強用配線パターンとなる部材を配置する工程と、
前記最後に積層された絶縁層を硬化させると共に、前記部材を前記最後に積層された絶縁層上に固着する工程と、
前記部材をパターニングして前記補強用配線パターンを形成する工程と、を含む請求項7記載の半導体パッケージの製造方法。
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