JP2013081079A5 - - Google Patents

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Publication number
JP2013081079A5
JP2013081079A5 JP2011220077A JP2011220077A JP2013081079A5 JP 2013081079 A5 JP2013081079 A5 JP 2013081079A5 JP 2011220077 A JP2011220077 A JP 2011220077A JP 2011220077 A JP2011220077 A JP 2011220077A JP 2013081079 A5 JP2013081079 A5 JP 2013081079A5
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JP
Japan
Prior art keywords
impedance
output
circuit
adjustment
adjustable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2011220077A
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English (en)
Japanese (ja)
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JP2013081079A (ja
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Publication date
Application filed filed Critical
Priority to JP2011220077A priority Critical patent/JP2013081079A/ja
Priority claimed from JP2011220077A external-priority patent/JP2013081079A/ja
Priority to US13/644,388 priority patent/US9018973B2/en
Publication of JP2013081079A publication Critical patent/JP2013081079A/ja
Publication of JP2013081079A5 publication Critical patent/JP2013081079A5/ja
Priority to US14/691,367 priority patent/US20150226825A1/en
Withdrawn legal-status Critical Current

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JP2011220077A 2011-10-04 2011-10-04 半導体装置 Withdrawn JP2013081079A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2011220077A JP2013081079A (ja) 2011-10-04 2011-10-04 半導体装置
US13/644,388 US9018973B2 (en) 2011-10-04 2012-10-04 Semiconductor device
US14/691,367 US20150226825A1 (en) 2011-10-04 2015-04-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011220077A JP2013081079A (ja) 2011-10-04 2011-10-04 半導体装置

Publications (2)

Publication Number Publication Date
JP2013081079A JP2013081079A (ja) 2013-05-02
JP2013081079A5 true JP2013081079A5 (enExample) 2014-12-11

Family

ID=48527123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011220077A Withdrawn JP2013081079A (ja) 2011-10-04 2011-10-04 半導体装置

Country Status (2)

Country Link
US (2) US9018973B2 (enExample)
JP (1) JP2013081079A (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4159553B2 (ja) * 2005-01-19 2008-10-01 エルピーダメモリ株式会社 半導体装置の出力回路及びこれを備える半導体装置、並びに、出力回路の特性調整方法
WO2015149283A1 (zh) * 2014-04-01 2015-10-08 京微雅格（北京）科技有限公司 一种集成电路芯片及其阻抗校准方法
KR20160004581A (ko) * 2014-07-03 2016-01-13 에스케이하이닉스 주식회사 반도체 장치 및 그 동작 방법
US9766831B2 (en) 2015-10-14 2017-09-19 Micron Technology, Inc. Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination
KR102558044B1 (ko) * 2016-06-14 2023-07-20 에스케이하이닉스 주식회사 비교회로 및 반도체장치
US10348270B2 (en) 2016-12-09 2019-07-09 Micron Technology, Inc. Apparatuses and methods for calibrating adjustable impedances of a semiconductor device
US10193711B2 (en) 2017-06-22 2019-01-29 Micron Technology, Inc. Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device
US10615798B2 (en) 2017-10-30 2020-04-07 Micron Technology, Inc. Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance
US10205451B1 (en) 2018-01-29 2019-02-12 Micron Technology, Inc. Methods and apparatuses for dynamic step size for impedance calibration of a semiconductor device
KR102693786B1 (ko) * 2019-02-18 2024-08-13 에스케이하이닉스 주식회사 캘리브레이션 회로 및 이를 포함하는 반도체 장치
US10747245B1 (en) 2019-11-19 2020-08-18 Micron Technology, Inc. Apparatuses and methods for ZQ calibration
JP6916929B1 (ja) * 2020-05-25 2021-08-11 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． インピーダンスキャリブレーション回路
CN115273953B (zh) * 2022-07-27 2025-08-01 长鑫存储技术有限公司 阻抗校准电路
KR20240016238A (ko) 2022-07-27 2024-02-06 창신 메모리 테크놀로지즈 아이엔씨 임피던스 교정 회로
CN116718898A (zh) * 2023-08-11 2023-09-08 深圳市思远半导体有限公司 芯片、芯片的输入输出多态检测方法及相关设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6836142B2 (en) * 2002-07-12 2004-12-28 Xilinx, Inc. Asymmetric bidirectional bus implemented using an I/O device with a digitally controlled impedance
KR100543211B1 (ko) * 2003-04-29 2006-01-20 주식회사 하이닉스반도체 온 디램 터미네이션 저항 조정 회로 및 그 방법
JP4205741B2 (ja) 2006-08-21 2009-01-07 エルピーダメモリ株式会社 キャリブレーション回路を有する半導体装置及びキャリブレーション方法
JP4205744B2 (ja) 2006-08-29 2009-01-07 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、半導体装置の出力特性調整方法
JP4920512B2 (ja) * 2007-07-04 2012-04-18 エルピーダメモリ株式会社 キャリブレーション回路及びこれを備える半導体装置、並びに、データ処理システム
JP2010171793A (ja) * 2009-01-23 2010-08-05 Elpida Memory Inc 半導体装置
JP2010183243A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc 半導体装置
JP5642935B2 (ja) * 2009-02-19 2014-12-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． インピーダンス調整回路及びこれを備える半導体装置
JP2012049838A (ja) * 2010-08-27 2012-03-08 Elpida Memory Inc 半導体装置およびその特性調整方法
US8624641B1 (en) * 2010-11-03 2014-01-07 Pmc-Sierra, Inc. Apparatus and method for driving a transistor

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