JP2013080971A - ウェハ裏面のキャパシタを有する半導体デバイスを形成する方法 - Google Patents
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- 239000003990 capacitor Substances 0.000 title claims abstract description 257
- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 74
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 230000008569 process Effects 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000001465 metallisation Methods 0.000 claims description 24
- 239000007769 metal material Substances 0.000 claims description 17
- 239000003989 dielectric material Substances 0.000 claims description 13
- 239000011810 insulating material Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 139
- 238000004519 manufacturing process Methods 0.000 description 60
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 230000000903 blocking effect Effects 0.000 description 18
- 238000013461 design Methods 0.000 description 14
- 239000011241 protective layer Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 125000006850 spacer group Chemical group 0.000 description 10
- 238000012545 processing Methods 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000009429 electrical wiring Methods 0.000 description 5
- 238000002513 implantation Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000002210 silicon-based material Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- FFBGYFUYJVKRNV-UHFFFAOYSA-N boranylidynephosphane Chemical compound P#B FFBGYFUYJVKRNV-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000011269 treatment regimen Methods 0.000 description 1
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Abstract
【解決手段】 本発明の方法は、その前面の活性シリコン層とその裏面のバルク・シリコン層との間に挿入された埋込み絶縁層を有する、SOI基板を準備するステップと、SOI基板の前面から埋込み絶縁層を貫通して延びる埋込みコンタクト・プラグを含む集積回路を、SOI基板の前記前面に形成するステップと、裏面エッチング・プロセスを実施してバルク・シリコン層内にトレンチを形成し、埋込みコンタクト・プラグの端部を埋込み絶縁層の裏表面に露出させるステップと、第1キャパシタ・プレートと、第2キャパシタ・プレートと、該第1及び第2キャパシタ・プレートの間に挿入されたキャパシタ誘電体層とを含むキャパシタをトレンチ内に形成するステップとを含み、第1キャパシタ・プレートは、埋込みコンタクト・プラグの露出した端部に接触するように形成される。
【選択図】 図2
Description
MIM(金属−絶縁材−金属)キャパシタ、互いにかみ合った構造などを用いる他の従来技術を用いて、高品質のキャパシタを形成することができるが、チップ前面の貴重なシリコン面積を消費する犠牲を払うことになる。
20:シリアライザ回路
21:トランスミッタ
30:デシリアライザ回路
31:レシーバ
40:伝送媒体
50:DCブロッキング・キャパシタ
70:オンチップESD(静電放電)デバイス
80、81:入力パッド(I/Oパッド)
90、91:はんだボール
100,300:半導体ICチップ
104,105:回路デバイス(ダイオード)
104a:p型ドープ領域
104b:n型ドープ領域
106:回路デバイス(MOSトランジスタ)
106a:ポリシリコン・ゲート構造部
106b/106c:ソース/ドレイン拡散領域
110:半導体基板(ウェハ)
110a、310a:薄いシリコン層(上部シリコン層)
110b、310b:埋め込み酸化物(BOX)層
110c、310c:バルク・シリコン層
115:STI(shallow trench isolation)領域
118:電気配線
120:コンタクト・プラグ
125、225:誘電体/絶縁材料
130:保護層
140、141、142:ウェハ貫通コンタクト・プラグ
200:ハードマスク・パターン
200a、200b、230a、235,313:開口部
210:トレンチ
215、240:側壁スペーサ
225:誘電体層(キャパシタ誘電体層)
221、222、251、252:キャパシタ電極(キャパシタ・プレート)
230:エッチング・マスク
236:裏面プラグ
250:導電性材料
253:分離トレンチ
260,311、312:保護層(保護絶縁層)
310:既製のSOIウェハ構造体(半導体SOI基板)
314:残りのマスク・パターン
315:絶縁柱
320,330:保護膜
340:裏面コンタクト
341、342、343:上部キャパシタ・プレート
345:誘電体膜
350:金属材料(第2金属層)
351、352:底部キャパシタ・プレート
360:絶縁材料層
361:トレンチ
Claims (7)
- 半導体デバイスを形成する方法であって、
その前面の活性シリコン層とその裏面のバルク・シリコン層との間に挿入された埋込み絶縁層を有する、SOI基板を準備するステップと、
前記SOI基板の前記前面から前記埋込み絶縁層を貫通して延びる埋込みコンタクト・プラグを含む集積回路を、前記SOI基板の前記前面に形成するステップと、
裏面エッチング・プロセスを実施して前記バルク・シリコン層内にトレンチを形成し、前記埋込みコンタクト・プラグの端部を前記埋込み絶縁層の裏表面に露出させるステップと、
第1キャパシタ・プレートと、第2キャパシタ・プレートと、該第1及び第2キャパシタ・プレートの間に挿入されたキャパシタ誘電体層とを含むキャパシタを前記トレンチ内に形成するステップとを含み、
前記第1キャパシタ・プレートは、前記埋込みコンタクト・プラグの前記露出した端部に接触するように形成される、方法。 - 前記キャパシタを前記形成するステップは、
第1メタライゼーション・プロセスを実施して前記トレンチを金属材料で部分的に充填し前記第1キャパシタ・プレートを形成するステップと、
前記第1キャパシタ・プレートの上に誘電体材料の共形層を堆積させるステップと、
第2メタライゼーション・プロセスを実施して前記トレンチの残りの部分を金属材料で充填し前記第2キャパシタ・プレートを形成するステップとを含む、請求項1に記載の方法。 - 前記第1メタライゼーション・プロセスを実施する前に、前記トレンチの側壁の内表面を絶縁材料で覆うステップをさらに含む、請求項2に記載の方法。
- 前記バルク・シリコン層を貫通するビア・ホールを形成して第2埋込みコンタクト・プラグの端部を前記埋込み絶縁層の前記裏表面に露出させるステップと、
前記第2メタライゼーション・プロセス中に前記ビア・ホールを金属材料で充填して前記第2キャパシタ・プレートを前記第2埋込みコンタクト・プラグに接続するステップとをさらに含む、請求項2に記載の方法。 - 前記裏面エッチング・プロセスを実施する前に、前記SOI基板の前記裏面を、該SOI基板の該裏面の元の厚さの10%から80%までの範囲の厚さまで薄化するステップをさらに含む、請求項1に記載の方法。
- 半導体デバイスを形成する方法であって、
その前面の活性シリコン層とその裏面のバルク・シリコン層との間に挿入された埋込み絶縁層を有するSOI基板を準備するステップと、
前記バルク・シリコン層内に、キャパシタ領域の境界を画定する絶縁フレーム構造部を形成するステップと、
集積回路を前記SOI基板の前記前面に形成するステップであって、前記集積回路は前記SOI基板の前記裏面の前記キャパシタ領域に位置合せされた、前記SOI基板の前記前面から前記埋込み絶縁層を貫通して延びる埋込みコンタクト・プラグを含む、ステップと、
裏面エッチング・プロセスを実施して、前記バルク・シリコン層内に前記絶縁フレーム構造部によって境界付けられたトレンチを形成し、前記埋込みコンタクト・プラグの端部を前記埋込み絶縁層の裏面表面に露出させるステップと、
第1キャパシタ・プレートと、第2キャパシタ・プレートと、該第1及び第2キャパシタ・プレートの間に挿入されたキャパシタ誘電体層とを含むキャパシタを前記トレンチ内に形成するステップとを含み、
前記第1キャパシタ・プレートは、前記埋込みコンタクト・プラグの前記露出した端部に接触するように形成される、方法。 - 前記キャパシタを前記形成するステップは、
第1メタライゼーション・プロセスを実施して前記トレンチを金属材料で部分的に充填し、前記第1キャパシタ・プレートを形成するステップと、
前記第1キャパシタ・プレートの上に誘電体材料の共形層を堆積させるステップと、
第2メタライゼーション・プロセスを実施して前記トレンチの残りの部分を金属材料で充填し、前記第2キャパシタ・プレートを形成するステップとを含む、請求項6に記載の方法。
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US11/443,394 US7473979B2 (en) | 2006-05-30 | 2006-05-30 | Semiconductor integrated circuit devices having high-Q wafer back-side capacitors |
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JP2013019016A Expired - Fee Related JP5602892B2 (ja) | 2006-05-30 | 2013-02-02 | ウェハ裏面のキャパシタを有する半導体デバイスを形成する方法 |
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CN (1) | CN101410969B (ja) |
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Cited By (3)
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JP2014236131A (ja) * | 2013-06-03 | 2014-12-15 | 富士通株式会社 | 半導体装置およびその製造方法。 |
JP2016526285A (ja) * | 2013-05-06 | 2016-09-01 | クアルコム,インコーポレイテッド | 静電放電ダイオード |
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JP5602892B2 (ja) | 2014-10-08 |
CN101410969A (zh) | 2009-04-15 |
WO2007137969A1 (en) | 2007-12-06 |
EP2030232A1 (en) | 2009-03-04 |
CN101410969B (zh) | 2011-09-14 |
EP2030232B1 (en) | 2014-05-21 |
US20070278619A1 (en) | 2007-12-06 |
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US20090111235A1 (en) | 2009-04-30 |
TW200812063A (en) | 2008-03-01 |
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