JP2012516556A - 減少させられたゲート電極ピッチを有する非対称トランジスタのための段階的なウエル注入 - Google Patents
減少させられたゲート電極ピッチを有する非対称トランジスタのための段階的なウエル注入 Download PDFInfo
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
洗練された半導体デバイスにおいて、非対称ウエル注入に基いて非対称トランジスタ構造が得られる一方で傾斜注入プロセスは回避し得る。この目的のために、段階的なレジストマスクのような段階的な注入マスクが形成されてよく、段階的な注入マスクは、非対称トランジスタのソース側と比較してドレイン側で高いイオン遮断能力を有していてよい。例えば、非対称構造は、高度な性能向上を伴う非傾斜注入プロセスに基いて得ことができ、また考慮されている技術標準にかかわりなく完成され得る。
【選択図】図2e
Description
Claims (22)
- トランジスタの第1のトランジスタ内部区域の上方で第1のイオン遮断能力を有し且つ前記トランジスタの第2のトランジスタ内部区域の上方で前記第1のイオン遮断能力とは異なる第2のイオン遮断能力を有する注入マスクを半導体領域の上方に形成することと、
前記注入マスクに基いて前記第1及び第2のトランジスタ内部区域内へウエルドーパント種を注入することと、
前記半導体領域のチャネル区域であって前記第1及び第2のトランジスタ内部区域を横方向に分離しているチャネル区域の上方にゲート電極を形成することとを備えた方法。 - 前記注入マスクを形成することは、前記第1及び第2のトランジスタ内部区域の上方で変化する厚みを伴うイオン遮断材質を形成することを備えている請求項1の方法。
- 前記イオン遮断材質はレジスト材質からなる請求項2の方法。
- 前記イオン遮断材質は非レジスト材質からなる請求項2の方法。
- 前記イオン遮断材質を形成することは、前記非レジスト材質を堆積させることと、前記非レジスト材質のエッチング挙動を局部的に変化させることと、前記局部的に変化するエッチング挙動に基いて前記非レジスト材質の材質を除去することとを備えている請求項4の方法。
- 前記エッチング挙動を局部的に変化させることは、前記非レジスト材質の上方にレジストマスクを形成することと、前記エッチング挙動を局部的に変化させる注入種を導入するように傾斜角を用いて注入プロセスを実行することとを備えている請求項5の方法。
- 前記注入マスクを形成するのに先立ち分離構造を形成することを更に備えた請求項1の方法であって、前記分離構造は前記半導体領域の横方向の輪郭を明らかにしている方法。
- 前記注入マスクを形成した後に分離構造を形成することを更に備えた請求項1の方法であって、前記分離構造は前記半導体領域の横方向の輪郭を明らかにしている方法。
- 前記第1のイオン遮断能力は前記第2のイオン遮断能力よりも小さく、前記第1のトランジスタ内部区域はソース領域に対応している請求項1の方法。
- 前記注入マスクは第2のトランジスタの第1のトランジスタ内部区域及び第2のトランジスタ内部区域を覆い、前記第2のトランジスタの前記第1のトランジスタ内部区域の上方の前記注入マスクのイオン遮断能力は、前記第2のトランジスタの前記第2のトランジスタ内部区域の上方の前記注入マスクのイオン遮断能力と実質的に等しい請求項1の方法。
- 前記トランジスタの前記第1及び第2のトランジスタ内部区域並びに前記第2のトランジスタの前記第1及び第2のトランジスタ内部区域は、前記トランジスタと前記第2のトランジスタの間に中間分離構造を設けることなしに前記半導体領域内に形成される請求項10の方法。
- 前記注入マスクを用いることなしに前記第1及び第2のトランジスタ内部区域内に前記ウエルドーパント種の付加的部分を注入することを更に備えた請求項1の方法。
- 前記ゲート電極は概ね50ナノメートル(nm)以下の長さを有するように形成される請求項1の方法。
- トランジスタの第1のトランジスタ内部区域及び第2のトランジスタ内部区域の上方に、段階的注入マスクであって前記第1のトランジスタ内部区域に対する第1のイオン遮断能力と前記第2のトランジスタ内部区域に対する前記第1のイオン遮断能力よりも大きな第2の増大されたイオン遮断能力とを提供する段階的注入マスクを形成することと、
前記注入マスクに基いて前記第1及び第2のトランジスタ内部区域内にウエルドーパント種を導入することと、
非対称なトランジスタ構造を得るように前記第1及び第2のトランジスタ内部区域に基いてドレイン及びソース領域を形成することとを備えた方法。 - 前記段階的注入マスクを形成した後にゲート電極を形成することを更に備えた請求項14の方法。
- 前記段階的注入マスクを形成するのに先立ちゲート電極を形成することを更に備えた請求項14の方法。
- 前記第1のトランジスタ内部区域内にソース領域が形成される請求項14の方法。
- チャネル領域の上方に形成されるゲート電極構造と、
ウエル領域内に形成されるドレイン領域及びソース領域とを備えた半導体デバイスであって、
前記ドレイン領域及び前記ソース領域は前記チャネル領域によって横方向に分離されており、ウエルドーパント種のドーパント濃度は横方法において前記チャネル領域からトランジスタの少なくともソース側での前記トランジスタの周辺まで増大している半導体デバイス。 - 前記ウエルドーパント種の前記濃度は前記チャネル領域内の横方向で徐々に変化する請求項18の半導体デバイス。
- ウエルドーパント種の全量は前記ドレイン領域と比較して前記ソース領域において高い請求項18の半導体デバイス。
- 前記ゲート電極構造のゲート長は概ね50ナノメートル以下である請求項18の半導体デバイス。
- 前記ウエル領域内に形成される第2のトランジスタのドレイン及びソース領域を更に備えた請求項18の半導体デバイスであって、前記第2のトランジスタの前記ドレイン及びソース領域は、前記第2のトランジスタのソース側及びドレイン側に設けられるウエルドーパント種に関して実質的に等しい構造を有している半導体デバイス。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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DE102009006885A DE102009006885B4 (de) | 2009-01-30 | 2009-01-30 | Verfahren zum Erzeugen einer abgestuften Wannenimplantation für asymmetrische Transistoren mit kleinen Gateelektrodenabständen und Halbleiterbauelemente |
DE102009006885.6 | 2009-01-30 | ||
US12/692,886 US9449826B2 (en) | 2009-01-30 | 2010-01-25 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches |
US12/692,886 | 2010-01-25 | ||
PCT/EP2010/000491 WO2010086153A1 (en) | 2009-01-30 | 2010-01-27 | Graded well implantation for asymmetric transistors having reduced gate electrode pitches |
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JP2012516556A true JP2012516556A (ja) | 2012-07-19 |
JP2012516556A5 JP2012516556A5 (ja) | 2013-03-07 |
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JP2011546706A Pending JP2012516556A (ja) | 2009-01-30 | 2010-01-27 | 減少させられたゲート電極ピッチを有する非対称トランジスタのための段階的なウエル注入 |
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US (1) | US9449826B2 (ja) |
JP (1) | JP2012516556A (ja) |
KR (1) | KR20110119768A (ja) |
CN (1) | CN102365714A (ja) |
DE (1) | DE102009006885B4 (ja) |
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---|---|---|---|---|
US8664027B2 (en) | 2011-02-11 | 2014-03-04 | Varian Semiconductor Associates, Inc. | LED mesa sidewall isolation by ion implantation |
FR2977071A1 (fr) * | 2011-06-27 | 2012-12-28 | St Microelectronics Crolles 2 | Procede de dopage controle d'un substrat semi-conducteur |
CN102903649A (zh) * | 2011-07-28 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | 一种选择离子注入的光刻胶厚度方法 |
US8481381B2 (en) | 2011-09-14 | 2013-07-09 | Globalfoundries Inc. | Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures |
CN104779138A (zh) * | 2014-01-14 | 2015-07-15 | 北大方正集团有限公司 | 一种横向变掺杂区的制作方法以及晶体管 |
DE102015112729A1 (de) * | 2015-08-03 | 2017-02-09 | Infineon Technologies Dresden Gmbh | Halbleiterbauelement mit einem lateral variierenden Dotierprofil und ein Verfahren zu dessen Herstellung |
CN106935502A (zh) * | 2015-12-29 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其制造方法 |
CN106992117A (zh) * | 2017-03-30 | 2017-07-28 | 北京燕东微电子有限公司 | 一种SiC结势垒肖特基二极管的制作方法 |
JP7024626B2 (ja) * | 2018-06-27 | 2022-02-24 | 三菱電機株式会社 | 半導体装置、半導体装置の製造方法 |
US11862691B2 (en) | 2019-11-01 | 2024-01-02 | Raytheon Company | Field effect transistor having field plate |
CN111969061A (zh) * | 2020-08-12 | 2020-11-20 | 无锡先仁智芯微电子技术有限公司 | 一种ldmos结构及其制作方法 |
CN112951917B (zh) * | 2021-01-29 | 2022-11-15 | 中国电子科技集团公司第十三研究所 | 一种氧化镓场效应晶体管及制备方法 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60227474A (ja) * | 1984-04-26 | 1985-11-12 | Nec Corp | Mosトランジスタの製造方法 |
JPS6249667A (ja) * | 1985-06-19 | 1987-03-04 | エツセジ−エツセ ミクロエレツトロニカソチエタ ペル アノニマ | Nチヤンネルmosトランジスタおよびその製造方法 |
JPH07130681A (ja) * | 1993-10-30 | 1995-05-19 | Sony Corp | 半導体装置の配線接続孔の形成方法装置 |
JPH08153803A (ja) * | 1994-11-30 | 1996-06-11 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JPH08250446A (ja) * | 1995-02-16 | 1996-09-27 | Samsung Electron Co Ltd | グレートーンマスク、これを用いたパターンの形成方法およびイオン注入方法 |
JPH11274491A (ja) * | 1998-03-20 | 1999-10-08 | Nippon Foundry Inc | 半導体装置及びその製造方法 |
JPH11340174A (ja) * | 1998-05-28 | 1999-12-10 | Nippon Steel Corp | 半導体装置の製造方法 |
JP2000082682A (ja) * | 1998-08-18 | 2000-03-21 | Siemens Ag | 半導体―絶縁層の製造方法及びそれを有する素子の製造方法 |
US6096610A (en) * | 1996-03-29 | 2000-08-01 | Intel Corporation | Transistor suitable for high voltage circuit |
JP2001044409A (ja) * | 1999-08-03 | 2001-02-16 | Sony Corp | 固体撮像素子の製造方法 |
JP2007501518A (ja) * | 2003-08-04 | 2007-01-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 非対称の側壁スペーサの形成方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3769109A (en) | 1972-04-19 | 1973-10-30 | Bell Telephone Labor Inc | PRODUCTION OF SiO{11 {11 TAPERED FILMS |
EP0338110B1 (en) | 1988-04-21 | 1993-03-17 | International Business Machines Corporation | Method for forming a photoresist pattern and apparatus applicable with said method |
US5371394A (en) | 1993-11-15 | 1994-12-06 | Motorola, Inc. | Double implanted laterally diffused MOS device and method thereof |
US6015991A (en) * | 1997-03-12 | 2000-01-18 | International Business Machines Corporation | Asymmetrical field effect transistor |
US6624030B2 (en) * | 2000-12-19 | 2003-09-23 | Advanced Power Devices, Inc. | Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region |
BR0109069A (pt) * | 2000-03-08 | 2004-12-07 | Ntu Ventures Pte Ltd | Processo para fabricar um circuito integrado fotÈnico |
US6507058B1 (en) | 2000-10-17 | 2003-01-14 | Semiconductor Components Industries Llc | Low threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same |
US6518136B2 (en) * | 2000-12-14 | 2003-02-11 | International Business Machines Corporation | Sacrificial polysilicon sidewall process and rapid thermal spike annealing for advance CMOS fabrication |
US7719054B2 (en) * | 2006-05-31 | 2010-05-18 | Advanced Analogic Technologies, Inc. | High-voltage lateral DMOS device |
US20060040450A1 (en) | 2004-08-20 | 2006-02-23 | Sharp Laboratories Of America, Inc. | Source/drain structure for high performance sub 0.1 micron transistors |
US7144797B2 (en) * | 2004-09-24 | 2006-12-05 | Rensselaer Polytechnic Institute | Semiconductor device having multiple-zone junction termination extension, and method for fabricating the same |
DE102005009023B4 (de) * | 2005-02-28 | 2011-01-27 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zum Herstellen einer Gateelektrodenstruktur mit asymmetrischen Abstandselementen und Gateestruktur |
US7485892B2 (en) * | 2005-12-29 | 2009-02-03 | Carl Zeiss Meditec Inc. | Optical broadband emitters and methods of making the same |
-
2009
- 2009-01-30 DE DE102009006885A patent/DE102009006885B4/de active Active
-
2010
- 2010-01-25 US US12/692,886 patent/US9449826B2/en active Active
- 2010-01-27 JP JP2011546706A patent/JP2012516556A/ja active Pending
- 2010-01-27 CN CN2010800141885A patent/CN102365714A/zh active Pending
- 2010-01-27 KR KR1020117019971A patent/KR20110119768A/ko not_active Application Discontinuation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60227474A (ja) * | 1984-04-26 | 1985-11-12 | Nec Corp | Mosトランジスタの製造方法 |
JPS6249667A (ja) * | 1985-06-19 | 1987-03-04 | エツセジ−エツセ ミクロエレツトロニカソチエタ ペル アノニマ | Nチヤンネルmosトランジスタおよびその製造方法 |
JPH07130681A (ja) * | 1993-10-30 | 1995-05-19 | Sony Corp | 半導体装置の配線接続孔の形成方法装置 |
JPH08153803A (ja) * | 1994-11-30 | 1996-06-11 | Sony Corp | 半導体装置及び半導体装置の製造方法 |
JPH08250446A (ja) * | 1995-02-16 | 1996-09-27 | Samsung Electron Co Ltd | グレートーンマスク、これを用いたパターンの形成方法およびイオン注入方法 |
US6096610A (en) * | 1996-03-29 | 2000-08-01 | Intel Corporation | Transistor suitable for high voltage circuit |
JPH11274491A (ja) * | 1998-03-20 | 1999-10-08 | Nippon Foundry Inc | 半導体装置及びその製造方法 |
JPH11340174A (ja) * | 1998-05-28 | 1999-12-10 | Nippon Steel Corp | 半導体装置の製造方法 |
JP2000082682A (ja) * | 1998-08-18 | 2000-03-21 | Siemens Ag | 半導体―絶縁層の製造方法及びそれを有する素子の製造方法 |
JP2001044409A (ja) * | 1999-08-03 | 2001-02-16 | Sony Corp | 固体撮像素子の製造方法 |
JP2007501518A (ja) * | 2003-08-04 | 2007-01-25 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 非対称の側壁スペーサの形成方法 |
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DE102009006885B4 (de) | 2011-09-22 |
DE102009006885A1 (de) | 2010-08-12 |
CN102365714A (zh) | 2012-02-29 |
US20100193866A1 (en) | 2010-08-05 |
US9449826B2 (en) | 2016-09-20 |
KR20110119768A (ko) | 2011-11-02 |
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