JP2012216773A - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP2012216773A
JP2012216773A JP2012015679A JP2012015679A JP2012216773A JP 2012216773 A JP2012216773 A JP 2012216773A JP 2012015679 A JP2012015679 A JP 2012015679A JP 2012015679 A JP2012015679 A JP 2012015679A JP 2012216773 A JP2012216773 A JP 2012216773A
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JP
Japan
Prior art keywords
layer
copper
wiring
coupling agent
tin alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012015679A
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English (en)
Japanese (ja)
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JP2012216773A5 (enExample
Inventor
Yuichiro Shimizu
雄一郎 清水
Akira Fukazawa
亮 深澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2012015679A priority Critical patent/JP2012216773A/ja
Priority to US13/433,680 priority patent/US9040832B2/en
Publication of JP2012216773A publication Critical patent/JP2012216773A/ja
Publication of JP2012216773A5 publication Critical patent/JP2012216773A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/389—Improvement of the adhesion between the insulating substrate and the metal by the use of a coupling agent, e.g. silane

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2012015679A 2011-03-29 2012-01-27 配線基板及びその製造方法 Pending JP2012216773A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2012015679A JP2012216773A (ja) 2011-03-29 2012-01-27 配線基板及びその製造方法
US13/433,680 US9040832B2 (en) 2011-03-29 2012-03-29 Wiring substrate and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2011072694 2011-03-29
JP2011072694 2011-03-29
JP2012015679A JP2012216773A (ja) 2011-03-29 2012-01-27 配線基板及びその製造方法

Publications (2)

Publication Number Publication Date
JP2012216773A true JP2012216773A (ja) 2012-11-08
JP2012216773A5 JP2012216773A5 (enExample) 2015-01-22

Family

ID=46925753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012015679A Pending JP2012216773A (ja) 2011-03-29 2012-01-27 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US9040832B2 (enExample)
JP (1) JP2012216773A (enExample)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015230901A (ja) * 2014-06-03 2015-12-21 三菱瓦斯化学株式会社 樹脂積層体及びプリント配線板
JP2017069399A (ja) * 2015-09-30 2017-04-06 凸版印刷株式会社 インターポーザ、半導体装置及び半導体装置の製造方法
WO2017094470A1 (ja) 2015-11-30 2017-06-08 凸版印刷株式会社 多層プリント配線基板及びその製造方法
JP2021097131A (ja) * 2019-12-17 2021-06-24 イビデン株式会社 ドライフィルムレジスト、及び、プリント配線板の製造方法
KR20220111637A (ko) * 2021-02-02 2022-08-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 제조 비용 감소 및 성능 증가를 위한 다층 스택을 갖는 상측 전도성 구조물
JPWO2022201563A1 (enExample) * 2021-03-25 2022-09-29
EP4319510A4 (en) * 2021-03-22 2024-10-02 Panasonic Intellectual Property Management Co., Ltd. WIRING BODY, MOUNTING SUBSTRATE, WIRING TRANSFER BOARD WITH WIRING, INTERMEDIATE MATERIAL FOR WIRING BODY, AND METHOD FOR MANUFACTURING WIRING BODY

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5602584B2 (ja) * 2010-10-28 2014-10-08 新光電気工業株式会社 配線基板及びその製造方法
US8945990B2 (en) * 2012-04-24 2015-02-03 Infineon Technologies Ag Chip package and method of forming the same
CN103717009A (zh) * 2012-10-08 2014-04-09 苏州卓融水处理科技有限公司 一种无核封装基板种子层附着力的方法
JP6322885B2 (ja) * 2012-11-01 2018-05-16 味の素株式会社 プリント配線板の製造方法
JP2014154800A (ja) * 2013-02-13 2014-08-25 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
US10475732B2 (en) 2013-07-12 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. 3DIC package integration for high-frequency RF system
JP6308007B2 (ja) * 2013-07-16 2018-04-11 ソニー株式会社 配線基板および配線基板の製造方法
JP6324876B2 (ja) * 2014-07-16 2018-05-16 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
JP6358887B2 (ja) * 2014-07-31 2018-07-18 新光電気工業株式会社 支持体、配線基板及びその製造方法、半導体パッケージの製造方法
KR101640909B1 (ko) * 2014-09-16 2016-07-20 주식회사 모다이노칩 회로 보호 소자 및 그 제조 방법
WO2019171990A1 (ja) * 2018-03-09 2019-09-12 株式会社有沢製作所 積層体及びその製造方法
US11637166B2 (en) * 2019-04-12 2023-04-25 Boe Technology Group Co., Ltd. Array substrate, manufacturing method thereof, and display apparatus
JP7310599B2 (ja) * 2019-12-26 2023-07-19 トヨタ自動車株式会社 配線基板の製造方法および配線基板
EP4319496A4 (en) * 2021-03-22 2024-09-25 Panasonic Intellectual Property Management Co., Ltd. WIRING BODY, MOUNTING SUBSTRATE, WIRING TRANSFER BOARD WITH WIRING, INTERMEDIATE MATERIAL FOR WIRING BODY, MANUFACTURING METHOD FOR WIRING BODY AND MANUFACTURING METHOD FOR MOUNTING SUBSTRATE
US20240237232A1 (en) * 2023-01-09 2024-07-11 Hannstar Display Corporation Circuit board and manufacturing method thereof, and light emitting module

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010038531A1 (ja) * 2008-09-30 2010-04-08 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
WO2010038532A1 (ja) * 2008-09-30 2010-04-08 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
WO2010050266A1 (ja) * 2008-10-27 2010-05-06 日立化成工業株式会社 銅の表面処理方法及び銅
JP2011049289A (ja) * 2009-08-26 2011-03-10 Kyocera Corp 配線基板及びその製造方法

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Publication number Priority date Publication date Assignee Title
JP3631682B2 (ja) 2001-02-26 2005-03-23 京セラ株式会社 多層配線基板及びその製造方法
US6623844B2 (en) 2001-02-26 2003-09-23 Kyocera Corporation Multi-layer wiring board and method of producing the same
US8450619B2 (en) * 2010-01-07 2013-05-28 International Business Machines Corporation Current spreading in organic substrates

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010038531A1 (ja) * 2008-09-30 2010-04-08 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
WO2010038532A1 (ja) * 2008-09-30 2010-04-08 イビデン株式会社 多層プリント配線板、及び、多層プリント配線板の製造方法
WO2010050266A1 (ja) * 2008-10-27 2010-05-06 日立化成工業株式会社 銅の表面処理方法及び銅
JP2011049289A (ja) * 2009-08-26 2011-03-10 Kyocera Corp 配線基板及びその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015230901A (ja) * 2014-06-03 2015-12-21 三菱瓦斯化学株式会社 樹脂積層体及びプリント配線板
JP2017069399A (ja) * 2015-09-30 2017-04-06 凸版印刷株式会社 インターポーザ、半導体装置及び半導体装置の製造方法
WO2017094470A1 (ja) 2015-11-30 2017-06-08 凸版印刷株式会社 多層プリント配線基板及びその製造方法
US11690178B2 (en) 2015-11-30 2023-06-27 Toppan Printing Co., Ltd. Multilayer printed wiring board and method of manufacturing the same
JP2021097131A (ja) * 2019-12-17 2021-06-24 イビデン株式会社 ドライフィルムレジスト、及び、プリント配線板の製造方法
KR20220111637A (ko) * 2021-02-02 2022-08-09 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 제조 비용 감소 및 성능 증가를 위한 다층 스택을 갖는 상측 전도성 구조물
KR102607661B1 (ko) * 2021-02-02 2023-11-29 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 집적 칩 및 집적 칩을 형성하기 위한 방법
EP4319510A4 (en) * 2021-03-22 2024-10-02 Panasonic Intellectual Property Management Co., Ltd. WIRING BODY, MOUNTING SUBSTRATE, WIRING TRANSFER BOARD WITH WIRING, INTERMEDIATE MATERIAL FOR WIRING BODY, AND METHOD FOR MANUFACTURING WIRING BODY
JPWO2022201563A1 (enExample) * 2021-03-25 2022-09-29
WO2022201563A1 (ja) * 2021-03-25 2022-09-29 ナミックス株式会社 配線基板用積層体

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US20120247814A1 (en) 2012-10-04
US9040832B2 (en) 2015-05-26

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