JP2012164971A - イメージセンサ - Google Patents
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- JP2012164971A JP2012164971A JP2011289705A JP2011289705A JP2012164971A JP 2012164971 A JP2012164971 A JP 2012164971A JP 2011289705 A JP2011289705 A JP 2011289705A JP 2011289705 A JP2011289705 A JP 2011289705A JP 2012164971 A JP2012164971 A JP 2012164971A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/144—Devices controlled by radiation
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Abstract
【解決手段】 イメージセンサ5は、第1面1及び第2面2を有する半導体層100、半導体層100の第1面1上に配置される配線層200、および半導体層100の第2面2上に配置される光透過層300を有する。半導体層100は、光電変換部110を構成するp型不純物層113、及びn型不純物層111を有する。p型不純物層113内に形成されるフローティング拡散領域131、及びフローティング拡散領域131を囲むように形成されるトランスファーゲート電極123は、n型不純物層111上の第1面1側に形成される。これにより、光電変換部110で電位が最も高い地点とトランスファーゲート電極123との間の距離が小さくなるため、フローティング拡散領域131への電荷伝送効率が向上することができる。
【選択図】 図4
Description
本発明が解決しようとする課題はここに制限されなく、言及されないその他の課題は下の記載から当業者に明確に理解できる。
以下、図面を参照して本発明の実施形態によるCMOSイメージセンサ及び製造方法に対して詳細に説明する。
図1は本発明の実施形態によるCMOSイメージセンサ5のブロック図である。
タイミング発生器50は行デコーダ20及び列デコーダ40にタイミング(timing)信号及び制御信号を提供する。
アナログデジタルコンバーターADC70は相関二重サンプラー60から出力された差異レベルに該当するアナログ信号をデジタル信号に変換して出力する。
図2A乃至図2Cは本発明の実施形態によるCMOSイメージセンサ51のアクティブピクセルセンサAPSアレイの回路図である。
一方、図7Cを参照すれば、トランスファーゲート電極123の底面がp型不純物層113とn型不純物層111との境界面に位置できる。
以下、図10及び図11を参照して本発明の実施形態によるイメージセンサ5の動作に対して説明する。
図12を参照すれば、半導体層100を準備し、半導体層100内に活性領域を定義する素子分離膜107を形成する。
このように、光電変換部110を形成した後、光電変換部110を形成するのに利用された第1マスクパターン115を除去する。
続いて、図15を参照すれば、トレンチT内壁に約10〜100Åの厚さを有するゲート絶縁膜121を形成する。
続いて、図15を参照すれば、ゲート絶縁膜121が形成されたトレンチT内に導電物質を満たしてトランスファーゲート電極123を形成する。
フローティング拡散領域131を形成した次には、イオン注入に利用された第3マスクパターン127を除去する。
図18を参照すれば、層間絶縁膜210及び金属配線220を含む配線層200の上に支持基板230を接合する。
図20は本発明の実施形態によるイメージセンサ5が集積されたイメージセンサ5チップを示す断面図である。
図20を参照すれば、イメージセンサ5チップは回路配線が形成された配線基板と配線基板の上に付着されたイメージセンサ5とを含む。
図21は本発明の実施形態によるイメージセンサ5を含むプロセッサー基盤システムを示す概略的なブロック図である。
図21を参照すれば、プロセッサー基盤システム1000はイメージセンサ51100の出力イメージを処理するシステムである。
図22は本発明の実施形態によるイメージセンサ5を含む電子装置を示す斜視図である。
10 ・・・アクティブピクセルセンサアレイ、
20 ・・・行デコーダ、
30 ・・・行ドライバ、
40 ・・・列デコーダ、
50 ・・・タイミング発生器、
60 ・・・相関二重サンプラー、
70 ・・・アナログデジタルコンバーター、
80 ・・・入出力バッファ、
100 ・・・半導体層、
103 ・・・p型エピタキシャル層、
105 ・・・高濃度不純物層、
107 ・・・素子分離膜、
109 ・・・p型分離ウェル、
110 ・・・光電変換部、
111 ・・・n型不純物層、
113 ・・・p型不純物層、
121 ・・・ゲート絶縁膜、
123 ・・・トランスファーゲート電極、
124 ・・・キャッピング絶縁膜、
126 ・・・ローカル不純物領域、
125 ・・・読出しゲート電極、
131 ・・・フローティング拡散領域、
133 ・・・ソース/ドレーン電極、
200 ・・・配線層、
210 ・・・層間絶縁膜、
215 ・・・コンタクトプラグ、
220 ・・・金属配線、
230 ・・・支持基板、
300 ・・・光透過層、
311 ・・・下部平坦膜、
313 ・・・上部平坦膜、
320 ・・・カラーフィルター、
330 ・・・マイクロレンズ。
Claims (12)
- 互に異なる導電型を有する積層された第1不純物領域及び第2不純物領域と、
前記第1不純物領域内に形成されるフローティング拡散領域と、
前記第1不純物領域内で前記フローティング拡散領域を囲むトランスファーゲート電極と、
を備え、
前記トランスファーゲート電極及び前記フローティング拡散領域は、前記第2不純物領域と重なることを特徴とするイメージセンサ。 - 前記トランスファーゲート電極は、閉曲線形状を有することを特徴とする請求項1に記載のイメージセンサ。
- 前記トランスファーゲート電極は、平面上で前記第2不純物領域に対して中心に位置することを特徴とする請求項1に記載のイメージセンサ。
- 前記トランスファーゲート電極の底面が前記第2不純物領域の上部面より下に位置するように前記トランスファーゲート電極が前記第2不純物領域に延長されることを特徴とする請求項1に記載のイメージセンサ。
- 前記第1不純物領域及び前記第2不純物領域は、これらの間の境界を共有し、
前記トランスファーゲート電極は、前記第1不純物領域及び前記第2不純物領域の間の前記境界から離れるように形成されていることを特徴とする請求項1に記載のイメージセンサ。 - 前記第1不純物領域及び前記第2不純物領域は、光電変換素子を提供し、
前記トランスファーゲート電極は、垂直に延長され、平面上で前記光電変換素子に対して中心に位置することを特徴とする請求項1に記載のイメージセンサ。 - 前記トランスファーゲート電極と隣接するローカル不純物領域をさらに含み、
前記ローカル不純物領域は、前記第1不純物領域と同じ導電型を有し、
前記ローカル不純物領域は、前記第1不純物領域の不純物濃度より高い不純物濃度を有することを特徴とする請求項1に記載のイメージセンサ。 - 前記第1不純物領域は、互に異なる不純物濃度を有する第1層及び第2層をさらに備え、
前記フローティング拡散領域は、前記第1層内に位置し、
前記トランスファーゲート電極は、前記第1層内及び前記第2層内に位置することを特徴とする請求項1に記載のイメージセンサ。 - 前記第1不純物領域の一部分は、電荷伝送素子のチャンネル領域に提供されることを特徴とする請求項1に記載のイメージセンサ。
- 前記第1不純物領域は、
表面不純物領域と、
前記表面不純物領域と前記第2不純物領域との間に形成される電位障壁領域と、
を含み、
前記表面不純物領域は、前記電位障壁領域の不純物濃度より大きい不純物濃度を有することを特徴とする請求項1に記載のイメージセンサ。 - 入射光に対応して生成される電荷が格納される電荷格納層と、
前記電荷格納層と異なる導電型を有し、前記電荷格納層の上に配置された電位障壁層と、
前記電位障壁層と異なる導電型を有し、前記電荷格納層の上下方向の離れる側に前記電位障壁層内に局所的に形成された電荷検出層と、
前記電荷検出層の周辺を囲む閉曲線形状を有し、前記電位障壁層の電位を制御して前記電荷格納層の電荷を前記電荷検出層へ伝送するゲート電極と、
を含むイメージセンサ。 - 互に対向する第1表面及び第2表面を含む半導体層と、
前記半導体層の前記第1表面上に形成され、読出しゲート電極及び配線を有する配線層と、
前記半導体層の前記第2表面上に形成され、カラーフィルター及びマイクロレンズを有する光透過層と、
閉曲線形状を形成し、前記半導体層の前記第1表面に直接隣接する前記半導体層内部のゲート電極と、
を備え、
前記半導体層は、
入射光に対応して生成された電荷が格納される電荷格納層と、
前記電荷格納層と反対の導電型を有し、前記電荷格納層と接しながら前記半導体層の前記第1表面に隣接するチャンネル層と、
前記電荷格納層と同一な導電型を有し、前記電荷格納層と上下方向の離れる側の前記チャンネル層内に局所的に形成された電荷検出層と、
をさらに備え、
前記閉曲線形状のゲート電極は、前記チャンネル層の一部分へ挿入されることを特徴とするイメージセンサ。
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WO2021241010A1 (ja) * | 2020-05-25 | 2021-12-02 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子、固体撮像装置及び電子機器 |
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WO2023017650A1 (ja) * | 2021-08-13 | 2023-02-16 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置及び電子機器 |
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US20120199882A1 (en) | 2012-08-09 |
US20140284664A1 (en) | 2014-09-25 |
DE102011055527A1 (de) | 2012-08-09 |
KR20120090352A (ko) | 2012-08-17 |
CN102629614B (zh) | 2016-03-09 |
CN102629614A (zh) | 2012-08-08 |
US8748945B2 (en) | 2014-06-10 |
JP5871616B2 (ja) | 2016-03-01 |
US9356067B2 (en) | 2016-05-31 |
DE102011055527B4 (de) | 2023-10-12 |
KR101845257B1 (ko) | 2018-04-04 |
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