CN109979930B - 基于复合介质栅光敏探测器的2×2阵列布局及工作方法 - Google Patents
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Abstract
本发明公开了一种基于复合介质栅光敏探测器的2×2阵列布局及工作方法。阵列由四个像元组成,每个像元包括一个感光晶体管和一个读取晶体管,这两者形成在同一P型半导体衬底上方,并均采用复合介质栅结构;四个读取晶体管的衬底连成正八边环形结构并位于阵列的中心;正八边环形结构的四条边中,未覆盖复合介质栅的衬底中形成四个两两相对且互呈直角的重掺杂N+区,其中两个相对的重掺杂N+区互连构成共享的N+源极,另外两个互连构成共享的N+漏极;四个感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。本发明可以显著提高光敏探测器的填充系数,实现高的满阱电荷容量,且与浮栅CMOS工艺兼容,易于制造。
Description
技术领域
本发明涉及成像器件阵列版图布局,尤其涉及一种应用于可见光、红外的探测器阵列版图布局及其阵列的工作方法。
背景技术
CCD和CMOS-APS是当前最为常见的两种成像器件。较早出现的CCD,其基本结构是一组组串联而成的MOS电容,通过MOS电容上的脉冲时序控制半导体表面势阱的产生和变化,以此实现光生电荷的存储和转移读出,这种方法造成CCD的成像速度较慢,同时CCD对工艺的要求极高,使其成品率低,成本较大。CMOS-APS通常由一个感光二极管和三至六个晶体管组成,采用更多晶体管意味着具备更加复杂的功能,CMOS-APS采用X-Y寻址方式读取信号,因此其成像速度较CCD快,同时CMOS-APS与CMOS工艺兼容,易于与外围电路整合,但因其像元中包含多个晶体管,其像元的填充系数低,这使得CMOS-APS的满阱电荷量低,为保证高的成像质量,像元尺寸很难进一步缩小。
通过上述比较发现,如果CMOS-APS成像探测器具有高填充系数,则既可以提高探测器的成像质量,又可以缩小像元尺寸。在已有专利CN201210442007中,提出了一种基于复合介质栅MOSFET的双晶体管光敏探测器,该探测器通过两个晶体管将探测器信号的收集功能和读取功能分开,使得探测器的感光部分不需要制作源漏,可以有效地防止感光晶体管之间互相的干扰。
发明内容
针对以上现有技术中存在的技术问题,本发明通过优化光敏探测器阵列的版图布局,提出了一种基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列版图布局方案,旨在提高光敏探测器的填充系数,尤其是针对小尺寸像元。本发明的另外一个目的是提供该2×2源漏共享型阵列的工作方法。
为实现上述发明目的,本发明采用的技术方案如下:
基于复合介质栅光敏探测器的2×2阵列布局,阵列由四个像元组成,每个像元包括一个感光晶体管和一个读取晶体管,感光晶体管和读取晶体管形成在同一P型半导体衬底上方,两者均采用复合介质栅的结构,所述复合介质栅自下而上依次为底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极,其中,四个感光晶体管的电荷耦合层之间互不相连,四个感光晶体管的控制栅极之间互不相连;四个所述读取晶体管的衬底连成正八边环形结构,并位于2×2阵列的中心位置;正八边环形结构的四条边中,未覆盖复合介质栅的衬底中通过N+离子注入形成四个重掺杂N+区,四个重掺杂N+区两两相对且互呈直角,其中,两个相对的重掺杂N+区互连构成共享的N+源极,另外两个相对的重掺杂N+区互连构成共享的N+漏极;四个所述感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。
进一步地,每个像元中,所述感光晶体管和读取晶体管在衬底中通过浅槽隔离区隔开;所述感光晶体管的电荷耦合层和读取晶体管的电荷耦合层相连,所述感光晶体管的控制栅极和读取晶体管的控制栅极相连。
进一步地,四个所述感光晶体管之间在P型半导体衬底中使用浅槽隔离区隔开。
进一步地,所述感光晶体管的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
进一步地,四个所述感光晶体管的控制栅极分别构成字线WL0、字线WL1、字线WL2和字线WL3,四个所述读取晶体管的漏极构成漏线DL,四个所述读取晶体管的源极构成源线SL。
本发明基于复合介质栅光敏探测器的2×2阵列布局的工作方法,包括如下步骤:
(1)光电子的收集:
在光敏探测器的衬底加负偏压,字线WL0、字线WL1、字线WL2和字线WL3同时加相同的零偏压或正偏压,读取晶体管漏线DL和源线SL接地;
(2)光电子的读取:
保持衬底的负偏压,保持字线WL0、字线WL1、字线WL2和字线WL3上所加的偏压,读取晶体管漏线DL加正偏压,读取晶体管源线SL接地,在需要读取的感光晶体管的字线上加一斜波电压,通过读取晶体管导通时的斜波电压值推算光电子信号;读取结束后,读取晶体管漏线DL和源线SL接地,在已读取的感光晶体管的控制栅极上保持曝光时所加的偏压,按照上述方式依次读取四个感光晶体管中的光电子信号;
(3)光电子的复位:
字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压,读取晶体管漏线DL和源线SL接地,光电子通过复合消失。
本发明结合CCD和CMOS-APS探测器的优点,减少了单个探测器中晶体管的数量。相比现有技术中的分立画法,本发明设计的阵列版图布局能有效地提高探测器像元的填充系数,增大满阱电荷容量,从而大大提高探测器的信噪比及成像质量。同时,本发明的阵列结构可以减小光敏探测器的尺寸,实现高像素密度成像阵列,且与浮栅CMOS工艺兼容,易于制造。
附图说明
图1为基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列布局结构图;
图2为图1沿aa’方向的剖面图;
图3为图1沿bb’方向的剖面图;
图4为图1沿cc’方向的剖面图;
图5为图1沿dd’方向的剖面图;
图6为基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列的等效电路图;
图7为单个探测单元的电容模型图。
具体实施方式
本实施例提供一种基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列布局,其版图如图1所示,2×2阵列包括4个探测单元,每个探测单元包括一个感光晶体管1和一个读取晶体管2。感光晶体管1和读取晶体管2形成在同一P型半导体衬底3上,两者的结构均采用复合介质栅,具体为:衬底3上方自下而上依次设有底层绝缘介质层4、电荷耦合层5、顶层绝缘介质层6和控制栅极7。感光晶体管1和读取晶体管2下方的P型半导体衬底3中使用浅槽隔离(STI)8隔开。每个探测单元中,感光晶体管1和读取晶体管2的电荷耦合层相连,感光晶体管1和读取晶体管2的控制栅极相连,通过电荷耦合方式读取光电子信号。对于读取晶体管2,在P型半导体衬底3靠近底层绝缘介质层4的一侧通过离子注入形成N型源极9a,在相对的另一侧通过离子注入形成N型漏极9b。探测器的结构可以参考CN102938409A专利公开的内容。
四个探测单元11a、11b、21a和21b形成正方形的2×2阵列,四个读取晶体管2的有源区16连成正八边环形结构,位于整个2×2阵列的中心位置。在读取晶体管2的正八边环中,处于四条间隔边位置的P型半导体衬底中,未覆盖复合介质栅的区域通过N+离子注入形成四个重掺杂N+区,四个重掺杂N+区两两相对,呈90度直角。将其中两个相对的重掺杂N+区进行互连,构成共享的N+源极,剩余的两个相对的重掺杂N+区进行互连,构成共享的N+漏极。感光晶体管1位于正八边环形结构沿四条斜边的外侧,即处于四个未进行N+重掺杂区域的外侧。四个感光晶体管1之间在P型半导体衬底中使用浅槽隔离区8隔开,且四个感光晶体管1的电荷耦合层5之间互不相连,四个感光晶体管1的控制栅极7之间也互不相连。感光晶体管1的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
如图4所示,四个探测单元11a、11b、21a和21b中的感光晶体管1的电荷耦合层5之间互不相连,四个探测单元11a、11b、21a和21b中的感光晶体管1的控制栅极7之间也互不相连。探测单元11a的读取晶体管2和探测单元11b的读取晶体管2共用同一个源极9a,探测单元21a的读取晶体管2和探测单元21b的读取晶体管2共用同一个源极9a,两个源极之间通过接触孔(CT)12、金属1(M1)13、通孔1(V1)14、金属2(M2)10、通孔2(V2)15和金属3(M3)11进行互连。探测单元11a的读取晶体管2和探测单元21a的读取晶体管2共用同一个漏极9b,探测单元11b的读取晶体管2和探测单元21b的读取晶体管2共用同一个漏极9b,两个漏极之间通过接触孔(CT)12、金属1(M1)13、通孔1(V1)14和金属2(M2)10进行互连,如图5所示。
图6给出了2×2源漏共享型阵列的等效电路图,虚线框表示一个探测单元,四个探测单元的感光晶体管1的控制栅极7分别形成字线WL0、WL1、WL2和WL3,读取晶体管2共用的源极9a形成源线SL,读取晶体管2共用的漏极9b形成漏线DL。
上述2×2源漏共享型阵列的工作方法如下:
(1)光电子收集:
在探测器阵列的衬底加一负偏压,字线WL0、WL1、WL2和WL3加相同的正偏压或零偏压,源线SL和漏线DL接地;
(2)光电子读取:
保持衬底、字线WL0、WL1、WL2和WL3所加的偏压,漏线DL加正偏压,源线SL接地,在需要读取的探测单元感光晶体管1的字线上加一斜波电压,通过读取晶体管2导通时的斜波电压值来推算光电子信号,一个探测单元读取完成后,漏线DL和源线SL接地,在已读取的感光晶体管1的控制栅极7上保持曝光时所加的偏压;按上述方法依次读取剩余探测单元光电子信号;
(3)光电子的复位:
字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压,读取晶体管漏线DL和源线SL接地,光电子通过复合消失。
像元填充系数的定义为一个像元中有效感光晶体管面积占一个像元面积的比值,按照相同的设计规则,如果单个像元面积为2um×2um,按本发明所述的源漏共享型阵列版图布局设计的像元,其填充系数可以达到70%,而现有分立画法的填充系数则低于60%。同时,随着像元尺寸的进一步缩小,本发明相比分立画法,其填充系数高的优势将会进一步提高。
本发明的2×2探测器阵列能增大像元的填充系数,提高探测单元的灵敏度,其原因在于:读取晶体管2阈值电压变化与感光晶体管1收集的光电子数存在的关系如下:
Claims (6)
1.基于复合介质栅光敏探测器的2×2阵列布局,其特征在于,阵列由四个像元组成,每个像元包括一个感光晶体管和一个读取晶体管,感光晶体管和读取晶体管形成在同一P型半导体衬底上方,两者均采用复合介质栅的结构,所述复合介质栅自下而上依次为底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极,其中,四个感光晶体管的电荷耦合层之间互不相连,四个感光晶体管的控制栅极之间互不相连;
四个所述读取晶体管的有源区连成正八边环形结构,并位于2×2阵列的中心位置;正八边环形结构的四条边中,未覆盖复合介质栅的衬底中通过N+离子注入形成四个重掺杂N+区,四个重掺杂N+区两两相对且互呈直角,其中,两个相对的重掺杂N+区互连构成共享的N+源极,另外两个相对的重掺杂N+区互连构成共享的N+漏极;
四个所述感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。
2.根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局,其特征在于,每个像元中,所述感光晶体管和读取晶体管在衬底中通过浅槽隔离区隔开;所述感光晶体管的电荷耦合层和读取晶体管的电荷耦合层相连,所述感光晶体管的控制栅极和读取晶体管的控制栅极相连。
3.根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局,其特征在于,四个所述感光晶体管之间在P型半导体衬底中使用浅槽隔离区隔开。
4.根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局,其特征在于,所述感光晶体管的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
5.根据权利要求1-4之一所述的基于复合介质栅光敏探测器的2×2阵列布局,其特征在于,四个所述感光晶体管的控制栅极分别构成字线WL0、字线WL1、字线WL2和字线WL3,四个所述读取晶体管的漏极构成漏线DL,四个所述读取晶体管的源极构成源线SL。
6.如权利要求5所述的基于复合介质栅光敏探测器的2×2阵列布局的工作方法,其特征在于,包括如下步骤:
(1)光电子的收集:
在光敏探测器的衬底加负偏压,字线WL0、字线WL1、字线WL2和字线WL3同时加相同的零偏压或正偏压,读取晶体管漏线DL和源线SL接地;
(2)光电子的读取:
保持衬底的负偏压,保持字线WL0、字线WL1、字线WL2和字线WL3上所加的偏压,读取晶体管漏线DL加正偏压,读取晶体管源线SL接地,在需要读取的感光晶体管的字线上加一斜波电压,通过读取晶体管导通时的斜波电压值推算光电子信号;读取结束后,读取晶体管漏线DL和源线SL接地,在已读取的感光晶体管的控制栅极上保持曝光时所加的偏压,按照上述方式依次读取四个感光晶体管中的光电子信号;
(3)光电子的复位:
字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压,读取晶体管漏线DL和源线SL接地,光电子通过复合消失。
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