CN110581190B - 一种适应亚微米像素的utbb光电探测器、阵列和方法 - Google Patents
一种适应亚微米像素的utbb光电探测器、阵列和方法 Download PDFInfo
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Abstract
本申请公开了一种适应亚微米像素的UTBB光电探测器、阵列和方法,包括:硅膜层、埋氧层、掺杂层和衬底,所述衬底、掺杂层、埋氧层和硅膜层依次从下至上设置;所述硅膜层包括相邻的一个NMOS管和一个PMOS管;所述掺杂层包括多个交替排列的N型掺杂区和P型掺杂区。所述NMOS管为一个像素单元,所述PMOS管为一个像素单元。通过在掺杂层采用横向电场,主动使信号电荷向像素内聚集,抑制串扰的能力更强,而且无需浅槽隔离,可以使像素单元进一步缩小。采用横向PN结感光结构,PN结的横向自建电场与埋氧层下垂直方向电场共同作用,使得光生电子可以漂移并聚集在埋氧层下方。横向电场的存在提高了光电转化效率,抑制了像素间串扰,使其更适合于亚微米像素。
Description
技术领域
本申请涉及硅基光电探测器领域,尤其涉及一种适应亚微米像素的UTBB光电探测器、阵列和方法。
背景技术
光电成像探测器广泛用于军事、医疗、汽车、移动设备等。现如今,在先进工业、汽车、医疗等领域对高分辨率大视场成像的需求越来越高,需要更小尺寸的像素单元。
目前主流光电成像探测器为CCD光电器件及CMOS-APS光电器件,CCD光电器件直接通过电荷转移进行光电探测,而CMOS-APS光电器件通过像素单元光电二极管收集电荷后转变为电压信号通过CMOS电路放大并读取。两种光电探测器件具有各自的优势和不足。
然而,由于器件本身结构限制,两种光电探测器单个像素单元均包含多个晶体管等器件结构,使得像素尺寸局限在微米量级以上无法进一步缩小。
使用单个晶体管,如超薄体及埋氧(Ultra-Thin Box and Body,UTBB)结构,实现光电探测单元可以有效降低像素单元尺寸,然而目前有采用UTBB结构作为图像传感器的方案需要采用浅槽隔离来抑制像素间的串扰,限制了像素单元的进一步缩小。
综上所述,需要提供一种尺寸小且能够抑制串扰的光电探测器、阵列和方法。
发明内容
为解决以上问题,本申请提出了一种适应亚微米像素的UTBB光电探测器、阵列和方法。
一方面,本申请提出了一种适应亚微米像素的UTBB光电探测器,包括:硅膜层、埋氧层、掺杂层和衬底,所述衬底、掺杂层、埋氧层和硅膜层依次从下至上设置;
所述硅膜层包括相邻的一个NMOS管和一个PMOS管;
所述掺杂层包括多个交替排列的N型掺杂区和P型掺杂区。
优选地,所述NMOS管为一个像素单元,所述PMOS管为一个像素单元;
所述NMOS管的源端和漏端被隔在NMOS管的沟道两端,NMOS管的栅端在NMOS管的沟道上;
所述PMOS管的源端和漏端被隔在PMOS管的沟道两端,PMOS管的栅端在PMOS管的沟道上。
优选地,所述NMOS管和所述PMOS管的沟道长度为20至100纳米,源端长度为20至90纳米,漏端长度为20至90纳米。
优选地,所述硅膜层的硅膜厚度为5至20纳米。
优选地,所述埋氧层厚度为10至30纳米。
优选地,所述掺杂层的深度为50至1000纳米,所述P型掺杂区和所述N型掺杂区的掺杂浓度为1×1016至1×1018立方厘米。
第二方面,本申请提出了一种适应亚微米像素的UTBB光电探测器阵列,包括:包括:由M×N个上述权利要求1-7任意一项所述的光电探测器组成的光电探测器阵列,其中M和N为大于等于2的自然数。
优选地,所述光电探测器阵列包括多列字线、多行位线、公共N型掺杂区电极和公共源极,其中,所有NMOS管的源极和PMOS管的源极与公共源极相连,掺杂层的所有N型掺杂区与所述公共N型掺杂区电极相连,每列光电探测器的栅极和与其对应的字线相连,每行光电探测器的漏极和与其对应的位线相连。
第三方面,本申请提出了一种适应亚微米像素的UTBB光电探测器的探测方法,包括:
对NMOS管栅端和漏端施加正电压,对PMOS管栅端和漏端施加负电压;
埋氧层与掺杂层之间聚集的正电荷量根据光照强度改变,从而改变NMOS管或PMOS管的阈值电压和漏端电流;
通过测量埋氧层上方硅膜层的漏端电流评估光照强度。
本申请的优点在于:通过在掺杂层采用横向电场,主动使信号电荷向像素内聚集,抑制串扰的能力更强,而且无需浅槽隔离,可以使像素单元进一步缩小。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选事实方案的目的,而并不认为是对本申请的限制。而且在整个附图中,用同样的参考符号表示相同的部件。在附图中:
图1是本申请提供的一种适应亚微米像素的UTBB光电探测器的结构图;
图2是本申请提供的一种适应亚微米像素的UTBB光电探测器阵列的结构图;
图3是本申请提供的一种适应亚微米像素的UTBB光电探测器的探测方法的步骤示意图;
图4是本申请提供的一种适应亚微米像素的UTBB光电探测器的探测方法的光照前后PN结与埋氧层界面处电势分布图;
图5是本申请提供的一种适应亚微米像素的UTBB光电探测器的探测方法的光照前后MOS管转移特性曲线图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
根据本申请的实施方式,提出一种适应亚微米像素的UTBB光电探测器,如图1所示,包括:硅膜层、埋氧层、掺杂层和衬底,所述衬底、掺杂层、埋氧层和硅膜层依次从下至上设置;
硅膜层包括相邻的一个NMOS管和一个PMOS管;
掺杂层包括多个交替排列的N型掺杂区和P型掺杂区。
NMOS管为一个像素单元,PMOS管为一个像素单元;
NMOS管的源端和漏端被隔在NMOS管的沟道两端,NMOS管的栅端在NMOS管的沟道上;
PMOS管的源端和漏端被隔在PMOS管的沟道两端,PMOS管的栅端在PMOS管的沟道上。
NMOS管和PMOS管的沟道长度为20至100纳米,源端长度为20至90纳米,漏端长度为20至90纳米。
硅膜层的硅膜厚度为5至20纳米。
硅膜厚度为沟道的厚度,沟道上方的是栅端,硅膜厚度不包括栅端的厚度。源端和漏端突出的部分是为了减小源端和漏端的电阻所做的源漏抬升,为UTBB工艺中常见的结构,所以硅膜厚度也不包括源端和漏端突出的部分。
埋氧层厚度为10至30纳米。
掺杂层的深度为50至1000纳米,P型掺杂区和N型掺杂区的掺杂浓度为1×1016至1×1018立方厘米。
掺杂层的P型掺杂区和N型掺杂区的掺杂浓度和面积可以分别调整。
P型掺杂区和N型掺杂区的位置可以互相交换。
掺杂层的P型掺杂区和N型掺杂区的位置与硅膜层的NMOS管和PMOS管在横向方向上的相对位置可以调整。
第二方面,本申请提出了一种适应亚微米像素的UTBB光电探测器阵列,如图2所示,包括:由M×N个光电探测器组成的光电探测器阵列,其中M和N为大于等于2的自然数。
光电探测器阵列包括多列字线、多行位线、公共N型掺杂区电极和公共源极,其中,所有NMOS管的源极和PMOS管的源极与公共源极相连,掺杂层的所有N型掺杂区与所述公共N型掺杂区电极相连,每列光电探测器的栅极和与其对应的字线相连,每行光电探测器的漏极和与其对应的位线相连。
如图2所示,所有NMOS管源极(端)和PMOS管源极接公共源极Vs,并置0电位,衬底中所有N型掺杂区接公共N型掺杂区电极Vn,每列器件栅极共接字线,每行器件漏极共接位线。器件复位时,所有字线置0电位,所有位线置0电位,N型掺杂区置负电位。信号收集时,所有字线和位线保持0电位,N型掺杂区置正电位。信号读取时,将所有位线的电压先置为+Vdd,依次选中连接NMOS管的字线,即奇数列字线,选中的字线电位置为+Vdd,通过位线读取每个NMOS管的信号电流。之后所有位线的电压置为-Vdd,依次选中连接PMOS管的字线,即偶数列字线,选中的字线电位置为-Vdd,通过位线读取每个PMOS管的信号电流。
第三方面,本申请提出了一种适应亚微米像素的UTBB光电探测器的探测方法,如图3所示,包括:
S101,对NMOS管栅端和漏端施加正电压,对PMOS管栅端和漏端施加负电压;
S102,埋氧层与掺杂层之间聚集的正电荷量根据光照强度改变,从而改变NMOS管或PMOS管的阈值电压和漏端电流;
S103,通过测量埋氧层上方硅膜层的漏端电流评估光照强度。
本申请实施例的光电探测方法主要分为复位、收集和读出三个过程。相应的电极偏置条件如表1所示。
表1
复位 | 收集 | 读取 | |
NMOS管栅极电压 | 0 | 0 | +Vdd |
NMOS管漏极电压 | 0 | 0 | +Vdd |
NMOS管源极电压 | 0 | 0 | 0 |
PMOS管栅极电压 | 0 | 0 | -Vdd |
PMOS管漏极电压 | 0 | 0 | -Vdd |
PMOS管源极电压 | 0 | 0 | 0 |
N型掺杂区电压 | Vreset | +Vdd | +Vdd |
在复位阶段,MOS管的源、漏和栅极电压为零,使MOS管处于关断状态。在PN结的N端(N型掺杂区)施加一个复位脉冲信号Vreset(复位信号),将PN结正偏,正偏电流向浮置的P型掺杂区注入电荷并将P端(P型掺杂区)电压复位至初始电压。
PN结是由一个N型掺杂区和一个P型掺杂区紧密接触所构成的。
在收集阶段,将PN结的N端电压置为+Vdd(正电源电压),将PN结反偏,对器件(电探测器)进行曝光。入射光在器件下方的PN结中产生光生载流子,光生载流子在PN结自建电场的作用下分离。由于埋氧层上下存在电压差,埋氧层附近存在垂直方向的电场。进入P端的光生空穴在垂直方向电场的作用下在埋氧层下聚集。
在读取阶段,通过埋氧层上方MOSFET漏端电流来读出光信号。NMOS管的栅极和漏极均置正电压,PMOS管的栅极和漏极均置负电压。如图4所示,为光照前后PN结与埋氧层界面处电势分布。埋氧层下方聚集的空穴将埋氧层与衬底界面处的电势抬升,并通过埋氧层作用于上方MOS管器件沟道,使埋氧层形成类似于电容器的结构,使NMOS管沟道中的反型载流子增多,阈值电压减小。相应的,PMOS管件沟道中的反型载流子减少,阈值电压增大。
如图5所示,为光照前后MOS管转移特性曲线。其中,Vds为源端和漏端的电压。由于在不同的光照强度下,埋氧层下方衬底聚集的正电荷量不同,从而MOS管阈值电压不同,漏端电流不同。通过测量埋氧层上方MOS管漏端电流可以评估光照强度。
本申请的实施方式中,通过在掺杂层采用横向电场,主动使信号电荷向像素内聚集,抑制串扰的能力更强,而且无需浅槽隔离,可以使像素单元进一步缩小。与CMOS-APS光电器件阵列结构相比,本申请实施方式的阵列中,每个像素点仅需单个器件能完成感光功能,能有效减小像素单元尺寸。采用横向PN结感光结构,PN结的横向自建电场与埋氧层下垂直方向电场共同作用,使得光生电子可以漂移并聚集在埋氧层下方。横向电场的存在提高了光电转化效率,抑制了像素间串扰,使其更适合于亚微米像素。通过采用横向PN结感光并抑制串扰,节省了浅槽隔离的面积,使其更适合于亚微米像素。
以上所述,仅为本申请较佳的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
Claims (8)
1.一种适应亚微米像素的UTBB光电探测器,其特征在于,包括:硅膜层、埋氧层、掺杂层和衬底,所述衬底、掺杂层、埋氧层和硅膜层依次从下至上设置;
所述硅膜层包括相邻的一个NMOS管和一个PMOS管;
所述掺杂层包括多个交替排列的N型掺杂区和P型掺杂区;
所述埋氧层为一个整体;
所述NMOS管为一个像素单元,所述PMOS管为一个像素单元;
所述NMOS管的源端和漏端被隔在NMOS管的沟道两端,NMOS管的栅端在NMOS管的沟道上;
所述PMOS管的源端和漏端被隔在PMOS管的沟道两端,PMOS管的栅端在PMOS管的沟道上;
所述NMOS管的沟道与其中一个所述P型掺杂区相对应,与所述埋氧层共同形成一个电容器结构;
所述PMOS管的沟道与其中另一个所述P型掺杂区相对应,与所述埋氧层共同形成一个电容器结构。
2.如权利要求1所述的光电探测器,其特征在于,所述NMOS管和所述PMOS管的沟道长度为20至100纳米,源端长度为20至90纳米,漏端长度为20至90纳米。
3.如权利要求1所述的光电探测器,其特征在于,所述硅膜层的硅膜厚度为5至20纳米。
4.如权利要求1所述的光电探测器,其特征在于,所述埋氧层厚度为10至30纳米。
5.如权利要求1所述的光电探测器,其特征在于,所述掺杂层的深度为50至1000纳米,所述P型掺杂区和所述N型掺杂区的掺杂浓度为1×1016至1×1018/立方厘米。
6.一种适应亚微米像素的UTBB光电探测器阵列,其特征在于,包括:由M×N个上述权利要求1-5任意一项所述的光电探测器组成的光电探测器阵列,其中M和N为大于等于2的自然数。
7.如权利要求6所述的UTBB光电探测器阵列,其特征在于,所述光电探测器阵列包括多列字线、多行位线、公共N型掺杂区电极和公共源极,其中,所有NMOS管的源极和PMOS管的源极与公共源极相连,掺杂层的所有N型掺杂区与所述公共N型掺杂区电极相连,每列光电探测器的栅极和与其对应的字线相连,每行光电探测器的漏极和与其对应的位线相连。
8.一种适应亚微米像素的UTBB光电探测器的探测方法,其特征在于,通过权利要求1-5任一项所述的UTBB光电探测器实现,所述探测方法包括:
对NMOS管栅端和漏端施加正电压,对PMOS管栅端和漏端施加负电压;
埋氧层与掺杂层之间聚集的正电荷量根据光照强度改变,从而改变NMOS管或PMOS管的阈值电压和漏端电流;
通过测量埋氧层上方硅膜层的漏端电流评估光照强度。
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