CN114841847A - 基于复合介质栅结构的感存算一体器件、阵列及其方法 - Google Patents
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Abstract
本发明公开了一种基于复合介质栅结构的感存算一体器件,包括形成在同一P型半导体衬底上方的复合介质栅光敏探测器和复合介质栅晶体管。其中,复合介质栅光敏探测器在衬底上方依次设有第一底层绝缘介质层、第一浮栅、第一顶层绝缘介质层和第一控制栅;复合介质栅晶体管用于完成其存储的权重和感光的光电子的调和平均数的运算,其在衬底上方依次设有第二底层绝缘介质层、第二浮栅、第二顶层绝缘介质层和第二控制栅;复合介质栅光敏探测器和复合介质栅晶体管分别在衬底内设有源极和漏极。本发明的器件能在信号读取的过程中完成调和平均数的运算,可以用来匹配后续图像处理单元的复杂运算,降低后续图像处理的算力需求和功耗。
Description
技术领域
本发明涉及感存算一体器件,是一种基于复合介质栅结构的集感光、存储和运算于一体的新器件。
背景技术
CCD和CMOS-APS作为当前最常见的两种成像器件,都具有各自的局限。CCD因其复杂的控制时序和电压要求,导致工作速度较慢,且不易集成;CMOS-APS因其采用感光二极管,且结构复杂,导致填充系数低,满阱电荷小。
在中国专利CN201210442007中提出了一种双晶体管光敏探测器,该探测器的特点是单个半导体器件即可实现完整的复位、感光以及读出的功能,构成一个完整的像素,可以极大地提高像素的填充因子。这种复合介质栅双晶体管光敏探测器作为新一代的成像器件,其更快的工作速度、更大的填充系数、更多的满阱电荷且能和CMOS工艺集成,使其与CCD和CMOS-APS相比具有先天优势。
为了满足智能化的需求,目前人工智能系统大多将图像数据读取后再通过CPU或GPU进行智能运算。但传统冯诺依曼架构存在着存储墙的瓶颈,难以达到较高的能效比,虽然出现了存算一体技术,但其仍然需要将所有图像数据都外传到处理端进行智能运算,存在着传输墙的瓶颈。
发明内容
针对目前尚无基于感存算一体化的系统设计,本发明旨在打破传感、存储和运算的壁垒,突破传输墙和存储墙,将三者有机融合,提供一种基于复合介质栅结构的感存算一体化器件和阵列。本发明的另一个目的在于提供上述器件和阵列的操作方法。
本发明器件采用的技术方案如下:
基于复合介质栅结构的感存算一体器件,包括形成在同一P型半导体衬底上方的复合介质栅光敏探测器和复合介质栅晶体管,其中,所述复合介质栅光敏探测器用于收集、存储和读出感光的光电子,其在衬底上方依次设有第一底层绝缘介质层、第一浮栅、第一顶层绝缘介质层和第一控制栅;所述复合介质栅晶体管用于完成其存储的权重和所述感光的光电子的调和平均数的运算,其在衬底上方依次设有第二底层绝缘介质层、第二浮栅、第二顶层绝缘介质层和第二控制栅;所述复合介质栅光敏探测器和所述复合介质栅晶体管分别在衬底内设有源极和漏极。
进一步地,所述复合介质栅光敏探测器的源极与所述复合介质栅晶体管的源极共用。
本发明提供上述基于复合介质栅结构的感存算一体器件的操作方法,包括如下步骤:
(1)权重的复位:调节所述第二控制栅与P型半导体衬底处于反偏状态,使得所述复合介质栅晶体管产生FN隧穿,完成权重的复位;
(2)权重的写入:①调节所述第二控制栅与P型半导体衬底处于正偏状态,使得所述复合介质栅晶体管产生FN隧穿,完成权重的写入;或②调节所述第二控制栅与P型半导体衬底处于正偏状态,在所述复合介质栅光敏探测器漏极接地,所述复合介质栅晶体管漏极接正偏信号,使得所述复合介质栅晶体管产生热电子注入,完成权重的写入;
(3)光电子的复位:调节所述第一控制栅与P型半导体衬底处于零偏状态,使得所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区消失,完成光电子的复位;
(4)光电子的产生:光电子入射到P型半导体衬底,产生光生电子空穴对;
(5)光电子的收集:调节所述第一控制栅与P型半导体衬底处于正偏压状态,使得所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区产生,步骤(4)中产生的光生电子空穴对在垂直电场的作用下分离,电子被扫入所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区,空穴被扫出衬底;
(6)信号的读出:在步骤(5)的正偏压基础上,所述复合介质栅光敏探测器漏极接地,所述第二控制栅上接正偏信号,所述复合介质栅晶体管的漏极接正偏信号,读取所述复合介质栅晶体管的输出电流。
本发明还提供一种基于复合介质栅结构的感存算一体器件阵列,将上述感存算一体器件采用NOR架构形成阵列:对于N行M列的所述感存算一体器件阵列,共有N个第一字线WL1信号,分别连接N个所述感存算一体器件的第一控制栅;共有N个第二字线WL2信号,分别连接N个所述感存算一体器件的第二控制栅;共有M个源线SL信号,分别连接M个所述复合介质栅光敏探测器的漏极;共有M个位线BL信号,分别连接M个所述复合介质栅晶体管的漏极。
本发明另外提供一种基于复合介质栅结构的感存算一体器件阵列的操作方法,包括如下步骤:
(1)权重的复位:调节WL2与P型半导体衬底处于反偏状态,使得每个器件中所述复合介质栅晶体管产生FN隧穿,完成权重的复位;
(2)权重的写入:①调节WL2与P型半导体衬底处于正偏状态,使得每个器件中所述复合介质栅晶体管产生FN隧穿,完成权重的写入;或②调节WL2与P型半导体衬底处于正偏状态,SL接地,BL接正偏信号,使得每个器件中所述复合介质栅晶体管产生热电子注入,完成权重的写入;
(3)光电子的复位:调节WL1与P型半导体衬底处于零偏状态,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区消失,完成光电子的复位;
(4)光电子的产生:光电子入射到P型半导体衬底,产生光生电子空穴对;
(5)光电子的收集:调节WL1与P型半导体衬底处于正偏压状态,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区产生,步骤(4)中产生的光生电子空穴对在垂直电场的作用下分离,电子被分别扫入每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区,空穴被扫出衬底;
(6)信号的读出:在步骤(5)的正偏压基础上,SL接地,WL2接正偏信号,BL接正偏信号,分别读取器件阵列的输出电流。
本发明的器件能在信号读取的过程中完成调和平均数的运算,可以用来匹配后续图像处理单元的复杂运算,降低后续图像处理的算力需求和功耗。
附图说明
图1是本发明的器件结构图;
图2是本发明器件结构图的AA’截面图;
图3是本发明器件的等效电路图;
图4是本发明器件的(a)符号图,(b)是(a)图的符号简化图;
图5是本发明的阵列结构图。
具体实施方式
本发明提供了一种基于复合介质栅结构的感存算一体器件,其结构如图1所示,包括形成在同一P型半导体衬底上方的复合介质栅光敏探测器和复合介质栅晶体管。其中,所述复合介质栅光敏探测器在衬底上方依次设有第一底层绝缘介质层、第一浮栅、第一顶层绝缘介质层、第一控制栅,并在衬底内两侧设有源极和漏极;所述复合介质栅晶体管在衬底上方依次设有第二底层绝缘介质层、第二浮栅、第二顶层绝缘介质层、第二控制栅,并在衬底内两侧设有源极和漏极。其中,本实施例的复合介质栅光敏探测器的源极与复合介质栅晶体管的源极共用;复合介质栅光敏探测器设有2个MOS电容,和一个沟道,如图2所示(图1中AA’方向横截面)。
基于复合介质栅结构的感存算一体器件等效电路如图3所示,复合介质栅光敏探测器M1和复合介质栅晶体管M2均工作在线性区,其电流分别为ID1和ID2。复合介质栅光敏探测器M1原始阈值电压为VTH1,0,所存储的光电信号为Vp,则其最终阈值电压为VTH1=VTH1,0+Vp;复合介质栅晶体管M2原始阈值电压为VTH2,0,所存储的权重信号为Vw,则其最终阈值电压为VTH2=VTH2,0+Vw。施加在第一控制栅上的信号为VWL1,施加在第二控制栅上的信号为VWL2,施加在复合介质栅晶体管漏端的信号为Vref,源端的信号为VS,由此可得:
其中,K1和K2分别为M1和M2的跨导系数,忽略非理想效应后可得:
即:
其中,Opt代表感光信号,Elec代表复合介质栅晶体管的存储信号。因此,该器件可以实现光信号(复合介质栅光敏探测器收集的光生电子)和电信号(复合介质栅晶体管存储的权重)的调和平均值的运算。
基于复合介质栅结构的感存算一体器件的符号如图4的(a)图所示,包括第一控制栅、第二控制栅、源极、漏极和衬底;考虑到通常采用P型衬底,因此可以将符号简化为图4的(b)图的形式。
基于此,图5给出了N行M列的感存算一体阵列架构,共有N个第一字线WL1信号,分别连接N个第一控制栅;共有N个第二字线WL2信号,分别连接N个第二控制栅;共有M个源线SL信号,分别连接M个复合介质栅光敏探测器的漏极;共有M个位线BL信号,分别连接M个复合介质栅晶体管的漏极。
本实施例给出一种基于该阵列的调和平均数计算方法。假设图5中的阵列尺寸为16×16,即N=16、M=16,记阵列中每个基于复合介质栅结构的感存算一体器件为Mi,j,其中i为行、j为列,从左下角开始编号,即左下角所述基于复合介质栅结构的感存算一体器件为M1,1,右上角基于复合介质栅结构的感存算一体器件编号为M16,16。假设每个基于复合介质栅结构的感存算一体器件中所述复合介质栅光敏探测器原始阈值电压为VTH1,0,光电子导致的阈值电压偏移为Vopt,即:
假设信号需要进行不同权重wi,j的调和平均数计算,计算结果xi,j为:
(1)权重的复位:调节第二字线WL2接-10V,P型半导体衬底接-3V,使得每个器件中所述复合介质栅晶体管产生FN隧穿,完成权重的复位,记此时每个所述基于复合介质栅结构的感存算一体器件中所述复合介质栅晶体管原始阈值电压VTH2至负值;
(2)权重的写入:调节第二字线WL2接5V,P型半导体衬底接-3V,源线SL接0V,位线BL接3V,使得每个器件中所述复合介质栅晶体管产生热电子注入,完成权重的写入,每个器件Mi,j中所述复合介质栅晶体管原始阈值电压分别写入成wi,j;
(3)光电子的复位:调节第一字线WL1接-3V,P型半导体衬底接-3V,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区消失,完成光电子的复位;
(4)光电子的产生:光电子入射到P型半导体衬底,产生光生电子空穴对;
(5)光电子的收集:调节第一字线WL1接0V,P型半导体衬底接-3V,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区产生,步骤(4)中产生的光生电子空穴对在垂直电场的作用下分离,电子被分别扫入每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区,空穴被扫出衬底;
(6)信号的读出:在步骤(5)的偏压基础上,源线SL接0V,第二字线WL2接5V,位线BL接0.2V,分别读取阵列器件的输出电流(假设K1=K2=K):
据此,阵列在读出时就完成了调和平均数的计算,省去了NM次加法、乘法和除法运算。
Claims (5)
1.基于复合介质栅结构的感存算一体器件,其特征在于,包括形成在同一P型半导体衬底上方的复合介质栅光敏探测器和复合介质栅晶体管,其中,所述复合介质栅光敏探测器用于收集、存储和读出感光的光电子,其在衬底上方依次设有第一底层绝缘介质层、第一浮栅、第一顶层绝缘介质层和第一控制栅;所述复合介质栅晶体管用于完成其存储的权重和所述感光的光电子的调和平均数的运算,其在衬底上方依次设有第二底层绝缘介质层、第二浮栅、第二顶层绝缘介质层和第二控制栅;所述复合介质栅光敏探测器和所述复合介质栅晶体管分别在衬底内设有源极和漏极。
2.根据权利要求1所述的基于复合介质栅结构的感存算一体器件,其特征在于,所述复合介质栅光敏探测器的源极与所述复合介质栅晶体管的源极共用。
3.如权利要求1或2所述基于复合介质栅结构的感存算一体器件的操作方法,其特征在于,包括如下步骤:
(1)权重的复位:调节所述第二控制栅与P型半导体衬底处于反偏状态,使得所述复合介质栅晶体管产生FN隧穿,完成权重的复位;
(2)权重的写入:①调节所述第二控制栅与P型半导体衬底处于正偏状态,使得所述复合介质栅晶体管产生FN隧穿,完成权重的写入;或②调节所述第二控制栅与P型半导体衬底处于正偏状态,在所述复合介质栅光敏探测器漏极接地,所述复合介质栅晶体管漏极接正偏信号,使得所述复合介质栅晶体管产生热电子注入,完成权重的写入;
(3)光电子的复位:调节所述第一控制栅与P型半导体衬底处于零偏状态,使得所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区消失,完成光电子的复位;
(4)光电子的产生:光电子入射到P型半导体衬底,产生光生电子空穴对;
(5)光电子的收集:调节所述第一控制栅与P型半导体衬底处于正偏压状态,使得所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区产生,步骤(4)中产生的光生电子空穴对在垂直电场的作用下分离,电子被扫入所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区,空穴被扫出衬底;
(6)信号的读出:在步骤(5)的正偏压基础上,所述复合介质栅光敏探测器漏极接地,所述第二控制栅上接正偏信号,所述复合介质栅晶体管的漏极接正偏信号,读取所述复合介质栅晶体管的输出电流。
4.基于复合介质栅结构的感存算一体器件阵列,其特征在于,将如权利要求1所述的感存算一体器件采用NOR架构形成阵列:
对于N行M列的所述感存算一体器件阵列,共有N个第一字线WL1信号,分别连接N个所述感存算一体器件的第一控制栅;共有N个第二字线WL2信号,分别连接N个所述感存算一体器件的第二控制栅;共有M个源线SL信号,分别连接M个所述复合介质栅光敏探测器的漏极;共有M个位线BL信号,分别连接M个所述复合介质栅晶体管的漏极。
5.如权利要求4所述基于复合介质栅结构的感存算一体器件阵列的操作方法,其特征在于,包括如下步骤:
(1)权重的复位:调节WL2与P型半导体衬底处于反偏状态,使得每个器件中所述复合介质栅晶体管产生FN隧穿,完成权重的复位;
(2)权重的写入:①调节WL2与P型半导体衬底处于正偏状态,使得每个器件中所述复合介质栅晶体管产生FN隧穿,完成权重的写入;或②调节WL2与P型半导体衬底处于正偏状态,SL接地,BL接正偏信号,使得每个器件中所述复合介质栅晶体管产生热电子注入,完成权重的写入;
(3)光电子的复位:调节WL1与P型半导体衬底处于零偏状态,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区消失,完成光电子的复位;
(4)光电子的产生:光电子入射到P型半导体衬底,产生光生电子空穴对;
(5)光电子的收集:调节WL1与P型半导体衬底处于正偏压状态,使得每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区产生,步骤(4)中产生的光生电子空穴对在垂直电场的作用下分离,电子被分别扫入每个器件中所述第一底层绝缘介质层下方P型半导体衬底内的耗尽区,空穴被扫出衬底;
(6)信号的读出:在步骤(5)的正偏压基础上,SL接地,WL2接正偏信号,BL接正偏信号,分别读取器件阵列的输出电流。
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