WO2019127942A1 - 基于复合介质栅光敏探测器的2×2阵列布局及工作方法 - Google Patents

基于复合介质栅光敏探测器的2×2阵列布局及工作方法 Download PDF

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WO2019127942A1
WO2019127942A1 PCT/CN2018/080131 CN2018080131W WO2019127942A1 WO 2019127942 A1 WO2019127942 A1 WO 2019127942A1 CN 2018080131 W CN2018080131 W CN 2018080131W WO 2019127942 A1 WO2019127942 A1 WO 2019127942A1
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word line
read
composite dielectric
line
read transistor
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PCT/CN2018/080131
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French (fr)
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马浩文
黄枝建
施毅
闫锋
张丽敏
卜晓峰
李煜乾
李张南
孔祥顺
毛成
杨程
曹旭
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南京大学
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Priority to US16/753,242 priority Critical patent/US11102438B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures

Definitions

  • the present invention relates to an array layout of an imaging device, and more particularly to a method for working with a detector array layout and an array thereof for visible light and infrared.
  • CCD and CMOS-APS are the two most common imaging devices available today.
  • the CCD that appeared earlier is a set of MOS capacitors connected in series.
  • the generation and change of the semiconductor surface potential well is controlled by the pulse timing on the MOS capacitor, thereby realizing the storage and transfer readout of the photogenerated charge.
  • the method causes the imaging speed of the CCD to be slow, and the CCD has extremely high requirements on the process, so that the yield is low and the cost is large.
  • CMOS-APS usually consists of a photodiode and three to six transistors. More transistors mean more complex functions.
  • CMOS-APS uses XY addressing to read signals, so its imaging speed is faster than CCD, and CMOS - APS is compatible with CMOS technology and is easy to integrate with peripheral circuits. However, because its pixels contain multiple transistors, its cell fill factor is low, which makes the CMOS-APS have a low full-charge charge, ensuring high image quality. The pixel size is hard to shrink further.
  • CMOS-APS imaging detector has a high fill factor, both the imaging quality of the detector and the pixel size can be reduced.
  • a two-transistor photosensitive detector based on a composite dielectric gate MOSFET is proposed. The detector separates the collection function and the reading function of the detector signal by two transistors, so that the photosensitive portion of the detector is not It is necessary to make source and drain, which can effectively prevent mutual interference between the phototransistors.
  • the present invention proposes a 2 ⁇ 2 source-drain shared array layout scheme based on a composite dielectric gate MOSFET photosensitive detector by optimizing the layout of the photosensitive detector array. Increase the fill factor of the photodetector, especially for small-sized pixels.
  • Another object of the present invention is to provide a method of operation of the 2 x 2 source-drain shared array.
  • the array Based on a 2 ⁇ 2 array layout of a composite dielectric gate photodetector, the array consists of four pixels, each of which includes a phototransistor and a read transistor, and the phototransistor and read transistor are formed on the same P-type semiconductor substrate.
  • the layers are not connected to each other, and the control gates of the four phototransistors are not connected to each other;
  • the substrates of the four read transistors are connected in a positive octagonal ring structure and located at the center of the 2 ⁇ 2 array;
  • four heavily doped N+ regions are formed by N+ ion implantation in the substrate not covering the composite dielectric gate, and the four heavily doped N+ regions are opposite to each other and at right angles to each other, wherein two opposite The heavily doped N+ region interconnects form a shared N+ source, and the other two opposite heavily doped N+ regions interconnect form a shared N+ drain;
  • four of the phototransistors are located outside the positive octagonal ring structure It is not performed in
  • the phototransistor and the read transistor are separated in the substrate by a shallow trench isolation region; the charge coupled layer of the phototransistor is connected to the charge coupled layer of the read transistor, the photosensitive The control gate of the transistor is connected to the control gate of the read transistor.
  • phototransistors are separated by a shallow trench isolation region in the P-type semiconductor substrate.
  • control gate surface and the substrate of the phototransistor is a transparent or translucent window of wavelength detected by the detector.
  • control gates of the four phototransistors respectively constitute a word line WL0, a word line WL1, a word line WL2, and a word line WL3, and the drains of the four read transistors constitute a drain line DL, and the four The source of the read transistor constitutes the source line SL.
  • the invention is based on the working method of a 2 ⁇ 2 array layout of a composite dielectric gate photosensitive detector, comprising the following steps:
  • the substrate of the photosensitive detector is negatively biased, and the word line WL0, the word line WL1, the word line WL2 and the word line WL3 are simultaneously applied with the same zero bias or positive bias, and the read transistor drain line DL and the source line SL are grounded. ;
  • the read transistor drain line DL is positively biased, and the read transistor source line SL is grounded.
  • the bias voltage applied when the exposure is maintained on the control gate of the read phototransistor, and the photoelectron signals in the four phototransistors are sequentially read in the above manner;
  • the word line WL0, the word line WL1, the word line WL2, and the word line WL3 are added with the same negative bias voltage as the negative bias applied to the substrate, and the read transistor drain line DL and the source line SL are grounded, and the photoelectrons disappear by recombination.
  • the present invention combines the advantages of CCD and CMOS-APS detectors to reduce the number of transistors in a single detector.
  • the array layout designed by the invention can effectively improve the filling factor of the detector pixel and increase the full trap charge capacity, thereby greatly improving the signal-to-noise ratio and the imaging quality of the detector.
  • the array structure of the present invention can reduce the size of the photosensitive detector, realize a high pixel density imaging array, and is compatible with the floating gate CMOS process, and is easy to manufacture.
  • 1 is a structural layout diagram of a 2 ⁇ 2 source-drain shared array based on a composite dielectric gate MOSFET photosensitive detector
  • Figure 2 is a cross-sectional view of Figure 1 taken along the aa' direction;
  • Figure 3 is a cross-sectional view of Figure 1 taken along the bb' direction;
  • Figure 4 is a cross-sectional view taken along line cc' of Figure 1;
  • Figure 5 is a cross-sectional view of Figure 1 taken along the dd' direction;
  • FIG. 6 is an equivalent circuit diagram of a 2 ⁇ 2 source-drain shared array based on a composite dielectric gate MOSFET photodetector
  • Figure 7 is a capacitance model diagram of a single detection unit.
  • This embodiment provides a 2 ⁇ 2 source-drain shared array layout based on a composite dielectric gate MOSFET photosensitive detector, the layout of which is shown in FIG. 1 , the 2 ⁇ 2 array includes 4 detecting units, and each detecting unit includes a photosensitive unit.
  • the phototransistor 1 and the read transistor 2 are formed on the same P-type semiconductor substrate 3, and both of them adopt a composite dielectric gate. Specifically, the underlying insulating dielectric layer 4 and the electric charge are sequentially disposed from the bottom to the top of the substrate 3.
  • the phototransistor 1 and the P-type semiconductor substrate 3 under the read transistor 2 are separated by shallow trench isolation (STI) 8.
  • STI shallow trench isolation
  • the phototransistor 1 and the charge-coupling layer of the read transistor 2 are connected, and the photo-sensing transistor 1 is connected to the control gate of the read transistor 2 to read the photoelectron signal by charge coupling.
  • an N-type source 9a is formed by ion implantation on the side of the P-type semiconductor substrate 3 close to the underlying insulating dielectric layer 4, and an N-type drain 9b is formed by ion implantation on the opposite side.
  • the structure of the detector can be referred to the disclosure of the CN102938409A patent.
  • the four detecting units 11a, 11b, 21a and 21b form a square 2 x 2 array, and the active regions 16 of the four read transistors 2 are connected in a regular octagonal annular structure at the center of the entire 2 x 2 array.
  • the region not covering the composite dielectric gate forms four heavily doped N+ regions by N+ ion implantation, and four heavily doped N+ regions.
  • the two sides are opposite each other and are at a right angle of 90 degrees.
  • the photoreceptor transistor 1 is located on the outer side of the four slanted sides of the regular octagonal ring structure, that is, on the outside of the four regions where the N+ heavily doped region is not performed.
  • the four phototransistors 1 are separated by a shallow trench isolation region 8 in the P-type semiconductor substrate, and the charge-coupling layers 5 of the four phototransistors 1 are not connected to each other, and the control gates 7 of the four phototransistors 1 are connected. They are also disconnected from each other. At least one of the control gate surface of the phototransistor 1 and the substrate is a transparent or translucent window of wavelength detected by the detector.
  • the charge coupled layers 5 of the phototransistors 1 in the four detecting units 11a, 11b, 21a, and 21b are not connected to each other, and the phototransistors 1 of the four detecting units 11a, 11b, 21a, and 21b are The control gates 7 are also not connected to each other.
  • the read transistor 2 of the detecting unit 11a and the read transistor 2 of the detecting unit 11b share the same source 9a
  • the read transistor 2 of the detecting unit 21a and the read transistor 2 of the detecting unit 21b share the same source 9a, two The source is mutually exchanged through the contact hole (CT) 12, the metal 1 (M1) 13, the via 1 (V1) 14, the metal 2 (M2) 10, the via 2 (V2) 15, and the metal 3 (M3) 11. even.
  • the read transistor 2 of the detecting unit 11a and the read transistor 2 of the detecting unit 21a share the same drain 9b, and the read transistor 2 of the detecting unit 11b and the read transistor 2 of the detecting unit 21b share the same drain 9b, two The drains are interconnected by a contact hole (CT) 12, a metal 1 (M1) 13, a via 1 (V1) 14, and a metal 2 (M2) 10, as shown in FIG.
  • CT contact hole
  • M1 metal 1
  • V1 via 1
  • M2 metal 2
  • FIG. 6 shows an equivalent circuit diagram of a 2 ⁇ 2 source-drain shared array, with a dashed box indicating a detection unit, and control gates 7 of the photodetectors 1 of the four detection units form word lines WL0, WL1, WL2, and WL3, respectively.
  • the source 9a shared by the read transistor 2 forms the source line SL
  • the drain 9b shared by the read transistor 2 forms the drain line DL.
  • the word lines WL0, WL1, WL2 and WL3 are added with the same positive bias or zero bias, and the source line SL and the drain line DL are grounded;
  • the drain line DL is positively biased, the source line SL is grounded, and a ramp is added to the word line of the photodetector 1 of the detecting unit to be read.
  • the voltage is calculated by reading the value of the ramp voltage when the transistor 2 is turned on. After the reading of one detecting unit is completed, the drain line DL and the source line SL are grounded, and the control gate 7 of the read photo transistor 1 is read.
  • the bias voltage applied when the exposure is maintained; the photoelectron signals of the remaining detecting units are sequentially read as described above;
  • the word line WL0, the word line WL1, the word line WL2, and the word line WL3 are added with the same negative bias voltage as the negative bias applied to the substrate, and the read transistor drain line DL and the source line SL are grounded, and the photoelectrons disappear by recombination.
  • the pixel fill factor is defined as the ratio of the area of the effective phototransistor in one pixel to the area of one pixel. According to the same design rule, if the area of a single pixel is 2 um ⁇ 2 um, the source-drain shared array according to the present invention
  • the cell layout design has a fill factor of 70%, while the existing discrete method has a fill factor of less than 60%. At the same time, as the size of the pixel is further reduced, the present invention has an advantage of higher fill factor compared to the discrete drawing method.
  • the 2 ⁇ 2 detector array of the present invention can increase the fill factor of the pixel and improve the sensitivity of the detecting unit.
  • the reason is as follows:
  • the relationship between the threshold voltage change of the read transistor 2 and the number of photoelectrons collected by the phototransistor 1 is as follows:
  • C 1 represents the capacitance of the underlying insulating dielectric layer 4 of the phototransistor 1
  • C 2 represents the capacitance between the charge coupled layer 5 of the phototransistor 1 and the control gate 7
  • ⁇ Q represents the number of photoelectrons collected by the phototransistor 1
  • ⁇ V cg represents 5 variation charge coupled layer potential

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Abstract

本发明公开了一种基于复合介质栅光敏探测器的2×2阵列布局及工作方法。阵列由四个像元组成，每个像元包括一个感光晶体管和一个读取晶体管，这两者形成在同一P型半导体衬底上方，并均采用复合介质栅结构；四个读取晶体管的衬底连成正八边环形结构并位于阵列的中心；正八边环形结构的四条边中，未覆盖复合介质栅的衬底中形成四个两两相对且互呈直角的重掺杂N+区，其中两个相对的重掺杂N+区互连构成共享的N+源极，另外两个互连构成共享的N+漏极；四个感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。本发明可以显著提高光敏探测器的填充系数，实现高的满阱电荷容量，且与浮栅CMOS工艺兼容，易于制造。

Description

基于复合介质栅光敏探测器的2×2阵列布局及工作方法 技术领域
本发明涉及成像器件阵列版图布局，尤其涉及一种应用于可见光、红外的探测器阵列版图布局及其阵列的工作方法。
背景技术
CCD和CMOS-APS是当前最为常见的两种成像器件。较早出现的CCD，其基本结构是一组组串联而成的MOS电容，通过MOS电容上的脉冲时序控制半导体表面势阱的产生和变化，以此实现光生电荷的存储和转移读出，这种方法造成CCD的成像速度较慢，同时CCD对工艺的要求极高，使其成品率低，成本较大。CMOS-APS通常由一个感光二极管和三至六个晶体管组成，采用更多晶体管意味着具备更加复杂的功能，CMOS-APS采用X-Y寻址方式读取信号，因此其成像速度较CCD快，同时CMOS-APS与CMOS工艺兼容，易于与外围电路整合，但因其像元中包含多个晶体管，其像元的填充系数低，这使得CMOS-APS的满阱电荷量低，为保证高的成像质量，像元尺寸很难进一步缩小。
通过上述比较发现，如果CMOS-APS成像探测器具有高填充系数，则既可以提高探测器的成像质量，又可以缩小像元尺寸。在已有专利CN201210442007中，提出了一种基于复合介质栅MOSFET的双晶体管光敏探测器，该探测器通过两个晶体管将探测器信号的收集功能和读取功能分开，使得探测器的感光部分不需要制作源漏，可以有效地防止感光晶体管之间互相的干扰。
发明内容
针对以上现有技术中存在的技术问题，本发明通过优化光敏探测器阵列的版图布局，提出了一种基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列版图布局方案，旨在提高光敏探测器的填充系数，尤其是针对小尺寸像元。本发明的另外一个目的是提供该2×2源漏共享型阵列的工作方法。
为实现上述发明目的，本发明采用的技术方案如下：
基于复合介质栅光敏探测器的2×2阵列布局，阵列由四个像元组成，每个像元包括一个感光晶体管和一个读取晶体管，感光晶体管和读取晶体管形成在同一P型半导体衬底上方，两者均采用复合介质栅的结构，所述复合介质栅自下而上依次为底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，其中，四个感光晶体管的电荷耦合层之间互不相连，四个感光晶体管的控制栅极之间互不相连；四个所述读取晶体管的衬底连成正八边环形结构，并位于2× 2阵列的中心位置；正八边环形结构的四条边中，未覆盖复合介质栅的衬底中通过N+离子注入形成四个重掺杂N+区，四个重掺杂N+区两两相对且互呈直角，其中，两个相对的重掺杂N+区互连构成共享的N+源极，另外两个相对的重掺杂N+区互连构成共享的N+漏极；四个所述感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。
进一步地，每个像元中，所述感光晶体管和读取晶体管在衬底中通过浅槽隔离区隔开；所述感光晶体管的电荷耦合层和读取晶体管的电荷耦合层相连，所述感光晶体管的控制栅极和读取晶体管的控制栅极相连。
进一步地，四个所述感光晶体管之间在P型半导体衬底中使用浅槽隔离区隔开。
进一步地，所述感光晶体管的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
进一步地，四个所述感光晶体管的控制栅极分别构成字线WL0、字线WL1、字线WL2和字线WL3，四个所述读取晶体管的漏极构成漏线DL，四个所述读取晶体管的源极构成源线SL。
本发明基于复合介质栅光敏探测器的2×2阵列布局的工作方法，包括如下步骤：
(1)光电子的收集：
在光敏探测器的衬底加负偏压，字线WL0、字线WL1、字线WL2和字线WL3同时加相同的零偏压或正偏压，读取晶体管漏线DL和源线SL接地；
(2)光电子的读取：
保持衬底的负偏压，保持字线WL0、字线WL1、字线WL2和字线WL3上所加的偏压，读取晶体管漏线DL加正偏压，读取晶体管源线SL接地，在需要读取的感光晶体管的字线上加一斜波电压，通过读取晶体管导通时的斜波电压值推算光电子信号；读取结束后，读取晶体管漏线DL和源线SL接地，在已读取的感光晶体管的控制栅极上保持曝光时所加的偏压，按照上述方式依次读取四个感光晶体管中的光电子信号；
(3)光电子的复位：
字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压，读取晶体管漏线DL和源线SL接地，光电子通过复合消失。
本发明结合CCD和CMOS-APS探测器的优点，减少了单个探测器中晶体管的数量。相比现有技术中的分立画法，本发明设计的阵列版图布局能有效地提高探测器像元的填充系数，增大满阱电荷容量，从而大大提高探测器的信噪比及成像质量。同时，本发明的阵列结构可以减 小光敏探测器的尺寸，实现高像素密度成像阵列，且与浮栅CMOS工艺兼容，易于制造。
附图说明
图1为基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列布局结构图；
图2为图1沿aa’方向的剖面图；
图3为图1沿bb’方向的剖面图；
图4为图1沿cc’方向的剖面图；
图5为图1沿dd’方向的剖面图；
图6为基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列的等效电路图；
图7为单个探测单元的电容模型图。
具体实施方式
本实施例提供一种基于复合介质栅MOSFET光敏探测器的2×2源漏共享型阵列布局，其版图如图1所示，2×2阵列包括4个探测单元，每个探测单元包括一个感光晶体管1和一个读取晶体管2。感光晶体管1和读取晶体管2形成在同一P型半导体衬底3上，两者的结构均采用复合介质栅，具体为：衬底3上方自下而上依次设有底层绝缘介质层4、电荷耦合层5、顶层绝缘介质层6和控制栅极7。感光晶体管1和读取晶体管2下方的P型半导体衬底3中使用浅槽隔离(STI)8隔开。每个探测单元中，感光晶体管1和读取晶体管2的电荷耦合层相连，感光晶体管1和读取晶体管2的控制栅极相连，通过电荷耦合方式读取光电子信号。对于读取晶体管2，在P型半导体衬底3靠近底层绝缘介质层4的一侧通过离子注入形成N型源极9a，在相对的另一侧通过离子注入形成N型漏极9b。探测器的结构可以参考CN102938409A专利公开的内容。
四个探测单元11a、11b、21a和21b形成正方形的2×2阵列，四个读取晶体管2的有源区16连成正八边环形结构，位于整个2×2阵列的中心位置。在读取晶体管2的正八边环中，处于四条间隔边位置的P型半导体衬底中，未覆盖复合介质栅的区域通过N+离子注入形成四个重掺杂N+区，四个重掺杂N+区两两相对，呈90度直角。将其中两个相对的重掺杂N+区进行互连，构成共享的N+源极，剩余的两个相对的重掺杂N+区进行互连，构成共享的N+漏极。感光晶体管1位于正八边环形结构沿四条斜边的外侧，即处于四个未进行N+重掺杂区域的外侧。四个感光晶体管1之间在P型半导体衬底中使用浅槽隔离区8隔开，且四个感光晶体管1的电荷耦合层5之间互不相连，四个感光晶体管1的控制栅极7之间也互不相连。感光晶体管1的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
如图4所示，四个探测单元11a、11b、21a和21b中的感光晶体管1的电荷耦合层5之间互不相连，四个探测单元11a、11b、21a和21b中的感光晶体管1的控制栅极7之间也互不相连。探测单元11a的读取晶体管2和探测单元11b的读取晶体管2共用同一个源极9a，探测单元21a的读取晶体管2和探测单元21b的读取晶体管2共用同一个源极9a，两个源极之间通过接触孔(CT)12、金属1(M1)13、通孔1(V1)14、金属2(M2)10、通孔2(V2)15和金属3(M3)11进行互连。探测单元11a的读取晶体管2和探测单元21a的读取晶体管2共用同一个漏极9b，探测单元11b的读取晶体管2和探测单元21b的读取晶体管2共用同一个漏极9b，两个漏极之间通过接触孔(CT)12、金属1(M1)13、通孔1(V1)14和金属2(M2)10进行互连，如图5所示。
图6给出了2×2源漏共享型阵列的等效电路图，虚线框表示一个探测单元，四个探测单元的感光晶体管1的控制栅极7分别形成字线WL0、WL1、WL2和WL3，读取晶体管2共用的源极9a形成源线SL，读取晶体管2共用的漏极9b形成漏线DL。
上述2×2源漏共享型阵列的工作方法如下：
(1)光电子收集：
在探测器阵列的衬底加一负偏压，字线WL0、WL1、WL2和WL3加相同的正偏压或零偏压，源线SL和漏线DL接地；
(2)光电子读取：
保持衬底、字线WL0、WL1、WL2和WL3所加的偏压，漏线DL加正偏压，源线SL接地，在需要读取的探测单元感光晶体管1的字线上加一斜波电压，通过读取晶体管2导通时的斜波电压值来推算光电子信号，一个探测单元读取完成后，漏线DL和源线SL接地，在已读取的感光晶体管1的控制栅极7上保持曝光时所加的偏压；按上述方法依次读取剩余探测单元光电子信号；
(3)光电子的复位：
字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压，读取晶体管漏线DL和源线SL接地，光电子通过复合消失。
像元填充系数的定义为一个像元中有效感光晶体管面积占一个像元面积的比值，按照相同的设计规则，如果单个像元面积为2um×2um，按本发明所述的源漏共享型阵列版图布局设计的像元，其填充系数可以达到70％，而现有分立画法的填充系数则低于60％。同时，随着像元尺寸的进一步缩小，本发明相比分立画法，其填充系数高的优势将会进一步提高。
本发明的2×2探测器阵列能增大像元的填充系数，提高探测单元的灵敏度，其原因在于： 读取晶体管2阈值电压变化与感光晶体管1收集的光电子数存在的关系如下：
Figure PCTCN2018080131-appb-000001
其中C 1表示感光晶体管1的底层绝缘介质层4的电容，C 2表示感光晶体管1的电荷耦合层5与控制栅极7之间的电容，ΔQ表示感光晶体管1收集的光电子数，ΔV cg表示电荷耦合层5电势的变化量，探测单元的等效电容如图7所示，由于其余电容相比C 1和C 2均可忽略，简化计算中不予考虑，在单个探测单元面积不变的情况下，电容C 2大小不变，电容C 1因像元填充系数增大而增大，因而公式中等式右侧的系数
Figure PCTCN2018080131-appb-000002
随着填充系数的增大而增大，即单位电荷量转化成电压的增益变大，所以探测单元的灵敏度变大。

Claims (6)

  1. 基于复合介质栅光敏探测器的2×2阵列布局，其特征在于，阵列由四个像元组成，每个像元包括一个感光晶体管和一个读取晶体管，感光晶体管和读取晶体管形成在同一P型半导体衬底上方，两者均采用复合介质栅的结构，所述复合介质栅自下而上依次为底层绝缘介质层、电荷耦合层、顶层绝缘介质层和控制栅极，其中，四个感光晶体管的电荷耦合层之间互不相连，四个感光晶体管的控制栅极之间互不相连；
    四个所述读取晶体管的衬底连成正八边环形结构，并位于2×2阵列的中心位置；正八边环形结构的四条边中，未覆盖复合介质栅的衬底中通过N+离子注入形成四个重掺杂N+区，四个重掺杂N+区两两相对且互呈直角，其中，两个相对的重掺杂N+区互连构成共享的N+源极，另外两个相对的重掺杂N+区互连构成共享的N+漏极；
    四个所述感光晶体管位于正八边环形结构的外侧且处于四个未进行N+重掺杂区域的一侧。
  2. 根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局，其特征在于，每个像元中，所述感光晶体管和读取晶体管在衬底中通过浅槽隔离区隔开；所述感光晶体管的电荷耦合层和读取晶体管的电荷耦合层相连，所述感光晶体管的控制栅极和读取晶体管的控制栅极相连。
  3. 根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局，其特征在于，四个所述感光晶体管之间在P型半导体衬底中使用浅槽隔离区隔开。
  4. 根据权利要求1所述的基于复合介质栅光敏探测器的2×2阵列布局，其特征在于，所述感光晶体管的控制栅极面和衬底至少有一处为探测器所探测波长透明或半透明窗口。
  5. 根据权利要求1-4之一所述的基于复合介质栅光敏探测器的2×2阵列布局，其特征在于，四个所述感光晶体管的控制栅极分别构成字线WL0、字线WL1、字线WL2和字线WL3，四个所述读取晶体管的漏极构成漏线DL，四个所述读取晶体管的源极构成源线SL。
  6. 如权利要求5所述的基于复合介质栅光敏探测器的2×2阵列布局的工作方法，其特征在于，包括如下步骤：
    (1)光电子的收集：
    在光敏探测器的衬底加负偏压，字线WL0、字线WL1、字线WL2和字线WL3同时加相同的零偏压或正偏压，读取晶体管漏线DL和源线SL接地；
    (2)光电子的读取：
    保持衬底的负偏压，保持字线WL0、字线WL1、字线WL2和字线WL3上所加的偏压， 读取晶体管漏线DL加正偏压，读取晶体管源线SL接地，在需要读取的感光晶体管的字线上加一斜波电压，通过读取晶体管导通时的斜波电压值推算光电子信号；读取结束后，读取晶体管漏线DL和源线SL接地，在已读取的感光晶体管的控制栅极上保持曝光时所加的偏压，按照上述方式依次读取四个感光晶体管中的光电子信号；
    (3)光电子的复位：
    字线WL0、字线WL1、字线WL2和字线WL3加与衬底所加负偏压相同的负偏压，读取晶体管漏线DL和源线SL接地，光电子通过复合消失。
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