JP2012135025A - 入れ子状のトランスインピーダンス増幅器 - Google Patents
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- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
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- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45531—Indexing scheme relating to differential amplifiers the FBC comprising a parallel resonance circuit and being coupled between the LC and the IC
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- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
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Abstract
【解決手段】入れ子状のトランスインピーダンス増幅器(TIA)回路は、入力及び出力を有する0次のTIAと、第1の演算増幅器(オペアンプ)と、を備えている。オペアンプは、0次のTIAの出力に接続する入力と、該入力によって駆動される第1のトランジスタと、第1のバイアス電圧によって駆動され且つ上記第1のトランジスタに接続する第2のトランジスタと、第2のトランジスタに接続する第1の電流源と、第1のトランジスタと第2のトランジスタの間のノードに存在する出力と、を備えている。
【選択図】図26
Description
Claims (15)
- 第1の入力及び第1の出力を有する0次のトランスインピーダンス増幅器(TIA)と、
第1の演算増幅器(オペアンプ)であって、
前記0次のTIAの前記第1の出力に直接接続する第1の入力、
該第1のオペアンプの前記第1の入力によって駆動される第1のトランジスタ、
第1のバイアス電圧によって駆動され、且つ、前記第1のトランジスタに直列接続する第2のトランジスタ、及び
前記第1のトランジスタと前記第2のトランジスタの間のノードにある第1の出力、
を有する、該第1のオペアンプと、
を備え、
前記0次のTIAが、
第2の入力及び第2の出力を有する第2のオペアンプと、
第3の入力及び第3の出力を有し、該第3の入力が前記第2の出力に接続されている第3のオペアンプと、
前記第3の出力に接続する第1端、及び、前記第3の入力に接続する第2端を有する第1の抵抗と、
を有し、
前記第1のオペアンプの前記第1の出力に接続する第1端、及び、(i)前記0次のTIAの前記第1の入力と(ii)前記第2のオペアンプの前記第2の入力に接続する第2端を有する第2の抵抗を更に備える、
入れ子状のTIA回路。 - 前記第2のトランジスタに接続する第1の電流源と、
前記第1のトランジスタに接続する第2の電流源と、
を更に備える、請求項1記載の入れ子状のTIA回路。 - 前記第1のオペアンプの利得が、前記0次のTIAの利得より大きく、前記第1のオペアンプの帯域幅が、前記0次のTIAの帯域幅より小さい、請求項1記載の入れ子状のTIA回路。
- 前記0次のTIAが、第2の入力及び第2の出力を有する0次の差動モードTIAであり、
前記第1のオペアンプが、差動モードオペアンプであり、
前記0次のTIAの前記第2の出力に接続する第2の入力、
前記第1のオペアンプの前記第2の入力によって駆動される第3のトランジスタ、
第1のバイアス電圧によって駆動され、且つ、前記第3のトランジスタに接続する第4のトランジスタ、
前記第2のトランジスタに接続する第1の電流源、
前記第4のトランジスタに接続する第2の電流源、及び
前記第3のトランジスタと前記第4のトランジスタの間の接続部にある第2の出力、
を有する、
請求項1記載の入れ子状のTIA回路。 - 前記第1のトランジスタ及び前記第3のトランジスタに接続する第3の電流源を更に備える、請求項4に記載の入れ子状のTIA回路。
- 前記第2のオペアンプは、複数の入力及び複数の出力を有する第2の差動モードオペアンプを含み、
前記第3のオペアンプは、複数の入力及び複数の出力を有する第3の差動モードオペアンプであって、該第3の差動モードオペアンプの前記複数の入力がそれぞれ、前記第2の差動モードオペアンプの前記複数の出力のうち対応の出力に接続している、該第3の差動モードオペアンプを含み、
第1端及び第2端を有する複数の抵抗を更に備え、
該複数の抵抗の前記第1端が前記第3の差動モードオペアンプの前記複数の入力に接続しており、該複数の抵抗の前記第2端が前記第3の差動モードオペアンプの前記複数の出力に接続している、
請求項4に記載の入れ子状のTIA回路。 - 前記第1のオペアンプの前記第2の出力に接続する第1端、及び、(i)前記0次のTIAの前記第2の入力と(ii)前記第2のオペアンプの入力に接続する第2端を有する第3の抵抗を更に備える、請求項4に記載の入れ子状のTIA回路。
- 第1の電圧を前記0次のTIAに与える第1の電源入力と、
第2の電圧を受ける第2の電源入力と、
前記0次のTIAに与えられる前記第1の電圧と前記第2の電圧とに基づいて第3の電圧を生成する電荷ポンプモジュールと、
を更に備え、
前記第3の電圧が、前記第1のオペアンプの電源入力に与えられる、
請求項1に記載の入れ子状のTIA回路。 - 前記第3のオペアンプの前記第3の入力が、前記第2のオペアンプの前記第2の出力に直接接続されている、請求項1に記載の入れ子状のTIA回路。
- 第1端及び第2端を有する第2の抵抗を更に備え、該第2の抵抗の該第1端が前記0次のTIAの前記第1の出力及び前記第1のトランジスタの前記第1の入力に直接接続されており、該第2の抵抗の該第2端が前記0次のTIAの前記第1の入力に直接接続されている、請求項1に記載の入れ子状のTIA回路。
- 前記0次のTIAは、0次の差動モードTIAであり、該0次のTIAは、
第2の入力及び第2の出力、
前記第3のオペアンプの入力と出力の間に接続された第3の抵抗、並びに、
前記第1のオペアンプの第2の出力に接続される第1端、及び、(i)前記第2のオペアンプの入力と(ii)前記0次のTIAの前記第2の入力に接続する第2端を有する第4の抵抗
を含む、請求項1に記載の入れ子状のTIA回路。 - 前記第1のオペアンプは差動モードオペアンプであり、該第1のオペアンプは、
前記0次のTIAの前記第2の出力に接続する第2の入力、
前記第1のオペアンプの前記第2の入力によって駆動される第3のトランジスタ、
第1のバイアス電圧によって駆動され、前記第3のトランジスタに直列接続された第4のトランジスタ、及び、
前記第3のトランジスタと前記第4のトランジスタの間のノードにある第2の出力
を含む、請求項11に記載の入れ子状のTIA回路。 - 前記第1のオペアンプは、
前記第1のトランジスタと前記第2のトランジスタの間に接続されており、第2のバイアス電圧によって駆動される第5のトランジスタ、及び、
前記第3のトランジスタと前記第4のトランジスタの間に接続されており、前記第2のバイアス電圧によって駆動される第6のトランジスタ
を更に含む、請求項12に記載の入れ子状のTIA回路。 - 前記第1のオペアンプは、
該第1のオペアンプの前記第1の入力によって駆動される第5のトランジスタ、
前記第5のトランジスタとグランド基準電位の間に接続された第6のトランジスタ、及び、
第2のバイアス電圧によって駆動され、前記第5のトランジスタと前記第6のトランジスタの間に接続された第7のトランジスタ
を更に含む、請求項12に記載の入れ子状のTIA回路。 - 前記第2のトランジスタと前記グランド基準電位との間に接続された第8のトランジスタを更に備え、
前記第6のトランジスタの制御端子が、(i)前記第7のトランジスタの出力と前記第8のトランジスタの制御端子に接続されている、
請求項14記載の入れ子状のTIA回路。
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Application Number | Priority Date | Filing Date | Title |
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US75989906P | 2006-01-18 | 2006-01-18 | |
US60/759899 | 2006-01-18 | ||
US79856706P | 2006-05-08 | 2006-05-08 | |
US79848006P | 2006-05-08 | 2006-05-08 | |
US60/798567 | 2006-05-08 | ||
US60/798480 | 2006-05-08 | ||
US81726806P | 2006-06-29 | 2006-06-29 | |
US60/817268 | 2006-06-29 | ||
US11/495,813 US7551024B2 (en) | 2001-03-13 | 2006-07-28 | Nested transimpedance amplifier |
US11/495813 | 2006-07-28 |
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JP2007009337A Division JP5010293B2 (ja) | 2006-01-18 | 2007-01-18 | 入れ子状のトランスインピーダンス増幅器 |
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JP2012037544A Expired - Fee Related JP5367857B2 (ja) | 2006-01-18 | 2012-02-23 | 入れ子状のトランスインピーダンス増幅器 |
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EP (1) | EP1811657B1 (ja) |
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US7405616B2 (en) | 2008-07-29 |
US7551024B2 (en) | 2009-06-23 |
SG134250A1 (en) | 2007-08-29 |
JP2007208972A (ja) | 2007-08-16 |
US20070103231A1 (en) | 2007-05-10 |
US7626453B2 (en) | 2009-12-01 |
US7616057B2 (en) | 2009-11-10 |
TWI416864B (zh) | 2013-11-21 |
JP5367857B2 (ja) | 2013-12-11 |
US7808311B2 (en) | 2010-10-05 |
TW200731659A (en) | 2007-08-16 |
TW200733547A (en) | 2007-09-01 |
US8159293B2 (en) | 2012-04-17 |
EP1811657A2 (en) | 2007-07-25 |
US20070096808A1 (en) | 2007-05-03 |
US20080272848A1 (en) | 2008-11-06 |
TWI420804B (zh) | 2013-12-21 |
US20110018627A1 (en) | 2011-01-27 |
US20060261892A1 (en) | 2006-11-23 |
JP5010293B2 (ja) | 2012-08-29 |
EP1811657A3 (en) | 2009-03-04 |
EP1811657B1 (en) | 2019-03-13 |
US20100073083A1 (en) | 2010-03-25 |
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