TWI223499B - Nested chopper delta-sigma modulator - Google Patents

Abstract

A nested chopper circuit includes a first chopper section, which is coupled to input terminals and is controlled by a pair of non-overlapping clocks, and a second chopper section, which is coupled to the first chopper section and is controlled by a pair of chopper clocks. The pair of non-overlapping clocks is a multiple of the pair of chopper clocks, and the non-overlapping clocks are configured to invert on a period continuously. When the pair of chopper clocks (Phi11 and Phi12) controls switches S1, S2, S3, and S4 of the second section, these switches follow the following logic when operated in conjunction with the pair of non-overlapping clocks (PhiA and PhiB): switches S1 and S4: PhiA*Phi11+PhiB*Phi12; and switches S2 and S3: PhiA*Phi12+PhiB*Phi11. A method for chopping an analog input signal for sampling also is described.

Description

1223499

The technical field to which the invention belongs: b The present invention relates to chopper circuits, in particular a chop that can reduce residual noise caused by the mismatch between the input terminals of the chop switch. Wave circuit. Prior technology:

In the application of analog digital converters, the accuracy and feasibility of the delta-sigma modulator makes it popular in many circuit applications, such as audio code circuits (aud i 0 codec circuits), communication circuits (Communication circuits), sensor circuits (sensor circuits), and test equipment circuits (instrumentation circuits). The performance of delta-sigma modulators is related to the input noise generated by switches, operational amplifiers, and digital circuits. This noise reduces the dynamic range of the input signal.

In the low frequency band, the increase of flicker noise is proportional to the decrease of the frequency ', while in the relatively low frequency band, the offset is dominated by the offset value', especially in the sensor whose operating efficiency is limited Circuit in the circuit interface. In the conventional technique, 'correlation 1 atedd ub 1 e sampling', self-calibrating operational ampl if iers, and chopper-stabi lized techniques are used to Handle this kind of noise. These techniques are classified into two categories: autozeroing and chopping, and can be used in amplifiers and integrators. Articles by Υ · Η · Chang, T.C. Wu and C.Y. Wu

1223499 V. Description of the invention (2) '丨 Chopper-stabi 1 i zed sigma-delta modulator, 丨 IEEE ISCAS, ρρ · 1 28 6- 1 289, May 1 9 93 The chopped triangle integral modulator is mentioned ( delta-sigma modulator) plus traditional operational amplifiers can have better immunity to low-frequency noise, but the chopping also generates residual noise due to the mismatch of electrical injection between the switches (esidua 1 noi se) . The ON and OFF of the switch also pulses the input of the delta-sigma modulator. These high-frequency switching signals will reduce the SNDR and resolution of the system as the input signal enters the modulator. Another method is by A. Bakker, K. Thiele, and J.H.

Huij sing in `` A CMOS nested-chopper instrumentation amplifier with 100-nV offset, 1 丨 IEEE J. Solid-State Circuits, vol · 35 · 12, pp · 1 877 -1 883, Dec · 2 000 put forward. It mentions that a nested-chopper ampl if ier will reduce the residual noise (res i dual noise). If it is used on a delta_sigma modulator, it will eliminate the OP AMP compensation value. (〇ff set) and related low-frequency noise. However, the front-end modulator is still affected by the high-frequency noise caused by the mismatch between the sampling switches. Another method is proposed by CB Wang in, A 20 bit 25kHz delta-sigma A / D converter utilizing frequency-shaped chopper stabilization scheme, M IEEE custom integrated circuits conference, pp. 9-12, 2000. Frequency Group Chopped Stable Delta Integral Analogy

0389-9168TWF (Nl); P910009TW; EDWARD.ptd Page 7 1223499 V. Description of the invention (3) Digital converter (frequency-shaped chopper stabilized delta-sigma A / D converter) can be used to remove clock spikes (clock spikes) noise). The chopper clock is generated by inputting a pseudo-random clock to a digital filter. The ‘50 Hz digital crossing has two zeros at DC and the half-sampling frequency (h a 1 f s a m p 1 i n g frequency). And the clock noise does not appear in the specified frequency band. The high-frequency noise in the automatic zeroing (a u t 〇 z e r 〇 n g) method of sampling from the input switch will be returned to the specified frequency band. Similarly, the advantages of the chopping technology

The point is that in the application of the delta-sigma modulator, the noise is lower than that of the auto-zero (311 ^; 〇261'0 丨 118) method. Therefore, in the future, we will need a circuit or method that can effectively reduce the noise generated when performing analog-to-digital conversion of an input signal. Summary of the Invention: In order to solve the above problems, the present invention proposes to use a nested chopper delta-sigma modulator as a solution. The residual noise caused by the mismatch between the input terminals of the chopper switch (residual no 1 se) can be reduced using closed circuits. The present invention can be applied to many aspects, such as a process, a system, or a device. Several specific applications will be revealed below. • First we need a nested chopper circuit, which contains a first chopper section coupled to the input and controlled by a pair of non-overlapping clocks. One

1223499 V. Description of the invention (4) The first chopping part is combined with the first chopping part, and the output of the first chopping part is connected to the input of the second chopping part, where the second chopping part is Controlled by a pair of non-overlapping clocks that are periodically opposite to each other. The pair of clocks consists of several chopper clocks. A nested chopper circuit is coupled to a delta-sigma modulator circuit, and the periodic destination clock samples the positive and negative input signals and then refers this sampling to the output of the φΛΓΛ wave part. Human side. -For non-overlapping clocks, it is composed of ΦΑ at this chopping time and nW for chopping clock ^ Φ11 * Φ12. When SHU. / Shili operates together, the following logic is available: S1 & S4. ΦΑ · Φ11 + φβ · ㈣, 铒 Β · φΐι. S2 & S3 · φA · φ 1 2+ Φ The first chopper part has two external chopper parts controlled by the first driver switch and the two non-heavy and heavy second-child bismuth parts. The second switch controls the internal switches, and the second non-overlapping clock and the second NOT: = 4 switches controlled. The first aspect of the present invention provides a periodicity that can be inverted. method. When there is a signal at the input, a clock that is larger than the input signal for sampling enters the first chopping section and the other pair of non-overlapping, which is periodically inverted, enters the second chopping section. Among them, the non-phase-inverted chopper clock is composed of clocks. The input signal is executed when the first heavy f clock is counted by an infinite number of choppers, and is sampled in the forward wave portion and the second chopper portion of the input signal so that the above-mentioned samples of the present invention are sampled from degrees and reverse periods. . And advantages can be more obvious Yiyi's characteristics, 1 0389-9168TWF (N1); P910009TW; EDWARD.p t d $ 9 pages 1223499

The preferred embodiment is described in detail in conjunction with the accompanying drawings. Here are some specific explanations as follows: Implementation: As shown in Figure 1, the chopping cycle of the Qianxi group / tongue-shaped m100 'is owned by two Several B's. The chopper 100 (such as the switch 4 and the system controlled by the stacked clocks ㈣ and 。. The nested chopper 100; the person and the 4 are not controlled) is controlled by the clock 011 and Φ12 part 104. The above is controlled by the first chopper A and ΦB which is matched with the input terminal, and the first skin is wide. 4 is divided by-pair of non-overlapping clocks. The first extinguishing, * a first chopping section 102 is coupled to the input terminal of the first chopping section, and the output terminal is controlled by the second chopping section 102.苴 中 一 射 ίϊ; · i JL's clocks ΦA and Φ, which are composed of chopped clocks Φ11 & Φ12, are composed of several chopped clocks and are periodically opposite to each other. The relevant pulses are as shown in the second A m ^ ^ ^, and rr steals 4 筮 9 R min map, but is demodulated by another chopping wave.

The large pulse is shown in Figure 2B. Oa feather AJ's nested chopping because the input is in the middle, a traditional clock is crying, and the night is fighting ^ t ^ The double frequency shift will adjust the signal ^ σσ ^ x…, method is directly connected to the front of the modulator. Therefore, the nested chopper 100 based on chopper stabilization technology is based on the integral modulator (uelta-slgffla modulator). Used for a corner First, the input signal is modulated to the high frequency band by the previous chopping. Then, a delta-sigma modulator with 1-band noise is demodulated, and the following chopper circuit is used to demodulate this signal. In order to overcome the _ ^ generated by the chopped chopped wave, a nest-like chopped dihedral integral modulator as shown in the figure is used.

1223499 V. Description of the invention (6) (nested chopper delta-sigma modulator). The noise spike generated by the chopper switch is reversed to a tunable period, so the average residual noise (averageresidua 1 n 〇ise) is reduced or eliminated, so that the modulator SNR has Improved. As shown in Figure 2A, the forward and reverse signals are alternately input to the modulator. Therefore, when φ A is 0 N, the control signals of s 1 and s 4 are ① 11 and the control signals of s 2 and s 3 are Φ 12. Please refer to Figures 2C and 2D for the status of the switches.

To maintain the operation of the chopper-stabilized modulator, the clock of the nested chopper is changed according to the present invention. In 104 of Fig. 1, when ΦA is ON, the function of the nested chopper 00 is the same as that of a single chopper circuit. As shown in FIG. 2C, in 10a, si and s4 are 0N when the phase angle is Φ1 1; in 1021), s2 and 33 are ON when the phase angle is Φ12. As shown in FIG. 2D, in 〇4b, ΦΒ is ON. In order to maintain the forward and reverse signals to be input to the modulator alternately, s2 and s3 in 102b are ON when the phase angle is Φ11, and si and s4 in 102a are ON when the phase angle is Φ12. . Therefore, the control logic of si, s2, s3, and s4 is: S1 & S4: ΦΑ · Φ11 + ΦΒ · Φ12 S2 & S3: ΦΑ · Φ12 + ΦΒ · φ11

Therefore, nested chopper del ta-sigma modulator can reduce residual noise (residuai no i se) and has lower low-frequency noise. Nested chopper delta-sigma modulator's structure and simple operation allow anyone skilled in the art to use it

0389-9168TWF (Nl); P910009TW; EDWARD.ptd

1223499 V. Description of the invention (7) On CMOS integrated circuit. Figure 3 shows a block diagram of a secondary differential nested chopping delta-sigma modulator with thermal noise and operational amplifier noise. The thermal noise 11 shown in the figure is the thermal noise of the first resonator and the non-linear output of the operational amplifier and the noise of the operation amplifier, and the nested chopper 100 is the first in the DSM (delta_sigma modulator). Before op amp. In Figure 4, the nested chopper 100 is moved to the output of the operational amplifier, and the switch can be simplified to a single NMOS switch due to the virtual ground input of the operational amplifier. However, feedback should include chopper-like logic that can correct positive and negative feedback. Figure 5 shows the dB vs. Hz plot of a chopping tip pulse with an input signal of -6dB, 578125kHz, a sampling frequency of 2.56MHz, and a maximum value of 0.55 // V. There are three examples in this figure. First, the top of the figure is one of the conventional techniques, a chopped stable DSM with residual noise (residua 1 noise). Second, the middle of the figure is a nested chopped DSM with residual noise of the present invention. Finally, the bottom of the figure is a perfect chopper-stabilized DSM with no residual noise. As shown, the residual noise of the second example is lower than that of the first example in the lower frequency band. Therefore, the present invention can effectively suppress unwanted input synthesis noise. Fig. 6 is a graph of SNDR vs. input amplitude, in which the peak SNDR of the nested chopped DSM of the present invention is 69.9 dB at 22,05 kHz and 86.3 dB at 8 kHz. The present invention is also applicable to various computer-related operations that require clever use of substances, such as data stored in a computer. Usually these quantities pass

1223499

1223499

Figure 1 shows the circuit diagram of the delta-sigma modulator of the nested chopper triangle integral modulation of the present invention. Figure 2 (A) shows a pair of non-overlapping clocks and a chopper clock. The double chirped 苐 2 (B) diagram shows the pulses after being demodulated by another chopper. Figures 2 (C) and 2 (D) show switches operating on a pair of non-overlapping clocks and chopper clocks. Figure 3 shows an example of a nested chopper delta-sigma modulator with thermal noise and the second derivative of the operational amplifier. Figure 4 shows another example of a nested chopper delta-sigma modulator with thermal noise and secondary differentiation of the operational amplifier. Figure 5 shows the dB vs. Hz plot of a chopping tip pulse with an input signal of -6 dB, 5.78125k Hz, a sampling frequency of 2.56MHz, and a maximum value of 0.5 // V. Figure 6 shows the SNDR vs. input amplitude map. Explanation of symbols: Φ 11 ~ phase angle 1 1 Φ 1 2 ~ phase angle 12 Φ A ~ phase angle A Φ B ~ phase angle B S1 ~ switch 1 S2 ~ switch 2

0389-9168TWF (N1); P910009TW; EDWARD.p td Page 14 1223499 Simple illustration of the diagram S3 ~ Switch 3 S4 ~ Switch 4 ΙΗΪ 0389-9168TWF (N1); P910009TW; EDWARD.ptd Page 15

Claims (1)

1223499 The scope of the patent application includes 1: nested chopper circuit, in which the second port is lightly connected to the input terminal, and ^ == not controlled by the heavy clock; and itl U 邛It is coupled to the above-mentioned first chopping part, wherein the first chopping part is given to Φ / 、 丁 上 #, and i A is output and connected to the input system of the second chopping part; a chopping part Controlled by a pair of first and second chopper clocks and the first non-overlapping clock is composed of the above-mentioned several chopper clocks, the first one above; 5 flutes and the first non-overlapping clocks are periodic with each other Inverted. Agency 2. The nested chopper circuit as described in item 1 of the scope of patent application, wherein the nested chopper circuit is coupled to a delta-sigma modulator (delta — sigma) modulator) ° 3. The nested chopper circuit (nes ted chopper ci rcui t) described in item 1 of the scope of the patent application, wherein the clocks which are periodically inverted from each other sample the positive and negative input signals before Sampling is provided to the input of the first chopping section. 4 · The nest chopper circuit (n e s t e d _ chopper circuit) as described in item 1 of the patent claim, wherein the first and second non-overlapping clocks are composed of Φ A and Φ B, respectively. 5. The nested chopper circuit as described in item 4 of the scope of patent application, wherein the first and second chopper clocks are respectively composed of 1223499 6. Scope of patent application Φ 1 1 and Φ 1 2 6. If the scope of the patent application is No. 5 chopper circuit), where upper, +, and 4; nested chopper circuits (nested parts of Si, S2, S3, s'4 switches) The chopper clock controls the second chopper 7 · If the scope of the patent application is No. 6 chopper circuit), in which the nested chopper circuit (nested, the first and second non-overlapping clock together 1 祚 = ^ S 3, S 4 switch on and S1 & S4. · ΦΑ · Φ11 + φΒ = will be based on the following logic: S2 & S3: ΦΑ · Φ12 + ΦΒ · φ !! Including ^ a nested chopping circuit (nestedch〇 ° ppercircu⑴) includes a first chopping part, which is the wave part There are two inputs that are controlled by the first non-overlapping time, of which the first chop is controlled by the second non-overlapping clock: the external switch of the inner 'happy system' and two and a second chopping part. The turn-out end of the first-chopper part to the input end of the chopper part; and the input connected to the second chopper part, wherein the second chopper part is inserted with 4 switches, wherein the first non-repetitive part Cong: 被-^ Bell is powered by the above several chopper clocks. The phase of the overlapping clock is opposite to the phase of the student, and the above phase. The phase of the first non-overlapping clock is inverse 9. As described in item 8 of the scope of the patent application, ch— "lrCU⑴" where the nested chopping Circuit ... ed Page 17 0389-9168TWF (Nl); P910009TW; EDWARD.ptd 1223499 VI. Patent application scope chopper circuit) Lightly connected to a delta-sigma modulator ° I 0 · If the scope of patent application The nested chopper circuit according to item 8, wherein the clock whose phase is periodically inverted can provide the positive and negative input signals required for sampling to the input terminal of the first chopper division. II · Nested chopper circuit as described in item 8 of the scope of patent application, wherein the first and second non-overlapping clocks are composed of Φ A and φ B, respectively 0 1 2 · As applied The nested chopper circuit according to item 11 of the patent scope, wherein the first and second chopper clocks are composed of Φ 1 1 and Φ 1 2 respectively. 1 The nested chopper circuit described in item 2 (nested chopper circuit), wherein the chopper clock controls the SI, S2, S3, and S4 switches of the second chopper section. 1 4 · The nested chopper circuit (ne sted cho ppe rcir cu it) as described in item 13 of the scope of patent application, wherein the above-mentioned S1, S2, S3, and S4 switches are non-overlapping with the above-mentioned first and second The clocks work together according to the following logic: S1 & S4: ΦΑ · Φ11 + ΦΒ · Φ 12; S2 & S3: Φ A · Φ 1 2+ ΦΒ · Φ 11 ° 1 5 · —A kind of analog signal can be cut off for supply Methods of sampling, including: ~ receiving an input signal; 0389-9168TWF (Nl); P910009TW; EDWARD.ptd Page 18 1223499 VI. Patent application scope and when there is a signal at the input end, a pair of periodically inverted phases, the second non-overlapping clock will enter the first chopping section ; The first and second chopper clocks of the second pair will enter the-~ " iff > \ The above-mentioned first and second non-overlapping clocks are counted by countless choppers, and > · It is composed of inches. The above analog input signal passes through the ^ chopping part and the second chopping part, and its continuous periodic reverse phase characteristic can be in the forward and reverse cycles of the analog input signal. Sampling. 16 · As described in item 15 of the scope of patent application, a method that can cut off the analog input signal for sampling is more complicated: the output end of the second chopping part is coupled to a delta-sigma modulation Is (de 1 ta-s i gma modulator) 〇1 7 · As described in item 15 of the scope of patent application, a method for cutting off analog input signals for sampling, wherein the first and second non-overlapping clocks are It consists of Φ A and Φ B. 1 8 · A method for cutting analog input signals for sampling as described in item 17 of the scope of patent application, wherein the first and second chopping clocks are composed of φ 1 1 and φ 1 2 respectively. 1 9 · A method for cutting analog input signals for sampling as described in item 18 of the scope of patent application, wherein the first and second chopping clocks control SI, S2, and s3 of the second chopping section. , S4 switch. 2 0. A method for cutting off analog input signals for sampling as described in item 19 of the scope of patent application, wherein the above S1, S2, S3, and S4 switches are connected to the first and second non-overlapping clocks / starts. It operates according to the following logic IIM 0389-9168TWF (Nl); P910009TW; EDWARD.ptd Page 19 1223499 VI. Patent Application Series · Φ11 + ΦΒ · Φ 12 Φ12 + ΦΒ · Φ 11 S1 & S4: ΦΑ S2 & S3: ΦΑ liiii 0389-9168TWF ( N1); P910009TW; EDWARD.ptd Page 20