TW200425645A - Nested chopper delta-sigma modulator - Google Patents

Abstract

A nested chopper circuit includes a first chopper section, which is coupled to input terminals and is controlled by a pair of non-overlapping clocks, and a second chopper section, which is coupled to the first chopper section and is controlled by a pair of chopper clocks. The pair of non-overlapping clocks is a multiple of the pair of chopper clocks, and the non-overlapping clocks are configured to invert on a period continuously. When the pair of chopper clocks (Φ11 and Φ12) controls switches S1, S2, S3, and S4 of the second section, these switches follow the following logic when operated in conjunction with the pair of non-overlapping clocks (ΦA and ΦB): switches S1&S4: ΦA.Φ11+ΦB.Φ12; and switches S2&S3: ΦA.Φ12+ΦB.Φ11. A method for chopping an analog input signal for sampling also is described.

Description

200425645 V. Description of the invention (1) The technical field to which the invention belongs The present invention relates to chopper circuits, and in particular, it can reduce the remaining noise caused by the mismatch between the input terminals of the chopping switch (Re si dual noise) chopper circuit. Prior technology:

In the application of analog digital converters, the accuracy and feasibility of the delta-sigma modulator makes it popular in many circuit applications, such as audio code circuits (aud i 0codec circuits), communications Cmmunication circuits, sensor drcuits, and instrumentation circuits. The performance of delta-sigma modulators is related to the input noise generated by switches, operational amplifiers, and digital circuits. This noise reduces the dynamic range of the input signal. In low frequency bands, the increase in flicker noise is proportional to the decrease in frequency, and in the relatively low frequency bands, it is dominated by the compensation value (0ff set). Noise is especially in the sensor circuit circuit interface where the system's operating efficiency is limited. In the known technology, 'correlated double sampling (c 〇rre 1 atedd 〇ub 1 e

sampling), self-correcting operational amplifiers (seif_caiibrating operational ampl if iers), and chopper-stabilized techniques (chopper-stabilized techniques) are all used to deal with this kind of miscellaneous sfl ° These techniques are classified as automatic zeroing (au 丨 〇zer 〇 丨 ng) and chopping, and can be used in amplifiers and integrators. Articles by Υ · Η · Chang, T.C. Wu and C.Y. Wu

〇389.9168TW (Nl); P91〇009TW; EDWARD.ptd

200425645 V. Description of the invention (2) " Chopper-stabilized sigma-delta modulator, M IEEE ISCAS, ρ · 1 28 6- 1 289, May 1 9 93 mentions the chopped delta-sigma modulator (delta-sigma modulator) ) Plus traditional operational amplifiers can have better immunity to low-frequency noise, but at the same time chopping also generates residual noise (residua 1 η oise) due to mismatch of charge injection between switches. The 0 N and 0 F F of the switch also pulses the input of the delta-sigma modulator. These high-frequency switching signals will reduce the SNDR and resolution of the system as the input signal enters the modulator. Another method is by A. Bakker, K. Thiele and JH Huijsing in '· Α CMOS nested-chopper instrumentation amplifier with 100-nV offset, " IEEE J. Solid-State Circuits, vol · 35 · 12, pp · 1877-1883, Dec. 2000 proposed in this article. It mentions that a nested-chopper amplifier will reduce residual noise. If it is used in a delta-sigma modulator, it will eliminate the OP AMP compensation value (〇 ff set) and related low-frequency noise. However, the front-end modulator is still affected by the high-frequency noise caused by the mismatch between the sampling switches. Another method is by CB Wang at ΠΑ 20 bit 25kHz delta-sigma A / D converter utilizing frequency-shaped chopper stabilization scheme, M IEEE custom integrated circuits conference, pp. 9-1, 2, 2 0 0 0 'Frequency Group Chopping Stable Delta Integral Analogy

0389-9168TWF (Nl); P910009TW; EDWARD.ptd Page 7 265 200425645 V. Description of the invention (3) Digital converter (frequency-shaped chopper stabilized delta-sigma A / D converter) can be used to remove clock pulse noise (clock spike noise). The chopper clock is generated from the input pseudo-random clock to a digital filter and a wave filter. There are two digital filters at the DC and half sampling frequency (ha 1 fsamp 1 ing frequency). zero. And the clock noise does not appear in the specified frequency band. Sampling from the input switch's automatic zeroing (aut ozering) method will return the frequency noise to the specified frequency band. Similarly, the advantages of chopping technology are The reason is that in the application of delta-sigma modulator, there is lower noise than the automatic zeroing method. ^ Therefore, in the future, we will need a circuit or method that can effectively reduce the noise generated when performing analog-to-digital conversion of an input signal. Summary of the Invention: In order to solve the above problems, the present invention proposes to use a nested chopper delta-sigma modulator (delta-sigma modulator) as a solution. The residual noise caused by the mismatch between the input terminals of the chopper switch (residual Noise) can be reduced using closed circuits. The present invention can be applied to many parties

Surface, such as a process, system, or device. Several specific applications will be revealed below. First we need a nested chopping circuit, which contains a first chopping section coupled to the input and controlled by a pair of non-overlapping clocks. One

200425645 V. Description of the invention (4) ^: The chopping part is coupled with the first chopping part, and the input of @first chopping part ^ f is connected to the input of the second and the wave part, where the second chopping part is opposite Controlled by clocks that are not heavy and are periodically inverted to each other. The clock consists of several chopper clocks. Nes, nested chopper circuit and delta-sigma ^ e ta — Sigma modulator circuit are consumed, and the phase-inverted clock in the basin is dying for the next time.> # # 周期 八 Τ cycle to The first chopping signal is eight μ, and the sampling is then referred to the Λ end of ΦΒ. The non-overlapping clock is made by ΦΑ and ΦΒ, and a pair of chopper clocks is this chopping. The clock controls the second chopper section. The switches S1 and S2 are divided into non-overlapping clocks J S3 and S4, and S_: ΦΑ · operates ^ with the following logic: Β · φ 1 1. 2 'S2 & S3: φA · φ12 + Φ The first chopper section has two switches and the two external chopper sections controlled by the second non-heavy non-heavy f-day clock are paired ^ The internal switches that are controlled, and the four switches controlled by the second non-overlapping clock and the second non-lingual clock Γ, ', in which the first invention provides: the clock is periodically inverted. method. When there is a signal at the input end, the clock that breaks the analog input signal for sampling will enter the first chopping section and the other pair of non-overlapping periodically inverted phases enter the second chopping section. Among them, the clock is composed of a chopped clock that is periodically inverted. The input signal is executed when the first overlapping clock is counted by an infinite number of choppers, and is used to make the above purpose of the present invention in the positive 2 waves σ 输入 of the input signal and the second chopper part. sampling. ,, features, and advantages can be more obvious and easier. $ 9, page 389-9168TWF (Nl); P910009TW; EDWARD.ptd 200425645 V. Description of the invention (5) 明 Ming: I would like to mention several preferred embodiments, 1 with the attached Illustrated for detailed implementation: Chopping, 'Pi Zhou ^ As shown in the picture: the nested chopper 100' has a non-overlapping by two by several B / and chopper 100 to r The switch A and the chopping 100 (as shown in Figs. 3 and 4) controlled by the clocks Φ A and _ are controlled by a clock. The nested chopper 100 includes a light-controlled ^ control ^ ^ ^ 1〇4 ^ Α and ΦΒ controlled, and the second chopper part 1 () 2_ combined in the first-chopper

Points 104. The output plate Q of the first chopper section 104 is connected to the input of the chopper section 102, and the second chopper section is controlled by the chopper. One of the pairs of non-overlapping clocks ΦA①θ / and ①12 is periodic and equal to each other = eight. And 0 疋 are shown in Figure 2A by several chopped clocks, while the other-chopping pulses are shown in Figure 2B. In the f-known technique, a f-shaped wave with a double frequency shift of the input signal will occur before the signal enters the converter and cannot be directly connected to the front end of the modulator. Objective: The nested chopper with chopper stabilization technology is exposed to be a delta-sigma modulator. First, the input signal is modulated by the previous chopping to the high-frequency noise-sending delta-sigma modulator (delta_s second pass m〇dulat〇r), and the following chopper circuit is used to demodulate this In order to overcome the residual noise caused by the previous chopping (Heart II ^ I used the nested chopping as shown in the figure!

26.8. 200425645 5. Description of the invention (6) (nested chopper delta-sigma modulator). The noisy spike generated by the chopping switch is reversed into a tunable period, so the average residual noise (average residuai n〇ise) is reduced or eliminated, making the modulator ’s SNR has improved. As shown in the timing chart in Fig. 2A, the forward and reverse signals are alternately input to the delta cycle converter. Therefore, when φ a is on, the control signals of s 1 and s 4 are φ 11 and the control signals of s 2 and s 3 are φ 12. Please refer to Figures 2C and 2D for the status of the switches. In order to maintain the operation of the chopper-stabilized modulator (c h pp er-s t a b i 1 ez d modulator), the clock of the nested chopper is changed according to the present invention. In 104 of Fig. 1, when? A is 0N, the function of the nested chopper 100 is the same as that of a single chopper circuit. As shown in Fig. 2C, in 102a, si and s4 are 0N when the phase angle is φΐ1; in 10213, S2 and S3 are 0N when the phase angle is Φ12. As shown in FIG. 2D, in 〇4b, ΦΒ is ON. In order to maintain the forward and reverse signals to be input to the modulator alternately, s2 and s3 in 1 〇2b are on when the phase angle is Φ11, and si and s4 in i〇2a are ON when the phase angle is Φ12. . Therefore, the control logic of si, s2, s3, and s4 is: «SI & S4: ΦΑ-Φ11 + ΦΒ-Φ12 S2 & S3: ΦΑ · Φ12 + ΦΒ · φ 11 chopper del ta-sigma modulator) can reduce residual noise (residuai no i se) and has lower low-frequency noise. Nested chopper delta-sigma modulator's structure and simple operation allow anyone skilled in the art to use it

0389-9168TWF (N1); P910009TW; EDWARD.p td Page 11 200425645 V. Description of the invention (7) On the CMOS integrated circuit. Figure 3 ^ shows a block diagram of a second-order differential nested chopping delta-sigma modulator with thermal noise and noise from different amplifiers. The thermal noise 11 shown in the figure is the thermal noise of the second Bo Zhenjie and the non-linear output of the amplifier and the noise of the amplifier. The nested chopper 100 is in the DSM (delta — sigma modulator). ) Before the first op amp. In Figure 4, the nested chopper 100 is moved to the output of the op amp, and the above switch can be simplified to a single NMOS switch due to the virtual ground input of the operational amplifier. However, the feedback edge contains chopper-like logic that can correct the positive and negative feedback.丨 Figure 5 shows the dB versus Hz plot of a chopping tip pulse with an input signal of -6dB, 578125kHz, a sampling frequency of 2.56MHz, and a maximum value of 0.5V. There are three examples in this figure. First, the top of the figure is one of the conventional techniques, a chopped stable DSM with residual noise. Secondly, the middle of the figure is a nested chopped DSM with residual noise of the present invention. Finally, the bottom of the figure is a perfect chopped stable dsm without residual noise. As shown, the residual noise in the second example is lower than that in the first example in the lower frequency band. Therefore, the present invention can effectively suppress undesired input synthesis δίΐ. Figure 6 is the SNDR vs. input amplitude graph, in which the peak of the nested chop 08 ^ 1 of the present invention, 301 ^, has a bandwidth of 69.9 at 22.051 ^ 2 (16 and 86 · 3dB at 8 1 ^ 2). 〇 The present invention is also applicable to various computer-related operations that require clever use of material quantities, such as data stored in a computer. Usually these quantities are obtained via

0389-9168TWF (Nl); P910009TW; EDWARD.ptd Page 12 200425645 V. Description of the invention (8) Electronic or electromagnetic signals can be stored, connected or converted as defined by the human chopper 10G: comparison, and nesting are often defined For making, sentence, 噔,. +, Ting Er's clever use is often, decided and compared. pp-ί f This creation has been disclosed in the preferred embodiment as above. Within the scope of this article, you can make a few changes within the scope of the non-field god and u; u do not depart from the essence of this creation, as defined by the scope of the patent application attached to Gutian Whichever comes first: Guaranteed

0389-9168TWF (N1); P910009TW; EDWARD.p t d p. 13 200425645

FIG. 1 shows a circuit diagram of a nested chopper delta-sigma modulator of the present invention. Figure 2 (A) shows the operation of a pair of non-overlapping clocks versus a chopped clock. Figure 2 (B) shows a pulse demodulated by another chopping. Figures 2 (C) and 2 (D) show the switches operating under a pair of non-overlapping clocks and chopper clocks. Figure 3 shows an example of a nested chopper delta-sigma modulator with thermal noise and the second derivative of the operational amplifier. Figure 4 shows another example of a nested chopper delta-sigma modulator with thermal noise and the second derivative of the operational amplifier. Figure 5 shows the dB vs. Hz plot of a chopping tip pulse with an input signal of -6 dB, 5.78125k Hz, a sampling frequency of 2.56MHz, and a maximum value of 0.5. Figure 6 shows the SNDR vs. input amplitude map. Explanation of symbols: Φ 1 1 ~ phase angle 1 1 Φ 1 2 ~ phase angle 12 Φ A ~ phase angle A Φ B ~ phase angle B S1 ~ switch 1 S2 ~ switch 2

0389-9168TWF (N1); P910009TW; EDWARD.ptd page 14 200425645 The diagram briefly explains S3 ~ switch 3 S4 ~ switch 4 Φ _ 0389-9168TWF (Nl); P910009TW; EDWARD.ptd page 15 111

Claims (1)

200425645 6. Scope of patent application 1. A nested chopping circuit, which includes: A first chopping section, which is coupled to the input terminal and is paired by a pair of first and second non- Controlled by an overlapping clock; and a second chopping section coupled to the first chopping section, wherein an output terminal of the first chopping section is connected to an input terminal of the second chopping section, and the second chopping section The wave part is controlled by a pair of first and second chopper clocks; wherein the first and second non-overlapping clocks are composed of the above several chopper clocks. The first and first non-overlapping clocks are periodic with each other. Of the inversion. 2. The nested chopper circuit (1 ^ 31: chopper circuit) according to item 1 of the scope of patent application, wherein the nested chopper circuit is coupled to a delta-sigma modulator (delta) — Sigma modulator) ° 3. The nested chopper circuit described in item 1 of the scope of the patent application, wherein the clocks that are periodically inverse to each other sample the positive and negative input machines and then This sampling is provided to the input of the first chop and pico-segment. 4 · The nested chopper circuit described in item 1 of the scope of the patent application, wherein the first and second non-heavy chopper circuits are composed of ΦΑ and ΦΒ. -"Li knife 5. The nested chopper circuit as described in item 4 of the scope of patent application", wherein the first and second chopper clocks are respectively 200425645 6. Scope of patent application Φ 11 and Φ 1 2 6 · The nested chopper circuit (Sited, Si, S2, S3, S4 of the nested part as described in the patent application scope chopper Circuit), 1 ^ The above mentioned chopper clock controls the second chopper chod: ei ^ ^ ° The nested chopper circuit described in the 6th item of the month 1 crime (nested when the first and second non-overlapping: soil fSl, 82, so, the switch is on and on. The operation will be based on the following logic: S1 & S4 · φΑ · Φ11 + φβ S2 & S3: ΦΑ · φΐ2 + φΒ · φ1ι. 8 · —Nested chopper circuit (-. Ted chopper circuit), including a first chopper circuit, In the ancient women's shirt, two parts of the t-wave are controlled by the first non-heavy input ... The first-chop is controlled by the second non-overlapping clock; the external switch with internal control and two and a second chopped part, Coupling the output of the above-mentioned chopping section in the second and second sections; describing the first-chopping section, its input end; 旳 Output 鸲 4 switches connected to the above-mentioned second chopping section. The phase of the controlled non-overlapping clock is the same as the inverse of the above-mentioned] and the above phase. The phase of the first non-overlapping clock is Inverse 9. The chopper circuit as described in item 8 of the scope of the patent application, wherein the nested chopper circuit (nested T nested chopper circuit (nested 0389-9168TW (Nl); P910009TW; EDWARD.ptd page 17 200425645) 6. The scope of patent application (chopper circuit) is connected to a delta-sigma modulator ° 1 〇 Nested chopper circuit as described in item 8 of the scope of patent application, where The clocks which are periodically inverted in phase with each other can provide the positive and negative input signals required for sampling to the above-mentioned input terminal of the first chopper division. 1 1. The nested chopper circuit described in item 8 of the scope of patent application ( nested chopper circuit), wherein the first and second non-overlapping clocks are respectively composed of φ A and Φ B. 1 2 · Nested chopper circuit as described in item 11 of the scope of patent application ), Where the first and second chopper clocks are composed of Φ 1 1 and φ 1 2 respectively. 1 3 · A nested chopper circuit as described in item 12 of the patent application scope, wherein Chopper clock control Said second chopper portion SI, S2, S3, S4 switch. 1 4 · The nested chopper circuit as described in item 13 of the scope of patent application, wherein the Si, S2, S3, and S4 switches operate at the same time as the first and second non-overlapping clocks. Will follow the following logic: ❿ S1 & S4: ΦΑ · Φ11 + ΦΒ · Φ 12; S2 & S3: ΦΑ · Φ12 + ΦΒ · Φ11. 1 5 · —A kind of analog input signal that can be cut for sampling includes: ,, method, "receive an input signal; 0389-9168TWF (Nl); P910009TW; EDWARD.ptd? 7κ 200425645 6. Scope of patent application When there is a signal at the input end, a pair of periodically opposing second non-overlapping clocks will enter the first chopping section; the first and other pairs of the first and second chopping clocks will enter The second chopping of the first and second non-overlapping clocks is composed of countless chopping: knife, into; τ ,, the above type 1 input signal will pass through the first chopping part and the second chopping part, and Its continuous periodic inversion characteristics can be sampled on the forward and reverse periods of the above analog input ^ 'number. 16. A method for chopping an analog input signal for sampling as described in item 15 of the scope of patent application, further comprising: coupling the output end of the second chopping part to a sigma inodulaior) ° 1 7 · As described in item 5 of the scope of patent application, a method can be used to cut off the analog input # for sampling, where the first and second non-overlapping clocks are composed of Φ A and φ B, respectively . 1 8 · A method for cutting analog input signals for sampling as described in item 7 of the scope of patent application, wherein the first and second chopping clocks are composed of Φ 1 1 and φ 1 2 respectively. 1 9 · A method for cutting analog input signals for sampling as described in item 18 of the scope of patent application, wherein the first and second chopping clocks control S1, S2, and S of the second chopping section. 3. S4 switch. 2 0. A method for cutting off an analog input signal for sampling as described in item 19 of the scope of the patent application, wherein the S1, S2, S3, and S4 switches are raised from the first and second non-overlapping clocks. It operates according to the following logic 0389-9168TW (Nl); P910009TW; EDWARD, ptd 200425645 6. Scope of Patent Application Series: Φ11 + ΦΒ · Φ12 Φ12 + ΦΒ · Φ 11 S1 & S4: ΦΑ S2 & S3: ΦΑ Βϋ 0389-9168TWF (N1); P910009TW; EDWARD.ptd page 20