CN204807622U - Detection circuitry - Google Patents
Detection circuitry Download PDFInfo
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- CN204807622U CN204807622U CN201520430376.6U CN201520430376U CN204807622U CN 204807622 U CN204807622 U CN 204807622U CN 201520430376 U CN201520430376 U CN 201520430376U CN 204807622 U CN204807622 U CN 204807622U
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Abstract
The utility model discloses a detection circuitry for detected voltage signal includes: voltage signal amplifier, drive circuit, over -sampling adc, digital filter. Drive circuit gains and the bandwidth modulation for the signal amplification that the voltage signal amplifier produced for over -sampling adc need not matchd to the bandwidth of voltage signal amplifier, and the voltage signal amplifier comes the filtering as the wave filter and inputs voltage signal's noise, need not reduce digital filter's bandwidth, has improved the SNR of system. Detection circuitry is still including setting up the chopper circuit before the voltage signal amplifier and setting up the 2nd chopper circuit between drive circuit and over -sampling adc. Through chopper circuit, the 1f noise modulated that produces voltage signal amplifier and drive circuit passes through the digital filter filtering to the high frequency, has improved the SNR of system.
Description
Technical field
The utility model relates to Analogical Circuit Technique field, is specifically related to a kind of testing circuit.
Background technology
Many advantages such as MEMS sensor is little, lightweight with its volume, resistance to mechanical is vibrated and temperature change capabilities is strong, electromagnetism interference superior performance are applied to many fields such as industry, acoustics, medical treatment, military affairs, petroleum detection more and more widely, special in moving communicating field, MEMS sensor has become the standard configuration of smart mobile phone.
Signal first amplifies with amplifier by the output signal testing circuit of existing MEMS sensor, then by analog to digital converter (AnalogtoDigitalConverter, ADC) carry out analog to digital conversion, finally with digital filter, filtering is carried out to the digital value that analog to digital converter exports.The output signal testing circuit of MEMS sensor mainly contains three kinds of frameworks: charge amplifier adds gradually-appoximant analog-digital converter and digital filter, voltage signal amplifier adds oversampling analog-to-digital converter and digital filter, and voltage signal amplifier adds gradually-appoximant analog-digital converter and digital filter.
In the testing circuit structure of prior art, because amplifier needs to drive analog to digital converter, so the bandwidth of amplifier can be restricted.Like this, the noise of amplifier and the noise of MEMS sensor output itself all carry out filtering by digital filter.Just must reduce the bandwidth of digital filter for reducing noise like this, be no matter the sample clock frequency of the sampling number or reduction ADC increasing ADC to reduce the bandwidth of digital filter, all can to increase the power consumption of front-end circuit for cost.Usually these circuit can reach the precision of 16bit, if continue to improve precision, cost can be larger, there is the contradiction between Optimal performance and power consumption.
Therefore expect that the testing circuit of the output signal of MEMS sensor can provide high signal to noise ratio (S/N ratio).
Utility model content
In view of this, the utility model proposes a kind of testing circuit, for detectable voltage signals, the faint output signal of such as MEMS sensor.
According to an aspect of the present utility model, the testing circuit that the utility model proposes comprises: voltage signal amplifier, for amplifying described voltage signal, to generate amplifying signal; Driving circuit, for adjusting gain, the bandwidth of described amplifying signal, to generate drive singal; Oversampling analog-to-digital converter, for sampling with first frequency to described drive singal, quantize under the control of the first clock signal, to generate digital signal; Digital filter, for carrying out filtering to described digital signal; Wherein, described amplifying signal does not comprise the noise in described voltage signal, and described drive singal mates with described oversampling analog-to-digital converter.
Preferably, described testing circuit also comprises: the first chopper circuit, before being arranged on described voltage signal amplifier, for carrying out copped wave to described voltage signal under the control of the second clock signal; Second chopper circuit, is arranged between described driving circuit and described oversampling analog-to-digital converter, for carrying out copped wave to described drive singal under the control of the second clock signal.
Preferably, described first frequency is greater than the twice of the frequency of described drive singal.
Preferably, described second clock signal comprises alternately and time equal first phase and second phase.
Preferably, input signal, when described second clock signal is first phase, directly exports by described first chopper circuit; Output signal, when described second clock signal is second phase, is set to same input inversion by described first chopper circuit; Input signal, when described second clock signal is first phase, directly exports by described second chopper circuit; Output signal, when described second clock signal is second phase, is set to same input signal anti-phase by described second chopper circuit.
Preferably, described oversampling analog-to-digital converter, under the control of the first clock signal, does not work in the Time Created after described first phase and second phase switch or abandons the digital signal of output.
Preferably, the cycle of described first clock signal is the half in the cycle of described second clock signal, cycle of described first clock signal comprises Time Created successively and working time, and the length of wherein said working time is the integral multiple in the sampling period of described oversampling analog-to-digital converter.
Preferably, the length of described working time is 2 of the sampling period of described oversampling analog-to-digital converter
ndoubly.
Preferably, described Time Created is determined according to the bandwidth of described voltage signal amplifier, and described Time Created is greater than the sampling period of described oversampling analog-to-digital converter, is less than the described working time.
Preferably, within described Time Created, described oversampling analog-to-digital converter disconnects with described digital filter; Within the described working time, described oversampling analog-to-digital converter connects with described digital filter.
The amplifying signal being the generation of voltage signal amplifier by driving circuit carries out gain and bandwidth modulation, the bandwidth of voltage signal amplifier is made not need to mate oversampling analog-to-digital converter, voltage signal amplifier is used as the noise that wave filter carrys out filtering MEMS sensor output signal, do not need the bandwidth reducing digital filter, improve the signal to noise ratio (S/N ratio) of system, improve circuit performance.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects, features and advantages of the present utility model will be more clear, in the accompanying drawings:
Fig. 1 is the structural drawing of the testing circuit according to the utility model first embodiment;
Fig. 2 is the structural drawing of the testing circuit according to the utility model second embodiment;
Fig. 3 is the input-output wave shape figure of the chopper circuit of testing circuit according to the utility model second embodiment;
Fig. 4 is the working timing figure of the testing circuit according to the utility model second embodiment.
Embodiment
Based on embodiment, the utility model is described below, but the utility model is not restricted to these embodiments.In hereafter details of the present utility model being described, detailedly describe some specific detail sections.Do not have the description of these detail sections can understand the utility model completely for a person skilled in the art yet.In order to avoid obscuring essence of the present utility model, known method, process, flow process, element and circuit do not describe in detail.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.Meanwhile, should be appreciated that in the following description, " circuit " refers to the galvanic circle connected and composed by electrical connection or electromagnetism by least one element or electronic circuit.When " being connected to " another element when claiming element or circuit or claiming element/circuit " to be connected to " between two nodes, it can be directly couple or be connected to another element or can there is intermediary element, the connection between element can be physically, in logic or its combine.On the contrary, " be directly coupled to " when claiming element or " being directly connected to " another element time, mean that both do not exist intermediary element.Unless the context clearly requires otherwise, similar words such as " comprising ", " comprising " otherwise in whole instructions and claims should be interpreted as the implication that comprises instead of exclusive or exhaustive implication; That is, be the implication of " including but not limited to ".
The output signal of MEMS sensor is very faint, usually only have several millivolts, have or even microvolt level, but also with noise; Signal quality is now non-constant, and signal to noise ratio (S/N ratio) is very low.The task of testing circuit is amplified the output signal of MEMS sensor, filtering, carries out analog to digital conversion again, obtains the output signal of high s/n ratio finally by digital filter.
Fig. 1 is the structural drawing of the testing circuit according to the utility model first embodiment, and testing circuit 100 comprises: voltage signal amplifier 101, driving circuit 102, oversampling analog-to-digital converter 103 and digital filter 104.Testing circuit 100 is for detecting the output signal of MEMS sensor 300.
Voltage signal amplifier 101 to be arranged between MEMS sensor 300 and driving circuit 102.Voltage signal amplifier 101 amplifies the faint output signal that MEMS sensor produces, to produce amplifying signal.Voltage signal amplifier, also known as continuous amplifier, is the amplifier based on operational amplifier, for amplification voltage signal.Meanwhile, voltage signal amplifier 101, can noise in the output signal of filtering MEMS sensor by the bandwidth of adjustment voltage signal amplifier 101 also as wave filter, improves signal to noise ratio (S/N ratio).
Driving circuit 102 is arranged between voltage signal amplifier 101 and oversampling analog-to-digital converter 103, driving circuit 102 for adjusting the gain, bandwidth etc. of amplifying signal, to produce the drive singal mated with oversampling analog-to-digital converter 103.
Oversampling analog-to-digital converter 103 is arranged between driving circuit 102 and digital filter 104, and for the simulating signal of input is converted to digital signal, such as, oversampling analog-to-digital converter 103 is Sigma-delta ADC's.The sample frequency of oversampling analog-to-digital converter 103, higher than nyquist sampling rate, can reduce quantizing noise, improves precision, makes the upper limiting frequency of its output digit signals can carry out digital processing to the region of 1/2 sample frequency simultaneously.
Digital filter 104 carries out filtering for the digital signal exported oversampling analog-to-digital converter 103.Digital filter 104 has easy adjustment, feature that precision is high, can eliminate nearly all oversampling analog-to-digital converter 103 out-of-band noise.
Usual analog to digital converter has high input impedance and larger and variable capacitive reactance, and Simultaneous Switching electric capacity or sampling hold circuit meeting generation current spike, driving circuit 102 can eliminate current spike provides Low ESR anti-source simultaneously.The sample frequency of oversampling analog-to-digital converter 103 is higher than nyquist sampling rate, the simulating signal be sampled needs the bandwidth of coupling, at 1/2 place of sample frequency, the circuit of previous stage needs and oversampling analog-to-digital converter 103 has close distortion and noisiness.
Voltage signal amplifier 101 is in order to the noise in the output signal of filtering MEMS sensor, need suitable bandwidth, therefore the amplifying signal that voltage signal amplifier 101 exports does not mate with oversampling analog-to-digital converter 103, the drive singal that driving circuit 102 is mated with oversampling analog-to-digital converter 103 with generation by the gain of adjustment amplifying signal, bandwidth.Driving circuit 102 makes the bandwidth of amplifying circuit 101 no longer restrict by oversampling analog-to-digital converter 103, can carry out filtering better to the output signal of MEMS sensor.
The testing circuit 100 of the utility model first embodiment just can improve the quality of output signal when not reducing digital filter 104 bandwidth.In the testing circuit 100 of the first embodiment, the noise of MEMS sensor output signal is by voltage signal amplifier 101 filtering, and the noise that voltage signal amplifier 101 produces is by digital filter 104 filtering.When the noise of MEMS sensor output signal is overriding noise source, the testing circuit 100 of the first embodiment effectively can improve the signal to noise ratio (S/N ratio) of system.
The testing circuit 100 of the utility model first embodiment can make on the same substrate with MEMS sensor 300, also can be packaged together with the MEMS sensor 300 that sheet is independent outward.
Fig. 2 is the structural drawing of the testing circuit according to the utility model second embodiment, and testing circuit 200 comprises: voltage signal amplifier 201, driving circuit 202, oversampling analog-to-digital converter 203, digital filter 204, chopper circuit 205 and chopper circuit 206.Testing circuit 200 is for detecting the output signal of MEMS sensor 300.
Chopper circuit 205 is arranged between MEMS sensor 300 and voltage signal amplifier 201.Chopper circuit 205 carries out copped wave to the output signal of MEMS sensor 300 under the control of clock signal Cp.The output signal of usual MEMS sensor 300 is low frequency signal, and the frequency of the output signal of MEMS sensor 300 is denoted as f
0.The output signal of MEMS sensor 300 is modulated to frequency f by chopper circuit 205
1, wherein f
1>>f
0.
Voltage signal amplifier 201 to be arranged between chopper circuit 205 and driving circuit 202.Voltage signal amplifier 201 amplifies the output signal of the MEMS sensor 300 after copped wave, to produce amplifying signal.Voltage signal amplifier, also known as continuous amplifier, is the amplifier based on operational amplifier, for amplification voltage signal.Meanwhile, voltage signal amplifier 201, can noise in the output signal of filtering MEMS sensor 300 by the bandwidth of adjustment voltage signal amplifier 201 also as wave filter, improves signal to noise ratio (S/N ratio).
Driving circuit 202 is arranged between voltage signal amplifier 201 and chopper circuit 206, driving circuit 202 for adjusting the gain, bandwidth etc. of amplifying signal, to produce the drive singal mated with oversampling analog-to-digital converter 203.
Chopper circuit 206 is arranged between driving circuit 202 and oversampling analog-to-digital converter 203.Chopper circuit 206 carries out copped wave to drive singal under the control of clock signal Cp.Chopper circuit 206 by drive singal from frequency f
1modulate back frequency f
0, and the noise that voltage signal amplifier 201 and driving circuit 202 produce is modulated onto frequency f
1.
Oversampling analog-to-digital converter 203 is arranged between chopper circuit 206 and digital filter 204, oversampling analog-to-digital converter 203 is sampled to drive singal, is quantized under the control of clock signal ADC_CLK, drive singal is converted to digital signal, such as, oversampling analog-to-digital converter 203 is Sigma-delta ADC's.The sample frequency of oversampling analog-to-digital converter 203, higher than nyquist sampling rate, makes the upper limiting frequency of its output digit signals can carry out digital processing to the region of 1/2 sample frequency.
Digital filter 204 carries out filtering for the digital signal exported oversampling analog-to-digital converter 203.Digital filter 204 has easy adjustment, feature that precision is high, can eliminate nearly all oversampling analog-to-digital converter 203 out-of-band noise.
Fig. 3 shows the input-output wave shape figure of the chopper circuit of the testing circuit of the utility model second embodiment.Chopper circuit 205 and chopper circuit 206 copped wave under the control of clock signal C P, the cycle of clock signal C P is Tcp=1/f
1.Clock signal C P comprises first phase alternately and second phase, and the time of first phase and second phase is respectively Tcp/2.
Chopper circuit 205 is when clock signal C P is first phase, and the output Vout of chopper circuit 205 is identical with the input Vin of chopper circuit 205; Chopper circuit 205 is when clock signal C P is second phase, and the output Vout of chopper circuit 205 is anti-phase with the input Vin of chopper circuit 205.The input Vin of such as chopper circuit 205 remains V1 always, and the output Vout of chopper circuit 205 is V1 when clock signal C P is first phase, is-V1 when clock signal C P is second phase.
Chopper circuit 206 is when clock signal C P is first phase, and the output Vout of chopper circuit 206 is identical with the input Vin of chopper circuit 206; Chopper circuit 206 is when clock signal C P is second phase, and the output Vout of chopper circuit 206 is anti-phase with the input Vin of chopper circuit 206.The input Vin of such as chopper circuit 206 remains V1 always, and the output Vout of chopper circuit 206 is V1 when clock signal C P is first phase, is-V1 when clock signal C P is second phase.
Fig. 4 illustrates the working timing figure of the testing circuit 200 of the utility model second embodiment.The one-period of the clock signal ADC_CLK of oversampling analog-to-digital converter 203 is Tcp/2.The one-period of clock signal ADC_CLK comprises Ts and working time Tc Time Created, wherein working time Tc=A*T, T is the sampling period of oversampling analog-to-digital converter 203, and namely oversampling analog-to-digital converter 203 completes the time of once sampling, quantizing, A be greater than 0 integer.In a preferred embodiment, A=2
n.When clock signal CP switches between the first phase and the second phase, then clock signal ADC_CLK is initially located in Time Created Ts is working time Tc.Time Created, Ts was less than working time Tc, and be greater than the sampling period T of oversampling analog-to-digital converter 203, Time Created, Ts was determined by the bandwidth of voltage signal amplifier 201, and at Ts Time Created, oversampling analog-to-digital converter 203 does not work or abandons the digital signal of output.
In a preferred embodiment, between oversampling analog-to-digital converter 203 and digital filter 204, be also provided with the first switch, the first switch disconnects when clock signal ADC_CLK is in Ts Time Created, closed when clock signal ADC_CLK is in working time Tc.
The noise that the noise that the noise of the output signal of MEMS sensor 300, voltage signal amplifier 201 produce, driving circuit 202 produce is mainly thermonoise and 1/f noise.Thermonoise is white noise, and thermonoise is in higher frequency can by voltage signal amplifier 201 and digital filter 204 filtering.1/f noise mainly concentrates on low frequency, because the voltage signal amplifier 201 in testing circuit 200 and digital filter 204 are low-pass filtering, is difficult to filtering 1/f noise.The output signal of MEMS sensor 300 is modulated to high frequency f by chopper circuit 205
1, drive singal is modulated back frequency f by chopper circuit 206
0.The drive singal entering oversampling analog-to-digital converter 203 remains on original frequency f
0, and the 1/f noise that voltage signal amplifier 201 and driving circuit 202 produce is modulated to high frequency f by chopper circuit 206
1, like this when through digital filter 204, the 1/f noise that voltage signal amplifier 201 and driving circuit 202 produce just can by filtering.
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, to those skilled in the art, the utility model can have various change and change.All do within spirit of the present utility model and principle any amendment, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (10)
1. a testing circuit, for detectable voltage signals, is characterized in that, described testing circuit comprises:
Voltage signal amplifier, for amplifying described voltage signal, to generate amplifying signal;
Driving circuit, for adjusting gain, the bandwidth of described amplifying signal, to generate drive singal;
Oversampling analog-to-digital converter, for sampling with first frequency to described drive singal, quantize under the control of the first clock signal, to generate digital signal;
Digital filter, for carrying out filtering to described digital signal;
Wherein, described amplifying signal does not comprise the noise in described voltage signal, and described drive singal mates with described oversampling analog-to-digital converter.
2. testing circuit according to claim 1, is characterized in that, described testing circuit also comprises:
First chopper circuit, before being arranged on described voltage signal amplifier, for carrying out copped wave to described voltage signal under the control of the second clock signal;
Second chopper circuit, is arranged between described driving circuit and described oversampling analog-to-digital converter, for carrying out copped wave to described drive singal under the control of the second clock signal.
3. testing circuit according to claim 1 and 2, is characterized in that, described first frequency is greater than the twice of the frequency of described drive singal.
4. testing circuit according to claim 2, is characterized in that, described second clock signal comprises alternately and time equal first phase and second phase.
5. testing circuit according to claim 4, is characterized in that, input signal, when described second clock signal is first phase, directly exports by described first chopper circuit; Output signal, when described second clock signal is second phase, is set to same input inversion by described first chopper circuit;
Input signal, when described second clock signal is first phase, directly exports by described second chopper circuit; Output signal, when described second clock signal is second phase, is set to same input signal anti-phase by described second chopper circuit.
6. testing circuit according to claim 4, is characterized in that, described oversampling analog-to-digital converter, under the control of the first clock signal, does not work in the Time Created after described first phase and second phase switch or abandons the digital signal of output.
7. testing circuit according to claim 6, it is characterized in that, the cycle of described first clock signal is the half in the cycle of described second clock signal, cycle of described first clock signal comprises Time Created successively and working time, and the length of wherein said working time is the integral multiple in the sampling period of described oversampling analog-to-digital converter.
8. testing circuit according to claim 7, is characterized in that, the length of described working time is 2 of the sampling period of described oversampling analog-to-digital converter
ndoubly.
9. testing circuit according to claim 7, is characterized in that, described Time Created is determined according to the bandwidth of described voltage signal amplifier, and described Time Created is greater than the sampling period of described oversampling analog-to-digital converter, is less than the described working time.
10. testing circuit according to claim 7, is characterized in that, within described Time Created, described oversampling analog-to-digital converter disconnects with described digital filter; Within the described working time, described oversampling analog-to-digital converter connects with described digital filter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520430376.6U CN204807622U (en) | 2015-06-19 | 2015-06-19 | Detection circuitry |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520430376.6U CN204807622U (en) | 2015-06-19 | 2015-06-19 | Detection circuitry |
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| Publication Number | Publication Date |
|---|---|
| CN204807622U true CN204807622U (en) | 2015-11-25 |
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ID=54592426
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104950165A (en) * | 2015-06-19 | 2015-09-30 | 杭州士兰微电子股份有限公司 | Detecting circuit and detecting method |
| CN107949104A (en) * | 2017-11-20 | 2018-04-20 | 常州工学院 | A kind of LED detection circuits and drive circuit and lighting system |
| CN109586718A (en) * | 2018-11-06 | 2019-04-05 | 同方威视技术股份有限公司 | Reduce circuit, noise-reduction method and the equipment of A/D converter noise |
-
2015
- 2015-06-19 CN CN201520430376.6U patent/CN204807622U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104950165A (en) * | 2015-06-19 | 2015-09-30 | 杭州士兰微电子股份有限公司 | Detecting circuit and detecting method |
| CN107949104A (en) * | 2017-11-20 | 2018-04-20 | 常州工学院 | A kind of LED detection circuits and drive circuit and lighting system |
| CN109586718A (en) * | 2018-11-06 | 2019-04-05 | 同方威视技术股份有限公司 | Reduce circuit, noise-reduction method and the equipment of A/D converter noise |
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