CN101394163B - Signal conditioning circuit and dual sampling-hold circuit - Google Patents
Signal conditioning circuit and dual sampling-hold circuit Download PDFInfo
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- CN101394163B CN101394163B CN2008102009700A CN200810200970A CN101394163B CN 101394163 B CN101394163 B CN 101394163B CN 2008102009700 A CN2008102009700 A CN 2008102009700A CN 200810200970 A CN200810200970 A CN 200810200970A CN 101394163 B CN101394163 B CN 101394163B
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Abstract
The invention discloses a signal conditioning circuit and a double sampling retaining circuit. The signal conditioning circuit comprises a first chopping switch, a programmable gain amplifier, a second chopping switch, a double sampling retaining circuit, an analog-to-digital converter, and a digital reduction sampling filter which are connected in sequence. The double sampling retaining circuit samples outputs of the programmable gain amplifier in two-phase positions of a chopping clock, and the results of two samplings are added. and an added output voltage istransmitted to and processed by the analog-to-digital converter, and the digital reduction sampling filter. Since the double sampling retaining circuit is added, the invention avoids the residual andoff-tune problem in a chopping amplifier. Meanwhile, the invention facilitates the integration of a single chip, without the need of external filtering capacitor. Furthermore, a novel sequential control reduces the consumption of a digital signal conditioning circuit based on a chopping amplifier.
Description
Technical field
The invention belongs to the signal processing technology field, relate to a kind of signal conditioning circuit and Opsonizing method thereof, relate in particular to a kind of digital signal modulate circuit and Opsonizing method thereof based on two sampling structure chopper amplifiers; In addition, the invention still further relates to a kind of dual-sampling hold circuit.
Background technology
Chopper amplifier is widely used in the Signal Measurement System owing to its superior low imbalance characteristic.Fig. 1 is the structural representation of a typical chopper amplifier.Input signal is modulated to Chop frequency Fchop place through Chop switch SW 1, and offset voltage and modulated input signal are modulated by the Chop switch after amplifying once more, and modulated time direct current place of input signal offset voltage then is modulated onto the Fchop place like this.Filter and just can obtain behind the offset voltage at Fchop place through the input signal after amplifying.Because about tens KHz, LPF (low pass filter) needs bigger resistance capacitance not easy of integration to Fchop usually.
U.S. Pat 2005/6891430B1 improves common chopper amplifier, it has described a signal conditioning circuit based on chopper amplifier, mainly comprises chopper amplifier (PGA), sigma-delta modulator, the digital filtering (seeing also Fig. 2) of Gain Adjustable.Need the electric capacity filtering of an external 22nF to be modulated to the offset voltage at chopping frequency place in PGA output place.The voltage method for building up that this signal conditioning circuit has proposed the speed combination simultaneously removes to drive sigma-delta modulator, though saved the part power consumption, because the gain of PGA is bigger, so direct driving sample circuit power consumption is still bigger.
In addition, at " Anton Bakker, A CMOS Nested-Chopper Instrumentaion Amplifier with 100-nVOffset, ISSCC2000, VOL35, NO12, Page 1877. " in the document, proposed to reduce residual imbalance with the method for nested shift frequency, it utilizes a lower frequency that filtering is then modulated in residual in the same way spike, can reduce the residual imbalance that high-frequency copped wave produces like this but can't eliminate the residual imbalance (seeing also Fig. 3) that low frequency copped wave self produces.Owing to will make that residual imbalance is littler, its low frequency chopping frequency has only tens Hz usually simultaneously, has therefore limited application, and needs bigger filter capacitor.
See also Fig. 4 (a)-(c), when above circuit is realized, cmos switch can produce opposite spike when turn-offing and opening, shown in Fig. 4 (a), then direction is identical after modulated, after LPF filtering, then produce a direct current output, be referred to as residual imbalance (Residue Offset) usually, shown in Fig. 4 (c).The common amplitude of this residual offset voltage all need usually this special consideration for high-precision measuring system, and existing technology is difficult to address this problem at the microvolt order of magnitude.
Summary of the invention
Technical problem to be solved by this invention is: provide a kind of digital signal modulate circuit based on two sampling structure chopper amplifiers, to avoid the problem of residual imbalance in the chopper amplifier.
Simultaneously, the invention provides the Opsonizing method of above-mentioned signal conditioning circuit.
In addition, the present invention also provides the dual-sampling hold circuit in the above-mentioned signal conditioning circuit.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of signal conditioning circuit is characterized in that: comprise first chopping switch, chopper amplifier, second chopping switch, dual-sampling hold circuit, analog to digital converter, the digital desampling fir filter that connect successively; Described dual-sampling hold circuit is sampled to the output of described chopper amplifier in two phase places of copped wave clock, with the double sampling results added; And the output voltage after the addition is transferred to described analog to digital converter and digital desampling fir filter handle.
As a preferred embodiment of the present invention, the double sampling of described dual-sampling hold circuit is the input voltage of process chopper amplifier amplification and the offset voltage of chopper amplifier itself.
As a preferred embodiment of the present invention, after the described double sampling results added, input voltage signal doubles, and offset voltage is cancelled out each other mutually on the contrary in the direction of two phase places.
As a preferred embodiment of the present invention, the output voltage of described dual-sampling hold circuit is repeatedly sampled in a chopping cycle to realize digital translation by described analog to digital converter.
As a preferred embodiment of the present invention, described chopper amplifier is by the copped wave clock and the inversion clock control thereof of first chopping switch, second chopping switch.
As a preferred embodiment of the present invention, described dual-sampling hold circuit comprises some capacitors, switching network, reaches amplifier; The described second chopping switch output comprises first port, second port, and first port connects first capacitor and second capacitor in parallel, then with minion pass, the 5th capacitors in series; Second port connects the 3rd capacitor and the 4th capacitor in parallel, then with octavo pass, the 6th capacitors in series; First switch, second switch, the 3rd switch, the 4th switch are set respectively between the two-port and first capacitor, second capacitor, the 3rd capacitor and the 4th capacitor; Between first capacitor, the 3rd capacitor the 5th switch is set, between second capacitor, the 4th capacitor the 6th switch is set; Described dual-sampling hold circuit is respectively at first switch, when the 3rd switch is high level, carry out double sampling when perhaps second switch, the 4th switch are high; And the 5th switch, the 6th switch, minion close and octavo when closing to high level to double sampling results added before described.
As a preferred embodiment of the present invention, described the 5th switch, the 6th switch, minion are closed and octavo is closed the frequency setting of the duty ratio of high level by oversampling analog-to-digital converter.
As a preferred embodiment of the present invention, described the 5th switch, the 6th switch, minion are closed and the duty ratio of octavo pass high level is below 10%.
The signal condition method of above-mentioned signal conditioning circuit, this method comprises the steps:
Step 1, the output of described chopper amplifier is sampled in two phase places of copped wave clock;
Step 2, with the double sampling results added;
Step 3, the output voltage filter process after the addition.
Described step is specially:
Step 1, described dual-sampling hold circuit are sampled to the output of described chopper amplifier in two phase places of copped wave clock;
Step 2, with the double sampling results added;
Step 3, the output voltage after the addition is transferred to described analog to digital converter and digital desampling fir filter handle.
A kind of dual-sampling hold circuit, it comprises some capacitors, switching network, reaches amplifier; After first capacitor and the second capacitor parallel connection, with the port that minion is closed, the 5th capacitors in series inserts described amplifier; After the 3rd capacitor and the 4th capacitor parallel connection, with the another port that octavo is closed, the 6th capacitors in series inserts described amplifier; First capacitor, second capacitor, the 3rd capacitor and the 4th capacitor are connected with first switch, second switch, the 3rd switch, the 4th switch respectively; Between first capacitor, the 3rd capacitor the 5th switch is set, between second capacitor, the 4th capacitor the 6th switch is set; Described dual-sampling hold circuit is respectively at first switch, when the 3rd switch is high level, carry out double sampling when perhaps second switch, the 4th switch are high; And the 5th switch, the 6th switch, minion close and octavo when closing to high level to double sampling results added before described.
As a preferred embodiment of the present invention, described the 5th switch, the 6th switch, minion are closed and octavo is closed the frequency setting of the duty ratio of high level by oversampling analog-to-digital converter; Described the 5th switch, the 6th switch, minion are closed and the duty ratio of octavo pass high level is below 10%.
Beneficial effect of the present invention is:
1, the present invention has avoided the problem of residual imbalance in the chopper amplifier;
2, need not external filter capacitor, it is integrated to be more conducive to single-chip;
3, new sequencing control reduces the power consumption based on the digital signal modulate circuit of chopper amplifier.
Description of drawings
Fig. 1 is the structural representation of existing chopper amplifier.
Fig. 2 is the structural representation of U.S. Pat 2005/6891430 based on the signal conditioning circuit of chopper amplifier.
Fig. 3 is the structural representation of the chopper amplifier of nested shift frequency in the document.
Fig. 4 is the production process schematic diagram of residual offset voltage.
Fig. 5 is the structural representation of signal conditioning circuit of the present invention.
Fig. 6 is the structural representation of chopper amplifier and dual-sampling hold circuit.
Fig. 7 (a)-(d) is the signal schematic representation of input voltage and offset voltage.
Fig. 8 is two sampling time sequence figure.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment one
The present invention is directed to the sampling hold period dual-sampling hold circuit that adopts the asymmetric duty ratio of innovation based on the digital signal modulate circuit of chopper amplifier.
See also Fig. 5, the invention provides a kind of signal conditioning circuit, comprise the first chopping switch SW1, the chopper amplifier PGA (being programmable gain amplifier in the present embodiment), the second chopping switch SW2, dual-sampling hold circuit CDS, analog to digital converter ADC, the digital desampling fir filter DEC that connect successively based on two sampling structure chopper amplifiers; Described dual-sampling hold circuit is sampled (comprising input voltage and offset voltage) to the output of described chopper amplifier in two phase places of copped wave clock, with the double sampling results added; And the output voltage after the addition is transferred to described analog to digital converter and digital desampling fir filter handle.
As shown in Figure 6, chopper amplifier is by copped wave clock CK_CHOP and its inversion clock CKN_CHOP control, sampling hold circuit then carries out double sampling respectively when CK1D and CK2D are high, to preceding twice sampled result addition, and remain on the output of amplifier A2 when CK_HD is high.Offset voltage is eliminated by summation in this output, so need not to carry out filtering.Output voltage can repeatedly be sampled in a chopping cycle to realize digital translation by sigma-delta modulator simultaneously.The duty ratio of described 4 CK_HD switch high level is by the frequency setting of oversampling analog-to-digital converter; The duty ratio of 4 CK_HD high level is less than 50%, usually at (as 8%, 5%, 3%) below 10%.Because the gain of sampling hold circuit is lower, than the easier foundation of the chopper amplifier of high-gain, so for the modulator that drives same sample frequency, the power consumption of this kind structure is lower.Fig. 8 is two sampling time sequence figure.
Two phase places at the copped wave clock are all sampled to the output of chopper amplifier, and with twice sampled result addition.The result of Chu Liing is that input signal doubles like this, and the imbalance of amplifier is owing to then cancelling out each other on the contrary at two phase directionals, as shown in Figure 7.Fig. 7 (a) is input voltage and the offset voltage schematic diagram behind first chopping switch; Fig. 7 (b) is the input voltage and the offset voltage schematic diagram of second correspondence behind the chopping switch; Corresponding input voltage and the offset voltage schematic diagram of Fig. 7 (c) sampling hold circuit output; Fig. 7 (d) is a copped wave clock schematic diagram.
Analog to digital converter quantizes the summation output of dual-sampling hold circuit, just the input voltage after amplifying is quantized; Be to have set up the input signal of finishing owing to what quantize simultaneously, this has also just been avoided the generation of remaining imbalance.
The present invention provides the signal condition method of above-mentioned signal conditioning circuit simultaneously, and this method comprises the steps:
Step 1, described dual-sampling hold circuit are sampled to the output of described chopper amplifier in two phase places of copped wave clock; As shown in Figure 6, chopper amplifier is by copped wave clock CK_CHOP and its inversion clock CKN_CHOP control, and sampling hold circuit then carries out double sampling respectively when CK1D and CK2D are high.
Step 2, with the double sampling results added; As shown in Figure 6, when CK_HD is high to preceding twice sampled result addition.
Step 3, the output voltage after the addition is transferred to described analog to digital converter and digital desampling fir filter handle.
The present invention has avoided the problem of residual imbalance in the chopper amplifier by increasing dual-sampling hold circuit; Simultaneously, need not external filter capacitor, it is integrated to be more conducive to single-chip; New sequencing control reduces the power consumption based on the digital signal modulate circuit of chopper amplifier.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change are possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to disclosed embodiment.
Claims (9)
1. a signal conditioning circuit is characterized in that: comprise first chopping switch, chopper amplifier, second chopping switch, dual-sampling hold circuit, analog to digital converter, the digital desampling fir filter that connect successively;
Described dual-sampling hold circuit is sampled to the output of described chopper amplifier in two phase places of copped wave clock, with the double sampling results added; And the output voltage after the addition is transferred to described analog to digital converter and digital desampling fir filter handle;
Described dual-sampling hold circuit comprises some capacitors, switching network, reaches amplifier;
The described second chopping switch output comprises first port, second port, and first port connects first capacitor and second capacitor in parallel, then with minion pass, the 5th capacitors in series; Second port connects the 3rd capacitor and the 4th capacitor in parallel, then with octavo pass, the 6th capacitors in series;
First switch, second switch, the 3rd switch, the 4th switch are set respectively between the two-port and first capacitor, second capacitor, the 3rd capacitor and the 4th capacitor;
Between first capacitor, the 3rd capacitor the 5th switch is set, between second capacitor, the 4th capacitor the 6th switch is set;
Described dual-sampling hold circuit is respectively at first switch, when the 3rd switch is high level, carry out double sampling when perhaps second switch, the 4th switch are high; And the 5th switch, the 6th switch, minion close and octavo when closing to high level to double sampling results added before described.
2. signal conditioning circuit according to claim 1 is characterized in that: the double sampling of described dual-sampling hold circuit is the input voltage of process chopper amplifier amplification and the offset voltage of chopper amplifier itself.
3. signal conditioning circuit according to claim 2 is characterized in that: after the described double sampling results added, input voltage signal doubles, and offset voltage is cancelled out each other mutually on the contrary in the direction of two phase places.
4. signal conditioning circuit according to claim 1 is characterized in that: the output voltage of described dual-sampling hold circuit is repeatedly sampled in a chopping cycle to realize digital translation by described analog to digital converter.
5. signal conditioning circuit according to claim 1 is characterized in that: described chopper amplifier is by the copped wave clock and the inversion clock control thereof of first chopping switch, second chopping switch.
6. signal conditioning circuit according to claim 1 is characterized in that: described the 5th switch, the 6th switch, minion are closed and octavo is closed the frequency setting of the duty ratio of high level by oversampling analog-to-digital converter.
7. signal conditioning circuit according to claim 6 is characterized in that: described the 5th switch, the 6th switch, minion are closed and the duty ratio of octavo pass high level is below 10%.
8. dual-sampling hold circuit is characterized in that: it comprises some capacitors, switching network, and amplifier;
After first capacitor and the second capacitor parallel connection, with the port that minion is closed, the 5th capacitors in series inserts described amplifier; After the 3rd capacitor and the 4th capacitor parallel connection, with the another port that octavo is closed, the 6th capacitors in series inserts described amplifier;
First capacitor, second capacitor, the 3rd capacitor and the 4th capacitor are connected with first switch, second switch, the 3rd switch, the 4th switch respectively;
Between first capacitor, the 3rd capacitor the 5th switch is set, between second capacitor, the 4th capacitor the 6th switch is set;
Described dual-sampling hold circuit is respectively at first switch, when the 3rd switch is high level, carry out double sampling when perhaps second switch, the 4th switch are high; And the 5th switch, the 6th switch, minion close and octavo when closing to high level to double sampling results added before described.
9. dual-sampling hold circuit according to claim 8 is characterized in that: described the 5th switch, the 6th switch, minion are closed and octavo is closed the frequency setting of the duty ratio of high level by oversampling analog-to-digital converter; Described the 5th switch, the 6th switch, minion are closed and the duty ratio of octavo pass high level is below 10%.
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| CN2008102009700A CN101394163B (en) | 2008-10-09 | 2008-10-09 | Signal conditioning circuit and dual sampling-hold circuit |
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| CN101394163B true CN101394163B (en) | 2011-06-15 |
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