CN110798221B - Signal modulation circuit - Google Patents
Signal modulation circuit Download PDFInfo
- Publication number
- CN110798221B CN110798221B CN201911167272.XA CN201911167272A CN110798221B CN 110798221 B CN110798221 B CN 110798221B CN 201911167272 A CN201911167272 A CN 201911167272A CN 110798221 B CN110798221 B CN 110798221B
- Authority
- CN
- China
- Prior art keywords
- unit
- ota
- switch
- fully differential
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
Abstract
The invention discloses a signal modulation circuit, which comprises: a pre-amplifying unit for amplifying the extracted input signal; the second-stage fully differential OTA unit comprises a first-stage fully differential OTA unit and a second-stage fully differential OTA unit and is used for processing the input signal and outputting an analog signal; the quantization comparison unit is used for performing quantization comparison on the analog signals output by the two-stage fully differential OTA unit; the feedback compensation unit is used for compensating the secondary fully differential OTA unit according to the comparison result output by the quantization comparison unit; and the time sequence control unit is used for carrying out time sequence control on the pre-amplification unit, the two-stage fully differential OTA unit, the quantization comparison unit and the feedback compensation unit. The invention can be suitable for effective extraction and quantitative transfer of small signals, and the design of the two-stage OTA can realize smaller harmonic distortion and better linear stability, and has better anti-interference performance and induction sensitivity.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a signal modulation circuit.
Background
With the development of the scientific and technological era, in the field of integrated circuit application, modern people are more and more pursuing the performance stability and reliability of chips. Among them, the research on infrared detection technology was the technology developed for scientific research and military use at the earliest, but with the development of semiconductor technology and new materials, the production cost is continuously reduced, and various inexpensive infrared sensors are coming out in succession.
The pyroelectric infrared sensor is widely applied to various automatic control devices at present, and meanwhile, according to unique characteristics of the pyroelectric infrared sensor, a more excellent product or an automatic control device is developed by combining other circuits. The traditional mode is mostly processed the pyroelectric infrared sensor signal and is enlargied and draw in analog operational amplifier and RC filter circuit, and its own circuit structure has decided that the chip often can not have fine processing in the aspect of filtering, anti-jamming, response sensitivity.
Therefore, in view of the above technical problems, it is necessary to provide a signal modulation circuit.
Disclosure of Invention
The invention aims to provide a signal modulation circuit, which is designed based on the structural idea of Sigma-Delta (Sigma-Delta), can modulate and convert an electric signal converted by a pyroelectric infrared sensor when the pyroelectric infrared sensor detects human body activity into a digital signal, and can be directly used for a digital unit to process.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a signal modulation circuit, the signal modulation circuit comprising:
a pre-amplifying unit for amplifying the extracted input signal;
the second-stage fully differential OTA unit comprises a first-stage fully differential OTA unit and a second-stage fully differential OTA unit and is used for processing the input signal and outputting an analog signal;
the quantization comparison unit is used for performing quantization comparison on the analog signals output by the two-stage fully differential OTA unit;
the feedback compensation unit is used for compensating the secondary fully differential OTA unit according to the comparison result output by the quantization comparison unit;
and the time sequence control unit is used for carrying out time sequence control on the pre-amplification unit, the two-stage fully differential OTA unit, the quantization comparison unit and the feedback compensation unit.
In one embodiment, the pre-amplifying unit is connected to the first signal input terminal Si-and the second signal input terminal Si +, and the pre-amplifying unit is integrated with a capacitor C1 connected to the first signal input terminal Si-and the second signal input terminal Si +.
In one embodiment, the two-stage fully differential OTA unit comprises:
the first-stage fully-differential OTA unit comprises a first OTA amplifier and a capacitor C2 connected in parallel between the input end and the output end of the first OTA amplifier;
the second-stage fully-differential OTA unit comprises a second OTA amplifier and a capacitor C4 connected in parallel between the input end and the output end of the second OTA amplifier;
and a capacitor C3 connected in series between the output of the first OTA amplifier and the input of the second OTA amplifier.
In one embodiment, the output voltage of the two-stage fully-differential OTA unit at the time n +1 is:
wherein, Δ Voutn2 is the output voltage of the second stage fully differential OTA cell at time n, Δ Voutn1 is the output voltage of the first stage fully differential OTA unit at time n, Δ Vin1 is the input voltage of the first stage fully differential OTA unit, and Δ Vref is the voltage difference provided by the feedback compensation unit.
In an embodiment, a switch T1 is connected in series between the first signal input terminal Si + and the second signal input terminal Si + and the pre-amplification unit, a switch T2 is connected in parallel between the first signal input terminal Si + and the second signal input terminal Si +, a switch T1 is connected in series between the output terminal of the first OTA amplifier and the capacitor C3, a switch T2 is connected in parallel between the output terminals of the first OTA amplifier, a switch T2 is connected in series between the input terminal of the second OTA amplifier and the capacitor C3, and the switch T1 and the switch T2 are timing switches.
In one embodiment, the input of the first OTA amplifier and/or the second OTA amplifier is connected to the reference voltage Vt through a switch T1.
In one embodiment, the feedback compensation unit includes:
capacitors Cb1 and Cb2 connected to the input terminals of the first and second OTA amplifiers, respectively;
the switch T1 is arranged between the input ends of the first OTA amplifier and the second OTA amplifier and the capacitors Cb1 and Cb2 and is connected in parallel to two ends of the capacitors Cb1 and Cb 2;
a switch T2 connected to the capacitors Cb1 and Cb2, respectively;
switches Fb1 and Fb2, set between switch T2 and voltages Vref + and Vref-;
the switches T1, T2 and the switches Fb1, Fb2 are timing switches.
In one embodiment, the quantization comparing unit is configured to perform quantization comparison on the analog signal output by the two-stage fully differential OTA unit, and when the output voltage of the two-stage fully differential OTA unit is greater than 0, the quantization comparing unit outputs a logic level 1, and when the output voltage of the two-stage fully differential OTA unit is less than 0, the quantization comparing unit outputs a logic level 0.
In an embodiment, when the quantization comparing unit outputs a logic level 1, the feedback compensating unit performs voltage compensation of- Δ vref on the secondary fully-differential OTA unit, and when the quantization comparing unit outputs a logic level 0, the feedback compensating unit performs voltage compensation of + Δ vref on the secondary fully-differential OTA unit.
In one embodiment, the signal input by the second signal input terminal Si + and the voltage Vref satisfy:
wherein m is the number of the quantized comparator unit outputting logic level 1, and n is the number of the quantized comparator unit outputting logic level 0.
Compared with the prior art, the invention has the following advantages:
the invention can be suitable for effective extraction and quantitative transfer of small signals, and the design of the two-stage OTA can realize smaller harmonic distortion and better linear stability, and has better anti-interference performance and induction sensitivity.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a block diagram of a signal modulation circuit according to the present invention;
FIG. 2 is a schematic circuit diagram of a signal modulation circuit according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a feedback compensation unit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a signal modulation circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
Referring to fig. 1, the present invention discloses a signal modulation circuit, including:
a Pre-amplification unit (Pre) for amplifying the extracted input signal;
a Two-stage fully differential OTA unit (Two-Step OTA) including a first-stage fully differential OTA unit and a second-stage fully differential OTA unit for processing an input signal and outputting an analog signal;
the quantization comparison unit (Comp) is used for performing quantization comparison on the analog signal output by the two-stage fully differential OTA unit;
the Feedback compensation unit (Feedback) is used for compensating the secondary fully differential OTA unit according to the comparison result output by the quantization comparison unit;
and the time sequence control units (Timing1, Timing2 and Timing3) are used for carrying out time sequence control on the pre-amplification unit, the two-stage fully differential OTA unit, the quantization comparison unit and the feedback compensation unit.
The signal modulation circuit realizes the working states of the pre-amplification unit, the two-stage fully differential OTA unit, the quantization comparison unit and the feedback compensation unit through a strict time sequence control circuit.
The pre-amplification unit can perform 1 time, 2 times, 4 times and 8 times of adjustment and amplification according to the actual signal strength, and then sends the processed signal to the fully differential transconductance circuit (namely the secondary fully differential OTA unit). The fully differential transconductance circuit is designed in a 2-stage connection mode, and compared with a single-stage circuit, the two-stage design can realize smaller harmonic distortion and better linear stability under the condition of quantizing and outputting one bit. Signals after the summation of the two-stage fully differential transconductance circuit is completed can be directly sent to the quantization comparison circuit, and the quantization comparison unit can reduce noise signal interference and can effectively perform quantization output in period conversion time. The output result of the quantization comparison unit is simultaneously sent to a post-stage digital circuit processing unit (DSP) and a feedback compensation unit for digital signal processing and strict sequential circuit control.
The present invention is further illustrated by the following specific examples.
In the embodiment, the signal modulation circuit amplifies, extracts and quantizes the output signal of the pyroelectric infrared detector, and effectively converts the changed signal into a digital signal without distortion. The amplitude of the output signal of the pyroelectric infrared detector is about 1mV, the output frequency is about 1 Hz, and the central voltage is about 0.7V.
Referring to fig. 2, which is a schematic circuit diagram of a signal modulation circuit according to an embodiment of the present invention, a pre-amplifying unit is connected to a first signal input terminal Si-and a second signal input terminal Si +, and a capacitor C1 connected to the first signal input terminal Si-and the second signal input terminal Si + is integrated in the pre-amplifying unit.
The second-stage fully differential OTA unit comprises:
the first-stage fully-differential OTA unit comprises a first OTA amplifier and a capacitor C2 connected in parallel between the input end and the output end of the first OTA amplifier;
the second-stage fully-differential OTA unit comprises a second OTA amplifier and a capacitor C4 connected in parallel between the input end and the output end of the second OTA amplifier;
and a capacitor C3 connected in series between the output of the first OTA amplifier and the input of the second OTA amplifier.
In addition, a switch T1 is arranged between the first signal input end Si-and the second signal input end Si + and the pre-amplification unit in series, a switch T2 is arranged between the first signal input end Si-and the second signal input end Si + in parallel, a switch T1 is arranged between the output end of the first OTA amplifier and the capacitor C3 in series, a switch T2 is arranged between the output end of the first OTA amplifier in parallel, a switch T2 is arranged between the input end of the second OTA amplifier and the capacitor C3 in series, and the input ends of the first OTA amplifier and/or the second OTA amplifier are connected with the reference voltage Vt through the switch T1.
The switches T1 and T2 in this embodiment are time-sequential switches, i.e., at time T1, the switch T1 is fully on and the switch T2 is off, and at time T2, the switch T2 is fully on and the switch T1 is off.
The first signal input end Si-and the second signal input end Si + are two input ends for receiving signals, in the specific implementation process, the Si-port is connected with a voltage value of 0V, the Si + port is connected with a signal output port of the pyroelectric infrared sensor, the input signal of the Si + port is read at a certain moment, the pre-amplification unit selects 1 time of signal input, and in the conversion time period, the voltage value V of the point A in the graph 2 is reachedAThe voltage value reaching point B in FIG. 2 is VBWhich produces a difference value of Δ Vin 1. The voltage values of the C point and the D point of the output port are changed into V after the first-stage OTA processingCAnd VD. For the first-level OTA the formula is defined:
ΔVin1＝VA-VB；
ΔVout1＝VC-VD；
defining n state as the current conversion period time, n-1 state as the previous conversion period, and n +1 as the next conversion period, then:
C2×[ΔVoutn1-ΔVoutn-11]＝C1*ΔVin1±Cb1*ΔVref；
under the condition that the pre-amplification unit selects 1-time adjustment factor, Cb1 is equal to C1, and the following can be obtained:
ΔVoutn1＝ΔVoutn-11+(C1/C2)×(ΔVin1±ΔVref)；
ΔVoutn+11＝ΔVoutn1+(C1/C2)×(ΔVin1±ΔVref)。
at the same time, at points E and F of the second-stage OTA input terminal, the read voltage value is VEAnd VFThe difference produced is Δ Vin2, and the output voltage after the second-stage OTA processing is:
ΔVoutn+12＝ΔVoutn2+(C3/C4)×(ΔVin2±ΔVref)；
then the output calculation formula for the two-stage OTA operation process is:
wherein, Δ Voutn2 second stage fully differential OTA Unit at nInstantaneous output voltage, Δ Voutn1 is the output voltage of the first stage fully differential OTA unit at time n, Δ Vin1 is the input voltage of the first stage fully differential OTA unit, and Δ Vref is the voltage difference provided by the feedback compensation unit.
As can be seen from the above formula, Δ Vout2 will linger between positive and negative according to the amount of Δ Vref, and finally sent to the quantization comparison unit for quantization to output logic voltage.
Referring to fig. 3, the feedback compensation unit in the present embodiment includes:
capacitors Cb1 and Cb2 connected to the input terminals of the first and second OTA amplifiers, respectively;
the switch T1 is arranged between the input ends of the first OTA amplifier and the second OTA amplifier and the capacitors Cb1 and Cb2 and is connected in parallel to two ends of the capacitors Cb1 and Cb 2;
a switch T2 connected to the capacitors Cb1 and Cb2, respectively;
switches Fb1 and Fb2, set between switch T2 and voltages Vref + and Vref-;
the switches T1, T2 and the switches Fb1, Fb2 are timing switches.
The capacitor Cb1 and the capacitor Cb2 are charged under the control of the switch T1 at the first moment, after charging is completed, the capacitor Cb1 and the capacitor Cb2 are connected in series through the switch T2 at the second moment to complete delta Vref conversion, and at the moment, the voltage difference value between the A end and the B end in the graph 3 is delta Vref, so that the delta Vref can be directly sent to an OTA input end for compensation.
The quantization comparison unit in this embodiment is configured to perform quantization comparison on the analog signal output by the two-stage fully-differential OTA unit:
when the output voltage delta Vout2 of the two-stage fully differential OTA unit is greater than 0, the quantization comparison unit outputs a logic level 1;
when the output voltage Δ Vout2 of the two-stage fully differential OTA unit is less than 0, the quantization comparison unit outputs a logic level 0.
Finally, the generated logic levels 1 and 0 are sent to the digital signal processing unit, and are also used for the feedback compensation circuit to perform compensation control on the OTA1 and the OTA 2.
The feedback compensation unit is controlled by outputting logic levels 1 and 0, specifically:
when the quantization comparison unit outputs a logic level 1, the feedback compensation unit performs voltage compensation of-delta vref on the secondary fully differential OTA unit, and the plus or minus in each formula is minus or plus;
when the quantization comparison unit outputs a logic level 0, the feedback compensation unit performs voltage compensation of + delta vref on the two-stage fully differential OTA unit, and plus or minus is plus in each formula.
As shown in fig. 2 to fig. 4, the complete modulation circuit in this embodiment can complete the conversion operation of the Si + signal, and the circuit functions finally completed by the complete modulation circuit include:
at time 1, after receiving a pyroelectric infrared sensor signal Vin, Si + generates Δ Vin1 to be greater than 0 at an input end of OTA1, so that Δ Vout1 and Δ Vout2 output by OTA1 and OTA2 are both greater than 0, and the quantization comparison unit outputs a logic level 1;
at the time 2, after the Si + continuously receives the pyroelectric infrared sensor signal Vin, Δ Vin1 is generated at the input end of the OTA1, and at the same time, the feedback compensation circuit makes Δ Vin1- Δ Vref, and if Δ Vin1- Δ Vref is still greater than 0, the quantization comparison unit outputs a logic level 1 until Δ Vin1- Δ Vref becomes less than 0, and the quantization comparison unit outputs a logic level 0. Then the next time the input will become Δ Vin1+ Δ Vref and the circuit will continue to operate as it is. The output of the quantization and comparison unit generates a series of level signals between 1 and 0.
The signal input by the second signal input end Si + and the voltage Vref meet the following conditions:
wherein m is the number of the quantized comparator unit outputting logic level 1, and n is the number of the quantized comparator unit outputting logic level 0.
It should be understood that the circuit in the present invention can amplify, extract and quantify various signals, and is not limited to the pyroelectric infrared sensor detection signals described in the above embodiments.
According to the technical scheme, the invention has the following beneficial effects:
the invention can be suitable for effective extraction and quantitative transfer of small signals, and the design of the two-stage OTA can realize smaller harmonic distortion and better linear stability, and has better anti-interference performance and induction sensitivity.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (1)
1. A signal modulation circuit, characterized in that the signal modulation circuit comprises:
a pre-amplifying unit for amplifying the extracted input signal;
the second-stage fully differential OTA unit comprises a first-stage fully differential OTA unit and a second-stage fully differential OTA unit and is used for processing the input signal and outputting an analog signal;
the quantization comparison unit is used for performing quantization comparison on the analog signals output by the two-stage fully differential OTA unit;
the feedback compensation unit is used for compensating the secondary fully differential OTA unit according to the comparison result output by the quantization comparison unit;
the time sequence control unit is used for carrying out time sequence control on the pre-amplification unit, the secondary fully-differential OTA unit, the quantization comparison unit and the feedback compensation unit;
the pre-amplification unit is connected with the first signal input end Si-and the second signal input end Si +, and a capacitor C1 connected with the first signal input end Si-and the second signal input end Si + is integrated in the pre-amplification unit;
the two-stage fully differential OTA unit comprises:
the first-stage fully-differential OTA unit comprises a first OTA amplifier and a capacitor C2 connected in parallel between the input end and the output end of the first OTA amplifier;
the second-stage fully-differential OTA unit comprises a second OTA amplifier and a capacitor C4 connected in parallel between the input end and the output end of the second OTA amplifier;
and a capacitor C3 connected in series between the output of the first OTA amplifier and the input of the second OTA amplifier;
the output voltage of the two-stage fully differential OTA unit at the moment of n +1 is as follows:
wherein, Δ Voutn2 is the output voltage of the second stage fully differential OTA cell at time n, Δ Voutn1 is the output voltage of the first-stage fully-differential OTA unit at the time n, Δ Vin1 is the input voltage of the first-stage fully-differential OTA unit, and Δ Vref is the voltage difference provided by the feedback compensation unit;
a switch T1 is arranged between the first signal input end Si-and the second signal input end Si + and the pre-amplification unit in series, a switch T2 is arranged between the first signal input end Si-and the second signal input end Si + in parallel, a switch T1 is arranged between the output end of the first OTA amplifier and the capacitor C3 in series, a switch T2 is arranged between the output ends of the first OTA amplifier in parallel, a switch T2 is arranged between the input end of the second OTA amplifier and the capacitor C3 in series, and the switch T1 and the switch T2 are time sequence switches;
the input end of the first OTA amplifier and/or the second OTA amplifier is connected with a reference voltage Vt through a switch T1;
the feedback compensation unit includes:
capacitors Cb1 and Cb2 connected to the input terminals of the first and second OTA amplifiers, respectively;
the switch T1 is arranged between the input ends of the first OTA amplifier and the second OTA amplifier and the capacitors Cb1 and Cb2 and is connected in parallel to two ends of the capacitors Cb1 and Cb 2;
a switch T2 connected to the capacitors Cb1 and Cb2, respectively;
switches Fb1 and Fb2, set between switch T2 and voltages Vref + and Vref-;
the switches T1, T2 and the switches Fb1, Fb2 are timing switches;
the quantization comparison unit is used for performing quantization comparison on the analog signals output by the secondary fully differential OTA unit, when the output voltage of the secondary fully differential OTA unit is greater than 0, the quantization comparison unit outputs a logic level 1, and when the output voltage of the secondary fully differential OTA unit is less than 0, the quantization comparison unit outputs a logic level 0;
when the quantization comparison unit outputs a logic level 1, the feedback compensation unit performs voltage compensation of-delta vref on the secondary fully-differential OTA unit, and when the quantization comparison unit outputs a logic level 0, the feedback compensation unit performs voltage compensation of + delta vref on the secondary fully-differential OTA unit;
the signal input by the second signal input end Si + and the voltage Vref meet the following conditions:
wherein m is the number of the quantized comparator unit outputting logic level 1, and n is the number of the quantized comparator unit outputting logic level 0.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911167272.XA CN110798221B (en) | 2019-11-25 | 2019-11-25 | Signal modulation circuit |
| PCT/CN2020/121867 WO2021103851A1 (en) | 2019-11-25 | 2020-10-19 | Signal modulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911167272.XA CN110798221B (en) | 2019-11-25 | 2019-11-25 | Signal modulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110798221A CN110798221A (en) | 2020-02-14 |
| CN110798221B true CN110798221B (en) | 2022-02-08 |
Family
ID=69446052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911167272.XA Active CN110798221B (en) | 2019-11-25 | 2019-11-25 | Signal modulation circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110798221B (en) |
| WO (1) | WO2021103851A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798221B (en) * | 2019-11-25 | 2022-02-08 | 苏州华芯微电子股份有限公司 | Signal modulation circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027060A (en) * | 2016-05-20 | 2016-10-12 | 复旦大学 | Input feedforward type Delta-Sigma modulator |
| CN107994905A (en) * | 2018-01-17 | 2018-05-04 | 厦门理工学院 | A kind of analog front circuit for ECG signal sampling chip |
| CN108712172A (en) * | 2018-07-26 | 2018-10-26 | 福州大学 | A kind of incremental Sigma-Delta digital analog converters |
| CN208479598U (en) * | 2018-07-26 | 2019-02-05 | 福州大学 | Incremental digital analog converter applied to Temperature Humidity Sensor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843232B2 (en) * | 2009-02-27 | 2010-11-30 | Atmel Corporation | Dual mode, single ended to fully differential converter structure |
| CN110798221B (en) * | 2019-11-25 | 2022-02-08 | 苏州华芯微电子股份有限公司 | Signal modulation circuit |
-
2019
- 2019-11-25 CN CN201911167272.XA patent/CN110798221B/en active Active
-
2020
- 2020-10-19 WO PCT/CN2020/121867 patent/WO2021103851A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106027060A (en) * | 2016-05-20 | 2016-10-12 | 复旦大学 | Input feedforward type Delta-Sigma modulator |
| CN107994905A (en) * | 2018-01-17 | 2018-05-04 | 厦门理工学院 | A kind of analog front circuit for ECG signal sampling chip |
| CN108712172A (en) * | 2018-07-26 | 2018-10-26 | 福州大学 | A kind of incremental Sigma-Delta digital analog converters |
| CN208479598U (en) * | 2018-07-26 | 2019-02-05 | 福州大学 | Incremental digital analog converter applied to Temperature Humidity Sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110798221A (en) | 2020-02-14 |
| WO2021103851A1 (en) | 2021-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5892473A (en) | Switched capacitor digital-analog converter with a decreased harmonic distortion | |
| US10277175B2 (en) | Switched-capacitor input circuit, switched-capacitor amplifier, and switched-capacitor voltage comparator | |
| CN103308183A (en) | Reading circuit used for sensor | |
| CN108712172A (en) | A kind of incremental Sigma-Delta digital analog converters | |
| CN101640829B (en) | Digital preamplifier for MEMS microphone | |
| CN110798221B (en) | Signal modulation circuit | |
| CN111555727B (en) | High-gain low-noise switched capacitor adjustable gain amplifier | |
| CN103312333A (en) | Zero-optimization integrator circuit suitable for Sigma-Delta ADC (Analog To Digital Conversion) circuit | |
| CN103312334B (en) | Be applicable to the integrator circuit of Sigma-Delta adc circuit | |
| CN104950165A (en) | Detecting circuit and detecting method | |
| CN101420611A (en) | Video input decoding chip | |
| CN203278797U (en) | Zero optimization integrator circuit | |
| US20090167362A1 (en) | Comparator | |
| CN103023499A (en) | Analog-digital converter and operating method thereof | |
| KR20190021634A (en) | Discrete-time integrator circuit with operational amplifier gain compensation function | |
| CN204807622U (en) | Detection circuitry | |
| US8466822B2 (en) | Analog-to-digital conversion apparatus and signal processing system | |
| CN102045029A (en) | Operation amplifying circuit | |
| US20230188105A1 (en) | Analog signal processing circuit and method for eliminating dc offset voltage | |
| CN208479598U (en) | Incremental digital analog converter applied to Temperature Humidity Sensor | |
| CN108880548A (en) | Improved low-power switching type capacitor device integrator, A/D converter and switching type capacitor device amplifier | |
| CN105680805B (en) | A kind of dc-couple high-precision amplification device | |
| CN203278793U (en) | Integrator circuit | |
| CN111969963A (en) | Pre-amplifier | |
| CN101931376A (en) | Direct current isolated amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |