JP2012064721A - 電子機器および基板アセンブリ - Google Patents
電子機器および基板アセンブリ Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000007767 bonding agent Substances 0.000 claims description 95
- 230000017525 heat dissipation Effects 0.000 claims description 2
- 239000004020 conductor Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005304 joining Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
【解決手段】実施形態にかかる電子機器にあっては、筐体と、筐体内に設けられ、表面に露出した第一のパッドおよび第二のパッドを有した基板と、基板の表面に対向する基板対向面に露出して接合剤を介して第一のパッドに接合された第一の電極と、基板対向面に露出して接合剤を介して第二のパッドに接合されて第一の電極より広くかつ第一の電極より高く突出した第二の電極と、を有した部品と、を備えたことを特徴の一つとする。
【選択図】図2
Description
Vb=αb×Sb×Th×β ・・・ (1)
となる。よって、固化された状態での電極10bとパッド9bとを接合する接合剤12の、電極10bの単位面積あたりの体積Hbは、
Hb=Vb/Sb=αb×Th×β ・・・(2)
となる。
Vc=αc×Sc×Th×β ・・・ (3)
となる。よって、固化された状態での電極10cとパッド9cとを接合する接合剤12の、電極10cの単位面積あたりの体積Hcは、
Hc=Vc/Sc=αc×Th×β ・・・(4)
となる。
0.5(Hc−Hb)< ΔH <1.5(Hc−Hb) ・・・(5)
であれば、電極10b,10cの双方で接合剤12の接合状態が良好であることが判明した。さらに、
0.8(Hc−Hb)< ΔH <1.2(Hc−Hb) ・・・(6)
であれば、より一層好ましいことが判明した。そして、電極10b,10cの突出高さの差ΔHが、電極10b,10cの単位面積あたりの高さの差(Hc−Hb)に近いほど、すなわち、
Hc−Hb≒ΔH ・・・(7)
または、
Hc−Hb=ΔH ・・・(8)
である場合に、特に良好であることが判明した。また、具体的には、ΔHは、10〜150[μm](マイクロメートル)であるのが好ましく、20〜80[μm]であるのがより一層好ましいことが判明した。なお、電極10cに対応する開口率αcは、1(=100%)であるのが好ましい。
Vb=αb’×Sb’×Th×β ・・・ (1)’
となる。よって、固化された状態での電極10bとパッド9bとを接合する接合剤12の、電極10bの単位面積あたりの体積Hbは、
Hb=Vb/Sb’=αb’×Th×β ・・・(2)’
となる。
Claims (10)
- 筐体と、
前記筐体内に設けられ、表面に露出した第一のパッドおよび第二のパッドを有した基板と、
前記基板の前記表面に対向する基板対向面に露出して接合剤を介して前記第一のパッドに接合された第一の電極と、前記基板対向面に露出して接合剤を介して前記第二のパッドに接合されて前記第一の電極より広くかつ前記第一の電極より高く突出した第二の電極と、を有した部品と、
を備えた電子機器。 - 前記第一の電極と前記第一のパッドとを接合した前記接合剤の厚さが、前記第二の電極と前記第二のパッドとを接合した前記接合剤の厚さより大きいことを特徴とする請求項1に記載の電子機器。
- 前記第二のパッドが、前記表面上では相互に隔離された複数のパッド部を有したことを特徴とする請求項1または2に記載の電子機器。
- 前記第一の電極および前記第二の電極が、前記基板対向面から突出したことを特徴とする請求項1〜3のうちいずれか一つに記載の電子機器。
- 前記第一の電極が信号電極であり、かつ前記第二の電極が放熱電極であることを特徴とする請求項1〜4のうちいずれか一つに記載の電子機器。
- 前記第一の電極と前記第一のパッドとを接合した接合剤の、当該接合剤が接合された前記第一の電極の単位面積あたりの体積が、前記第二の電極と前記第二のパッドとを接合した接合剤の、当該接合剤が接合された前記第二の電極の単位面積あたりの体積より、大きいことを特徴とする請求項1〜5のうちいずれか一つに記載の電子機器。
- 前記第一の電極と前記第二の電極との突出高さの差を、ΔHとし、
前記第一の電極と前記第一のパッドとを接合した接合剤の、当該接合剤が接合された前記第一の電極の単位面積あたりの体積を、Hcとし、
前記第二の電極と前記第二のパッドとを接合した接合剤の、当該接合剤が接合された前記第二の電極の単位面積あたりの体積を、Hbとしたとき、
0.5(Hc−Hb)< ΔH <1.5(Hc−Hb)
であることを特徴とする請求項6に記載の電子機器。 - 筐体と、
前記筐体内に設けられ、表面に露出した第一のパッドおよび第二のパッドを有した基板と、
接合剤を介して前記第一のパッドに接合された第一の電極と、接合剤を介して前記第二のパッドに接合された第二の電極と、を有した部品と、
を備え、
前記第一の電極とこれに前記接合剤を介して接合された前記第一のパッドとの間の第一の距離が、前記第二の電極とこれに前記接合剤を介して接合された前記第二のパッドとの間の第二の距離より大きいことを特徴とする電子機器。 - 表面に露出した第一のパッドおよび第二のパッドを有した基板と、
前記基板の前記表面に対向する基板対向面に露出して接合剤を介して前記第一のパッドに接合された第一の電極と、前記基板対向面に露出して接合剤を介して前記第二のパッドに接合されて前記第一の電極より広い第二の電極と、を有した部品と、
を備え、
前記第二の電極が前記第一の電極より前記基板側へ突出したことを特徴とする基板アセンブリ。 - 基板対向面に露出した第一の電極と、
前記基板対向面に露出して前記第一の電極より広くかつ前記第一の電極より突出した第二の電極と、
を有したことを特徴とする半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010207030A JP4996729B2 (ja) | 2010-09-15 | 2010-09-15 | 電子機器および基板アセンブリ |
US13/082,217 US20120063102A1 (en) | 2010-09-15 | 2011-04-07 | Electronic Device, Circuit Board Assembly, and Semiconductor Device |
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JP2010207030A JP4996729B2 (ja) | 2010-09-15 | 2010-09-15 | 電子機器および基板アセンブリ |
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Publication Number | Publication Date |
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JP2012064721A true JP2012064721A (ja) | 2012-03-29 |
JP4996729B2 JP4996729B2 (ja) | 2012-08-08 |
Family
ID=45806548
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US (1) | US20120063102A1 (ja) |
JP (1) | JP4996729B2 (ja) |
Cited By (1)
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KR20200107200A (ko) * | 2019-03-06 | 2020-09-16 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001267484A (ja) * | 2000-03-14 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002134654A (ja) * | 2001-10-29 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置及びその製造方法 |
JP2003168764A (ja) * | 2001-11-30 | 2003-06-13 | Fujitsu Ltd | 半導体装置 |
JP2006041224A (ja) * | 2004-07-28 | 2006-02-09 | Denso Corp | 電子装置および電子装置の実装構造 |
Family Cites Families (7)
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JP2924854B2 (ja) * | 1997-05-20 | 1999-07-26 | 日本電気株式会社 | 半導体装置、その製造方法 |
TW586208B (en) * | 2002-02-26 | 2004-05-01 | Advanced Semiconductor Eng | Wafer-level packaging structure |
KR100975521B1 (ko) * | 2003-10-04 | 2010-08-12 | 삼성전자주식회사 | 발광 소자 조립체 |
US7476976B2 (en) * | 2005-02-23 | 2009-01-13 | Texas Instruments Incorporated | Flip chip package with advanced electrical and thermal properties for high current designs |
SG139573A1 (en) * | 2006-07-17 | 2008-02-29 | Micron Technology Inc | Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods |
JP2008227271A (ja) * | 2007-03-14 | 2008-09-25 | Fujitsu Ltd | 電子装置および電子部品実装方法 |
JP2009105212A (ja) * | 2007-10-23 | 2009-05-14 | Toshiba Corp | プリント配線板および電子機器 |
-
2010
- 2010-09-15 JP JP2010207030A patent/JP4996729B2/ja active Active
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- 2011-04-07 US US13/082,217 patent/US20120063102A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001267484A (ja) * | 2000-03-14 | 2001-09-28 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2002134654A (ja) * | 2001-10-29 | 2002-05-10 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置及びその製造方法 |
JP2003168764A (ja) * | 2001-11-30 | 2003-06-13 | Fujitsu Ltd | 半導体装置 |
JP2006041224A (ja) * | 2004-07-28 | 2006-02-09 | Denso Corp | 電子装置および電子装置の実装構造 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200107200A (ko) * | 2019-03-06 | 2020-09-16 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
KR102600022B1 (ko) * | 2019-03-06 | 2023-11-07 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
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US20120063102A1 (en) | 2012-03-15 |
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