JP2011508983A5 - - Google Patents

Download PDF

Info

Publication number
JP2011508983A5
JP2011508983A5 JP2010541477A JP2010541477A JP2011508983A5 JP 2011508983 A5 JP2011508983 A5 JP 2011508983A5 JP 2010541477 A JP2010541477 A JP 2010541477A JP 2010541477 A JP2010541477 A JP 2010541477A JP 2011508983 A5 JP2011508983 A5 JP 2011508983A5
Authority
JP
Japan
Prior art keywords
copper
stud
tin
external contact
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2010541477A
Other languages
English (en)
Japanese (ja)
Other versions
JP5248627B2 (ja
JP2011508983A (ja
Filing date
Publication date
Priority claimed from US11/969,368 external-priority patent/US7807572B2/en
Application filed filed Critical
Publication of JP2011508983A publication Critical patent/JP2011508983A/ja
Publication of JP2011508983A5 publication Critical patent/JP2011508983A5/ja
Application granted granted Critical
Publication of JP5248627B2 publication Critical patent/JP5248627B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2010541477A 2008-01-04 2008-12-16 半導体のマイクロパッド形成方法 Active JP5248627B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/969,368 2008-01-04
US11/969,368 US7807572B2 (en) 2008-01-04 2008-01-04 Micropad formation for a semiconductor
PCT/US2008/086920 WO2009088659A2 (en) 2008-01-04 2008-12-16 Micropad formation for a semiconductor

Publications (3)

Publication Number Publication Date
JP2011508983A JP2011508983A (ja) 2011-03-17
JP2011508983A5 true JP2011508983A5 (enExample) 2012-02-09
JP5248627B2 JP5248627B2 (ja) 2013-07-31

Family

ID=40844919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010541477A Active JP5248627B2 (ja) 2008-01-04 2008-12-16 半導体のマイクロパッド形成方法

Country Status (5)

Country Link
US (1) US7807572B2 (enExample)
JP (1) JP5248627B2 (enExample)
CN (1) CN101911292B (enExample)
TW (1) TWI442476B (enExample)
WO (1) WO2009088659A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2298960A1 (en) * 2009-08-24 2011-03-23 ATOTECH Deutschland GmbH Method for electroless plating of tin and tin alloys
US20120175772A1 (en) * 2011-01-07 2012-07-12 Leung Andrew K Alternative surface finishes for flip-chip ball grid arrays
US9117772B2 (en) * 2012-06-19 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding package components through plating
JP6079374B2 (ja) * 2013-03-29 2017-02-15 三菱マテリアル株式会社 ハンダ粉末の製造方法及びこの粉末を用いたハンダ用ペースト
JP6181441B2 (ja) * 2013-06-24 2017-08-16 新光電気工業株式会社 パッド構造、実装構造、及び、製造方法
DE102016109349A1 (de) 2016-05-20 2017-11-23 Infineon Technologies Ag Chipgehäuse, verfahren zum bilden eines chipgehäuses und verfahren zum bilden eines elektrischen kontakts
US11276659B2 (en) 2020-02-28 2022-03-15 Micron Technology, Inc. Methods for forming elements for microelectronic components, related conductive elements, and microelectronic components, assemblies and electronic systems incorporating such conductive elements

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3395040A (en) * 1965-01-06 1968-07-30 Texas Instruments Inc Process for fabricating cryogenic devices
US4692349A (en) 1986-03-03 1987-09-08 American Telephone And Telegraph Company, At&T Bell Laboratories Selective electroless plating of vias in VLSI devices
US4832799A (en) 1987-02-24 1989-05-23 Polyonics Corporation Process for coating at least one surface of a polyimide sheet with copper
US5309632A (en) 1988-03-28 1994-05-10 Hitachi Chemical Co., Ltd. Process for producing printed wiring board
US5162144A (en) 1991-08-01 1992-11-10 Motorola, Inc. Process for metallizing substrates using starved-reaction metal-oxide reduction
US5196053A (en) * 1991-11-27 1993-03-23 Mcgean-Rohco, Inc. Complexing agent for displacement tin plating
WO1995022840A1 (de) 1994-02-16 1995-08-24 Siemens Aktiengesellschaft Verfahren zur herstellung einer dreidimensionalen schaltungsanordnung
JPH09170083A (ja) * 1995-12-20 1997-06-30 Mitsubishi Electric Corp スズまたはスズ合金の無電解めっき方法
US6245658B1 (en) 1999-02-18 2001-06-12 Advanced Micro Devices, Inc. Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system
US6882045B2 (en) * 1999-10-28 2005-04-19 Thomas J. Massingill Multi-chip module and method for forming and method for deplating defective capacitors
US6361823B1 (en) 1999-12-03 2002-03-26 Atotech Deutschland Gmbh Process for whisker-free aqueous electroless tin plating
US6638847B1 (en) * 2000-04-19 2003-10-28 Advanced Interconnect Technology Ltd. Method of forming lead-free bump interconnections
TW571005B (en) 2000-06-29 2004-01-11 Ebara Corp Method and apparatus for forming copper interconnects, and polishing liquid and polishing method
WO2002004704A2 (en) * 2000-07-11 2002-01-17 Applied Materials, Inc. Method and apparatus for patching electrochemically deposited layers using electroless deposited materials
US6551931B1 (en) 2000-11-07 2003-04-22 International Business Machines Corporation Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped
JP3642034B2 (ja) * 2001-03-26 2005-04-27 日立電線株式会社 半導体装置用テープキャリア及びその製造方法
US6689680B2 (en) * 2001-07-14 2004-02-10 Motorola, Inc. Semiconductor device and method of formation
US6680128B2 (en) 2001-09-27 2004-01-20 Agilent Technologies, Inc. Method of making lead-free solder and solder paste with improved wetting and shelf life
US6605874B2 (en) 2001-12-19 2003-08-12 Intel Corporation Method of making semiconductor device using an interconnect
US6824666B2 (en) 2002-01-28 2004-11-30 Applied Materials, Inc. Electroless deposition method over sub-micron apertures
JP2003282615A (ja) 2002-03-20 2003-10-03 Seiko Epson Corp バンプの構造、バンプの形成方法、半導体装置およびその製造方法並びに電子機器
JP2003282616A (ja) * 2002-03-20 2003-10-03 Seiko Epson Corp バンプの形成方法及び半導体装置の製造方法
US6750133B2 (en) * 2002-10-24 2004-06-15 Intel Corporation Selective ball-limiting metallurgy etching processes for fabrication of electroplated tin bumps
JP3815429B2 (ja) * 2002-12-05 2006-08-30 日立電線株式会社 半導体装置用テープキャリアの製造方法
TWI229930B (en) 2003-06-09 2005-03-21 Advanced Semiconductor Eng Chip structure
US6924232B2 (en) 2003-08-27 2005-08-02 Freescale Semiconductor, Inc. Semiconductor process and composition for forming a barrier material overlying copper
US7049234B2 (en) 2003-12-22 2006-05-23 Intel Corporation Multiple stage electroless deposition of a metal layer
US7119019B2 (en) * 2004-03-31 2006-10-10 Intel Corporation Capping of copper structures in hydrophobic ILD using aqueous electro-less bath
KR100597993B1 (ko) 2004-04-08 2006-07-10 주식회사 네패스 반도체 패키지용 범프, 그 범프를 적용한 반도체 패키지 및 제조방법
KR100642633B1 (ko) 2004-06-11 2006-11-10 삼성전자주식회사 엠아이엠 캐패시터들 및 그의 제조 방법
US7745376B2 (en) * 2004-08-10 2010-06-29 Nove Technologies, Inc. Superconducting composite
US7078272B2 (en) 2004-09-20 2006-07-18 Aptos Corporation Wafer scale integration packaging and method of making and using the same
US7449409B2 (en) * 2005-03-14 2008-11-11 Infineon Technologies Ag Barrier layer for conductive features
US7317253B2 (en) 2005-04-25 2008-01-08 Sony Corporation Cobalt tungsten phosphate used to fill voids arising in a copper metallization process
US7585760B2 (en) 2006-06-23 2009-09-08 Intel Corporation Method for forming planarizing copper in a low-k dielectric
US7572723B2 (en) 2006-10-25 2009-08-11 Freescale Semiconductor, Inc. Micropad for bonding and a method therefor

Similar Documents

Publication Publication Date Title
JP2011508983A5 (enExample)
RU2016108818A (ru) Сверхпроводник и способ его изготовления
JP2012038996A5 (enExample)
JP2013251255A5 (enExample)
JP2010174373A5 (enExample)
JP2012253331A5 (enExample)
JP2011100991A5 (enExample)
EP2811513A4 (en) SUBSTRATE FOR POWER MODULES, SUBSTRATE WITH COOLING BODY FOR POWER MODULES, POWER MODULE, METHOD FOR PRODUCING A SUBSTRATE FOR POWER MODULES AND PASTE FOR JOINING COPPER ELEMENTS
JP2012248829A5 (ja) 半導体装置の作製方法
JP2009231824A5 (ja) 半導体装置
JP2013065843A5 (enExample)
WO2010074956A3 (en) Doping of lead-free solder alloys and structures formed thereby
EP1947215A3 (en) Method for forming a displacement tin alloy plated film, displacement tin alloy plating bath and method for maintaining a plating performance
JP2017038062A5 (enExample)
JP2011100990A5 (ja) 半導体装置
FR2982422B1 (fr) Substrat conducteur pour cellule photovoltaique
CN103606542A (zh) 穿透硅通孔金属互连结构及其制造方法
JP2014086728A5 (enExample)
JP2013028864A5 (ja) 銀ナノ粒子を製造するプロセスおよび導電性要素を製造するプロセス
JP2013517375A5 (enExample)
JP2010171107A5 (ja) 半導体装置
WO2015179035A3 (en) Production and use of flexible conductive films and inorganic layers in electronic devices
JP2014526807A5 (enExample)
JP2015115543A5 (enExample)
JP2012519374A5 (enExample)