JP2011176293A5 - - Google Patents

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Publication number
JP2011176293A5
JP2011176293A5 JP2011012518A JP2011012518A JP2011176293A5 JP 2011176293 A5 JP2011176293 A5 JP 2011176293A5 JP 2011012518 A JP2011012518 A JP 2011012518A JP 2011012518 A JP2011012518 A JP 2011012518A JP 2011176293 A5 JP2011176293 A5 JP 2011176293A5
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JP
Japan
Prior art keywords
semiconductor wafer
forming
semiconductor
insulating layer
heat treatment
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JP2011012518A
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English (en)
Japanese (ja)
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JP5719611B2 (ja
JP2011176293A (ja
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Priority to JP2011012518A priority Critical patent/JP5719611B2/ja
Priority claimed from JP2011012518A external-priority patent/JP5719611B2/ja
Publication of JP2011176293A publication Critical patent/JP2011176293A/ja
Publication of JP2011176293A5 publication Critical patent/JP2011176293A5/ja
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Publication of JP5719611B2 publication Critical patent/JP5719611B2/ja
Expired - Fee Related legal-status Critical Current
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JP2011012518A 2010-01-26 2011-01-25 Soi基板の作製方法 Expired - Fee Related JP5719611B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011012518A JP5719611B2 (ja) 2010-01-26 2011-01-25 Soi基板の作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010014880 2010-01-26
JP2010014880 2010-01-26
JP2011012518A JP5719611B2 (ja) 2010-01-26 2011-01-25 Soi基板の作製方法

Publications (3)

Publication Number Publication Date
JP2011176293A JP2011176293A (ja) 2011-09-08
JP2011176293A5 true JP2011176293A5 (enExample) 2013-12-26
JP5719611B2 JP5719611B2 (ja) 2015-05-20

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Family Applications (1)

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JP2011012518A Expired - Fee Related JP5719611B2 (ja) 2010-01-26 2011-01-25 Soi基板の作製方法

Country Status (3)

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US (1) US8367517B2 (enExample)
JP (1) JP5719611B2 (enExample)
SG (1) SG173283A1 (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5799740B2 (ja) * 2011-10-17 2015-10-28 信越半導体株式会社 剥離ウェーハの再生加工方法
JP2013093434A (ja) * 2011-10-26 2013-05-16 Semiconductor Energy Lab Co Ltd 半導体基板の解析方法
JP2014082316A (ja) 2012-10-16 2014-05-08 Shin Etsu Handotai Co Ltd Soiウェーハの製造方法
JP2014107357A (ja) * 2012-11-26 2014-06-09 Shin Etsu Handotai Co Ltd Soiウェーハの製造方法
KR101792066B1 (ko) * 2013-10-31 2017-11-01 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 게르마늄층을 열처리하는 반도체 기판의 제조 방법 및 반도체 장치의 제조 방법
JP6366383B2 (ja) * 2014-06-27 2018-08-01 株式会社ディスコ 加工装置
KR101911764B1 (ko) * 2014-11-05 2018-10-26 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 게르마늄층을 채널 영역으로 하는 반도체 장치 및 그 제조 방법
US9620376B2 (en) * 2015-08-19 2017-04-11 Lam Research Corporation Self limiting lateral atomic layer etch
DE102016000051A1 (de) * 2016-01-05 2017-07-06 Siltectra Gmbh Verfahren und Vorrichtung zum planaren Erzeugen von Modifikationen in Festkörpern
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
KR101820680B1 (ko) * 2016-12-05 2018-01-22 에스케이실트론 주식회사 반도체 기판 제조 방법
EP3706158A4 (en) 2017-11-02 2021-01-06 Showa Denko K.K. ETCHING PROCESS AND SEMICONDUCTOR MANUFACTURING PROCESS
CN110544668B (zh) * 2018-05-28 2022-03-25 沈阳硅基科技有限公司 一种通过贴膜改变soi边缘stir的方法
US11710656B2 (en) 2019-09-30 2023-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor-on-insulator (SOI) substrate
DE102020107236B4 (de) * 2019-09-30 2023-05-04 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum herstellen eines halbleiter-auf-isolator(soi)-substrats
CN116223183B (zh) * 2023-03-31 2026-02-03 洛阳中硅高科技有限公司 硅基体消解液、有机硅烷痕量金属杂质的检测方法以及试剂盒
FR3163205A1 (fr) * 2024-06-10 2025-12-12 Soitec Procédé de fabrication d’une plaquette donneuse pour le transfert de couches minces, et plaquette donneuse

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2635450B2 (ja) * 1991-03-26 1997-07-30 信越半導体株式会社 中性子照射用原料czシリコン単結晶
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3697106B2 (ja) 1998-05-15 2005-09-21 キヤノン株式会社 半導体基板の作製方法及び半導体薄膜の作製方法
JP2001144275A (ja) 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせsoiウエーハの製造方法および貼り合わせsoiウエーハ
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
FR2858875B1 (fr) * 2003-08-12 2006-02-10 Soitec Silicon On Insulator Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse
JP4552856B2 (ja) * 2003-09-05 2010-09-29 株式会社Sumco Soiウェーハの作製方法
EP1806769B1 (en) * 2004-09-13 2013-11-06 Shin-Etsu Handotai Co., Ltd. Soi wafer manufacturing method
JP2006294737A (ja) 2005-04-07 2006-10-26 Sumco Corp Soi基板の製造方法及びその製造における剥離ウェーハの再生処理方法。
JP4715470B2 (ja) * 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
US20070148917A1 (en) * 2005-12-22 2007-06-28 Sumco Corporation Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer
US7829436B2 (en) * 2005-12-22 2010-11-09 Sumco Corporation Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
FR2899380B1 (fr) * 2006-03-31 2008-08-29 Soitec Sa Procede de revelation de defauts cristallins dans un substrat massif.
JP5314838B2 (ja) 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法
JP5289805B2 (ja) 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
JP5459899B2 (ja) * 2007-06-01 2014-04-02 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20090061593A1 (en) * 2007-08-28 2009-03-05 Kishor Purushottam Gadkaree Semiconductor Wafer Re-Use in an Exfoliation Process Using Heat Treatment
JP5522917B2 (ja) 2007-10-10 2014-06-18 株式会社半導体エネルギー研究所 Soi基板の製造方法
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate

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