JP2011044795A - 入力インターフェース回路 - Google Patents

入力インターフェース回路 Download PDF

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Publication number
JP2011044795A
JP2011044795A JP2009190102A JP2009190102A JP2011044795A JP 2011044795 A JP2011044795 A JP 2011044795A JP 2009190102 A JP2009190102 A JP 2009190102A JP 2009190102 A JP2009190102 A JP 2009190102A JP 2011044795 A JP2011044795 A JP 2011044795A
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JP
Japan
Prior art keywords
circuit
clock
delay
input
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009190102A
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English (en)
Japanese (ja)
Other versions
JP2011044795A5 (enrdf_load_stackoverflow
Inventor
Kazuchika Watanabe
一央 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2009190102A priority Critical patent/JP2011044795A/ja
Priority to US12/801,482 priority patent/US8446196B2/en
Priority to CN2010102370931A priority patent/CN101996674A/zh
Publication of JP2011044795A publication Critical patent/JP2011044795A/ja
Publication of JP2011044795A5 publication Critical patent/JP2011044795A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means

Landscapes

  • Pulse Circuits (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP2009190102A 2009-08-19 2009-08-19 入力インターフェース回路 Pending JP2011044795A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009190102A JP2011044795A (ja) 2009-08-19 2009-08-19 入力インターフェース回路
US12/801,482 US8446196B2 (en) 2009-08-19 2010-06-10 Input interface circuit
CN2010102370931A CN101996674A (zh) 2009-08-19 2010-07-21 输入接口电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009190102A JP2011044795A (ja) 2009-08-19 2009-08-19 入力インターフェース回路

Publications (2)

Publication Number Publication Date
JP2011044795A true JP2011044795A (ja) 2011-03-03
JP2011044795A5 JP2011044795A5 (enrdf_load_stackoverflow) 2012-04-05

Family

ID=43604848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009190102A Pending JP2011044795A (ja) 2009-08-19 2009-08-19 入力インターフェース回路

Country Status (3)

Country Link
US (1) US8446196B2 (enrdf_load_stackoverflow)
JP (1) JP2011044795A (enrdf_load_stackoverflow)
CN (1) CN101996674A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8976596B1 (en) 2013-08-23 2015-03-10 Kabushiki Kaisha Toshiba Controller
JP2018064233A (ja) * 2016-10-14 2018-04-19 日本電気株式会社 スルーレート調整回路、及びスルーレート調整方法
WO2021145109A1 (ja) * 2020-01-16 2021-07-22 ソニーセミコンダクタソリューションズ株式会社 受信回路

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6051500B2 (ja) 2011-03-15 2016-12-27 株式会社リコー 画像読取装置及び電子機器
EP2774151B1 (en) * 2011-11-01 2019-08-14 Rambus Inc. Data transmission using delayed timing signals
US9479173B1 (en) * 2012-01-27 2016-10-25 Altera Corporation Transition accelerator circuitry
US9325542B2 (en) * 2012-11-21 2016-04-26 Globalfoundries Inc. Power-scalable skew compensation in source-synchronous parallel interfaces
KR20170008077A (ko) * 2015-07-13 2017-01-23 에스케이하이닉스 주식회사 고속 통신을 위한 인터페이스 회로 및 이를 포함하는 시스템
CN105262464B (zh) * 2015-11-16 2018-05-08 西安紫光国芯半导体有限公司 减小芯片输入端口所需建立保持时间的电路及方法
CN107591173B (zh) * 2016-07-06 2020-07-03 华邦电子股份有限公司 半导体存储器装置及其时脉调整方法
US10347307B2 (en) * 2017-06-29 2019-07-09 SK Hynix Inc. Skew control circuit and interface circuit including the same
US10256795B1 (en) * 2017-10-11 2019-04-09 Micron Technology, Inc. Pipelined latches to prevent metastability
KR102495361B1 (ko) * 2018-03-14 2023-02-06 에스케이하이닉스 주식회사 입출력 회로
US10431293B1 (en) * 2018-07-23 2019-10-01 Micron Technology, Inc. Systems and methods for controlling data strobe signals during read operations
CN110827885B (zh) * 2018-08-13 2023-03-31 华邦电子股份有限公司 输入接收器电路及自适应反馈方法
CN112003604B (zh) * 2020-08-24 2025-06-06 深圳线易微电子有限公司 一种信号传输电路与信号传输网络

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10336008A (ja) * 1997-05-30 1998-12-18 Fujitsu Ltd クロック発生回路及び半導体装置
JP2004342212A (ja) * 2003-05-15 2004-12-02 Elpida Memory Inc クロック発生回路およびそれを用いた半導体記憶装置
JP2005044854A (ja) * 2003-07-23 2005-02-17 Handotai Rikougaku Kenkyu Center:Kk クロックツリー回路、半導体集積回路装置、半導体集積回路装置の設計方法、および、半導体集積回路の設計プログラムを記録した媒体
JP2007265606A (ja) * 2007-05-18 2007-10-11 Fujitsu Ltd 半導体集積回路
JP2008071018A (ja) * 2006-09-13 2008-03-27 Matsushita Electric Ind Co Ltd メモリインターフェース回路
JP2009124703A (ja) * 2007-11-09 2009-06-04 Hynix Semiconductor Inc データセンタートラッキング回路及びこれを含む半導体集積回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4443728B2 (ja) * 2000-06-09 2010-03-31 株式会社ルネサステクノロジ クロック発生回路
KR100812602B1 (ko) * 2006-09-29 2008-03-13 주식회사 하이닉스반도체 반도체 메모리 장치 및 그 구동방법

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10336008A (ja) * 1997-05-30 1998-12-18 Fujitsu Ltd クロック発生回路及び半導体装置
JP2004342212A (ja) * 2003-05-15 2004-12-02 Elpida Memory Inc クロック発生回路およびそれを用いた半導体記憶装置
JP2005044854A (ja) * 2003-07-23 2005-02-17 Handotai Rikougaku Kenkyu Center:Kk クロックツリー回路、半導体集積回路装置、半導体集積回路装置の設計方法、および、半導体集積回路の設計プログラムを記録した媒体
JP2008071018A (ja) * 2006-09-13 2008-03-27 Matsushita Electric Ind Co Ltd メモリインターフェース回路
JP2007265606A (ja) * 2007-05-18 2007-10-11 Fujitsu Ltd 半導体集積回路
JP2009124703A (ja) * 2007-11-09 2009-06-04 Hynix Semiconductor Inc データセンタートラッキング回路及びこれを含む半導体集積回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8976596B1 (en) 2013-08-23 2015-03-10 Kabushiki Kaisha Toshiba Controller
JP2018064233A (ja) * 2016-10-14 2018-04-19 日本電気株式会社 スルーレート調整回路、及びスルーレート調整方法
US10374586B2 (en) 2016-10-14 2019-08-06 Nec Corporation Slew rate adjusting circuit and slew rate adjusting method
WO2021145109A1 (ja) * 2020-01-16 2021-07-22 ソニーセミコンダクタソリューションズ株式会社 受信回路
JP7600145B2 (ja) 2020-01-16 2024-12-16 ソニーセミコンダクタソリューションズ株式会社 受信回路

Also Published As

Publication number Publication date
US20110043262A1 (en) 2011-02-24
CN101996674A (zh) 2011-03-30
US8446196B2 (en) 2013-05-21

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