JP2010518760A - ハイスピード・シリアル・リンクのミッション環境における、該ハイスピード・シリアル・リンクの物理層テスティングのためのシステム及び方法 - Google Patents

ハイスピード・シリアル・リンクのミッション環境における、該ハイスピード・シリアル・リンクの物理層テスティングのためのシステム及び方法 Download PDF

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JP2010518760A
JP2010518760A JP2009549272A JP2009549272A JP2010518760A JP 2010518760 A JP2010518760 A JP 2010518760A JP 2009549272 A JP2009549272 A JP 2009549272A JP 2009549272 A JP2009549272 A JP 2009549272A JP 2010518760 A JP2010518760 A JP 2010518760A
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high speed
data
speed serial
signal
tester
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JP2010518760A5 (enExample
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ハフェド，モハメッド・エム
ダンセレオ，ドナルド
デュアデン，ジェフリー
ラバージ，セバスチャン
ナゾン，イヴォン
タム，クラレンス・カー，ラン
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ディー・エフ・ティー・マイクロシステムズ・インコーポレーテッド
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31708—Analysis of signal quality
    • G01R31/31711—Evaluation methods, e.g. shmoo plots
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31901—Analysis of tester Performance; Tester characterization
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Calibration Of Command Recording Devices (AREA)
  • Information Transfer Systems (AREA)
JP2009549272A 2007-02-09 2008-02-08 ハイスピード・シリアル・リンクのミッション環境における、該ハイスピード・シリアル・リンクの物理層テスティングのためのシステム及び方法 Pending JP2010518760A (ja)

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US88908507P 2007-02-09 2007-02-09
PCT/US2008/053476 WO2008098202A2 (en) 2007-02-09 2008-02-08 Physical-layer testing of high-speed serial links in their mission environments

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JP2010518760A true JP2010518760A (ja) 2010-05-27
JP2010518760A5 JP2010518760A5 (enExample) 2012-04-12

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US (1) US20080192814A1 (enExample)
EP (1) EP2115940A2 (enExample)
JP (1) JP2010518760A (enExample)
TW (1) TW200935781A (enExample)
WO (1) WO2008098202A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022524715A (ja) * 2019-01-31 2022-05-10 テクトロニクス・インコーポレイテッド 高速入出力マージン試験のためのシステム、方法及び装置

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8327204B2 (en) * 2005-10-27 2012-12-04 Dft Microsystems, Inc. High-speed transceiver tester incorporating jitter injection
US7681091B2 (en) * 2006-07-14 2010-03-16 Dft Microsystems, Inc. Signal integrity measurement systems and methods using a predominantly digital time-base generator
US7813297B2 (en) * 2006-07-14 2010-10-12 Dft Microsystems, Inc. High-speed signal testing system having oscilloscope functionality
JP4796645B2 (ja) * 2007-03-27 2011-10-19 富士通株式会社 イコライザ特性最適化方法、伝送システム、通信装置及びプログラム
US7869379B2 (en) * 2007-05-18 2011-01-11 International Business Machines Corporation Method for monitoring channel eye characteristics in a high-speed SerDes data link
US7715323B2 (en) * 2007-05-18 2010-05-11 International Business Machines Corporation Method for monitoring BER in an infiniband environment
US7797121B2 (en) * 2007-06-07 2010-09-14 Advantest Corporation Test apparatus, and device for calibration
US8085837B2 (en) * 2007-06-19 2011-12-27 Agere Systems Inc. Characterizing non-compensable jitter in an electronic signal
US7949489B2 (en) * 2007-07-26 2011-05-24 International Business Machines Corporation Detecting cable length in a storage subsystem with wide ports
US7903746B2 (en) * 2007-07-26 2011-03-08 International Business Machines Corporation Calibrating parameters in a storage subsystem with wide ports
US8229048B2 (en) * 2007-09-11 2012-07-24 Oracle America, Inc. Use of emphasis to equalize high speed signal quality
US7917319B2 (en) * 2008-02-06 2011-03-29 Dft Microsystems Inc. Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits
US8234540B2 (en) 2008-07-01 2012-07-31 International Business Machines Corporation Error correcting code protected quasi-static bit communication on a high-speed bus
US8180935B2 (en) * 2009-05-22 2012-05-15 Lsi Corporation Methods and apparatus for interconnecting SAS devices using either electrical or optical transceivers
US20110267073A1 (en) * 2010-04-29 2011-11-03 Juniper Networks, Inc. Validating high speed link performance margin for switch fabric with any-to-any connection across a midplane
US8527815B2 (en) * 2010-09-16 2013-09-03 Lsi Corporation Method for detecting a failure in a SAS/SATA topology
EP2628087B1 (en) * 2010-10-15 2015-04-22 ST-Ericsson SA Methods and systems for testing electrical behavior of an interconnect having asymmetrical links
US8855178B2 (en) * 2011-03-02 2014-10-07 Mediatek Inc. Signal transmitter and signal transmitting method for transmitting specific data bit with different predetermined voltage levels
US8630821B2 (en) * 2011-07-25 2014-01-14 Qualcomm Incorporated High speed data testing without high speed bit clock
WO2013060361A1 (en) * 2011-10-25 2013-05-02 Advantest (Singapore) Pte. Ltd. Automatic test equipment
US8996928B2 (en) * 2012-04-17 2015-03-31 Qualcomm Incorporated Devices for indicating a physical layer error
US8995514B1 (en) * 2012-09-28 2015-03-31 Xilinx, Inc. Methods of and circuits for analyzing a phase of a clock signal for receiving data
US8918682B2 (en) * 2012-11-14 2014-12-23 Altera Corporation Methods for testing network circuitry
US9071477B2 (en) * 2013-10-09 2015-06-30 Global Unichip Corporation Method and associated processing module for interconnection system
US20150358839A1 (en) * 2014-06-10 2015-12-10 Litepoint Corporation Method and system for testing a radio frequency data packet signal transceiver at a low network media layer
US9804991B2 (en) * 2015-03-03 2017-10-31 Qualcomm Incorporated High-frequency signal observations in electronic systems
US9590774B1 (en) 2015-09-25 2017-03-07 Microsoft Technology Licensing, Llc Circuit for introducing signal jitter
JP6086639B1 (ja) * 2016-05-12 2017-03-01 株式会社セレブレクス データ受信装置
US9929856B1 (en) * 2016-11-07 2018-03-27 Dell Products, Lp System and method for jitter negation in a high speed serial interface
KR102629185B1 (ko) * 2016-12-07 2024-01-24 에스케이하이닉스 주식회사 데이터 통신을 위한 수신기
US10892966B2 (en) * 2018-06-01 2021-01-12 Apple Inc. Monitoring interconnect failures over time
US11940483B2 (en) * 2019-01-31 2024-03-26 Tektronix, Inc. Systems, methods and devices for high-speed input/output margin testing
TWI762828B (zh) * 2019-11-01 2022-05-01 緯穎科技服務股份有限公司 高速序列電腦匯流排的訊號調整方法及其相關電腦系統
CN111682979B (zh) * 2020-05-28 2021-12-07 杭州迪普科技股份有限公司 高速信号测试板生成方法及装置
US12061232B2 (en) 2020-09-21 2024-08-13 Tektronix, Inc. Margin test data tagging and predictive expected margins
CN116802510A (zh) 2020-11-24 2023-09-22 特克特朗尼克公司 用于高速输入/输出裕量测试的系统、方法和设备
US11843376B2 (en) 2021-05-12 2023-12-12 Gowin Semiconductor Corporation Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA)
US11474969B1 (en) * 2021-05-12 2022-10-18 Gowin Semiconductor Corporation Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
CN115237094B (zh) * 2022-07-19 2025-09-16 超聚变数字技术有限公司 一种测试装置和测试设备
CN115396353B (zh) * 2022-08-31 2024-08-27 深圳市国芯物联科技有限公司 一种高速串行芯片误码率测试系统及方法
CN116318155B (zh) * 2023-05-19 2023-08-11 武汉普赛斯电子股份有限公司 一种精密时基等效采样装置及方法

Family Cites Families (68)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7663502B2 (en) * 1992-05-05 2010-02-16 Intelligent Technologies International, Inc. Asset system control arrangement and method
DE3481472D1 (de) * 1984-12-21 1990-04-05 Ibm Digitale phasenregelschleife.
US5349587A (en) * 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
JP3030598B2 (ja) * 1994-06-24 2000-04-10 アンリツ株式会社 ジッタ検出装置
US5606567A (en) * 1994-10-21 1997-02-25 Lucent Technologies Inc. Delay testing of high-performance digital components by a slow-speed tester
US5517147A (en) * 1994-11-17 1996-05-14 Unisys Corporation Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
US5835501A (en) * 1996-03-04 1998-11-10 Pmc-Sierra Ltd. Built-in test scheme for a jitter tolerance test of a clock and data recovery unit
US6519723B1 (en) * 1996-09-27 2003-02-11 Applied Digital Access, Inc. Firewall performance monitoring and limited access system
US6008703A (en) * 1997-01-31 1999-12-28 Massachusetts Institute Of Technology Digital compensation for wideband modulation of a phase locked loop frequency synthesizer
US6076175A (en) * 1997-03-31 2000-06-13 Sun Microsystems, Inc. Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
JPH1138100A (ja) * 1997-07-18 1999-02-12 Advantest Corp 半導体試験装置
AU2488299A (en) * 1998-01-30 1999-08-16 Wavecrest Corporation Method and apparatus for jitter analysis
US6057679A (en) * 1998-06-12 2000-05-02 Credence Systems Corporation Integrated circuit tester having amorphous logic for real-time data analysis
US6181267B1 (en) * 1998-09-30 2001-01-30 Agilent Technologies Inc. Internally triggered equivalent-time sampling system for signals having a predetermined data rate
DE69801827T2 (de) * 1998-11-14 2002-03-28 Agilent Technologies, Inc. (N.D.Ges.D.Staates Delaware) Taktgenerator
JP2000244309A (ja) * 1999-02-18 2000-09-08 Mitsubishi Electric Corp クロック生成回路および半導体装置
JP4146965B2 (ja) * 1999-05-17 2008-09-10 株式会社アドバンテスト 遅延信号生成装置および半導体試験装置
US6091671A (en) * 1999-07-14 2000-07-18 Guide Technology, Inc. Time interval analyzer having interpolator with constant current capacitor control
US6374388B1 (en) * 1999-09-10 2002-04-16 Agilent Technologies, Inc. Equivalent time capture scheme for bit patterns within high data rate signals
US6640193B2 (en) * 1999-12-15 2003-10-28 Texas Instruments Incorporated Method and system for measuring jitter
US6629274B1 (en) * 1999-12-21 2003-09-30 Intel Corporation Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer
US6834367B2 (en) * 1999-12-22 2004-12-21 International Business Machines Corporation Built-in self test system and method for high speed clock and data recovery circuit
US6329850B1 (en) * 1999-12-27 2001-12-11 Texas Instruments Incorporated Precision frequency and phase synthesis
US6816987B1 (en) * 2000-03-25 2004-11-09 Broadcom Corporation Apparatus and method for built-in self-test of a data communications system
US6931579B2 (en) * 2000-04-28 2005-08-16 Mcgill University Integrated excitation/extraction system for test and measurement
JP2001339282A (ja) * 2000-05-30 2001-12-07 Advantest Corp 可変遅延回路及び半導体回路試験装置
JP2002076855A (ja) * 2000-08-29 2002-03-15 Advantest Corp 遅延回路、試験装置、コンデンサ
JP4310036B2 (ja) * 2000-09-07 2009-08-05 株式会社アドバンテスト タイミング信号発生回路、及び、それを備えた半導体検査装置
GB0026614D0 (en) * 2000-10-31 2000-12-13 Lsi Logic Europ Ltd A method and apparatus for estimation of error in data recovery schemes
GB2369940B (en) * 2000-12-09 2004-10-20 Mitel Corp Multiple input phase lock loop with hitless reference switching
US6658363B2 (en) * 2001-01-18 2003-12-02 Hewlett-Packard Development Company, L.P. Digital data pattern detection methods and arrangements
US6763489B2 (en) * 2001-02-02 2004-07-13 Logicvision, Inc. Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description
WO2002065690A1 (fr) * 2001-02-14 2002-08-22 Thine Electronics, Inc. Circuit integre a semi-conducteurs
EP1162739B1 (en) * 2001-04-03 2003-03-05 Agilent Technologies, Inc. (a Delaware corporation) Filter injecting data dependent jitter and level noise
KR100374648B1 (ko) * 2001-06-28 2003-03-03 삼성전자주식회사 전자파를 감소시키기 위한 위상동기루프회로 및 그의제어방법
US7016445B2 (en) * 2001-08-02 2006-03-21 Texas Instruments Incorporated Apparatus for and method of clock recovery from a serial data stream
US6816988B2 (en) * 2001-08-31 2004-11-09 Agilent Technologies, Inc. Method and system for minimal-time bit-error-rate testing
US7116851B2 (en) * 2001-10-09 2006-10-03 Infinera Corporation Optical signal receiver, an associated photonic integrated circuit (RxPIC), and method improving performance
US7295783B2 (en) * 2001-10-09 2007-11-13 Infinera Corporation Digital optical network architecture
JP3869699B2 (ja) * 2001-10-24 2007-01-17 株式会社アドバンテスト タイミング発生器、半導体試験装置、及びタイミング発生方法
US6785622B2 (en) * 2001-10-29 2004-08-31 Agilent Technologies, Inc. Method and apparatus for performing eye diagram measurements
US6865496B2 (en) * 2001-11-01 2005-03-08 Agilent Technologies, Inc. Zero-crossing direction and time interval jitter measurement apparatus using offset sampling
JP4320139B2 (ja) * 2001-11-13 2009-08-26 株式会社アドバンテスト タイミング発生装置、及び試験装置
US6868047B2 (en) * 2001-12-12 2005-03-15 Teradyne, Inc. Compact ATE with time stamp system
US6934896B2 (en) * 2001-12-31 2005-08-23 Advantest Corp. Time shift circuit for functional and AC parametric test
US7426220B2 (en) * 2002-01-09 2008-09-16 L-3 Communications Corporation Method and apparatus for aligning the clock signals of transceivers in a multiple access communication system utilizing programmable, multi-tap phase-locked loops
ITMI20020459A1 (it) * 2002-03-06 2003-09-08 St Microelectronics Srl Randomizzatore per convertirore di tipo sigms delta
US6775809B1 (en) * 2002-03-14 2004-08-10 Rambus Inc. Technique for determining performance characteristics of electronic systems
KR100459709B1 (ko) * 2002-04-03 2004-12-04 삼성전자주식회사 여유 있는 셋업 앤드 홀드 타임 마진을 가지는 병렬-직렬송신 회로
US6650101B2 (en) * 2002-04-08 2003-11-18 Agilent Technologies, Inc. Timebase for sampling an input signal having a synchronous trigger
US6918073B2 (en) * 2002-04-12 2005-07-12 Agilent Technologies, Inc. Differential self-test of input/output circuits
US20030198311A1 (en) * 2002-04-19 2003-10-23 Wireless Interface Technologies, Inc. Fractional-N frequency synthesizer and method
JP3559785B2 (ja) * 2002-06-17 2004-09-02 Ｎｅｃエレクトロニクス株式会社 Ｐｌｌ回路及び位相差検出回路
US7136772B2 (en) * 2002-11-08 2006-11-14 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Monitoring system for a communications network
US6909316B2 (en) * 2003-02-21 2005-06-21 Agilent Technologies, Inc. Variable delay circuit with high resolution
US6909980B2 (en) * 2003-03-13 2005-06-21 Agilent Technologies, Inc. Auto skew alignment of high-speed differential eye diagrams
US6768390B1 (en) * 2003-04-02 2004-07-27 Agilent Technologies, Inc. System and method for generating balanced modulated signals with arbitrary amplitude and phase control using modulation
US7627790B2 (en) * 2003-08-21 2009-12-01 Credence Systems Corporation Apparatus for jitter testing an IC
US7158899B2 (en) * 2003-09-25 2007-01-02 Logicvision, Inc. Circuit and method for measuring jitter of high speed signals
US7403486B2 (en) * 2003-10-31 2008-07-22 Acterna Signal level measurement and data connection quality analysis apparatus and methods
US20060139387A1 (en) * 2004-05-27 2006-06-29 Silverbrook Research Pty Ltd Printer controller for providing data and command via communication output
JP4425735B2 (ja) * 2004-07-22 2010-03-03 株式会社アドバンテスト ジッタ印加回路、及び試験装置
EP1653650B1 (en) * 2004-10-27 2007-08-08 Agilent Technologies, Inc. Source synchronous sampling
US7526033B2 (en) * 2005-02-04 2009-04-28 Agere Systems Inc. Serializer deserializer (SERDES) testing
US7545396B2 (en) * 2005-06-16 2009-06-09 Aurora Systems, Inc. Asynchronous display driving scheme and display
US7627003B1 (en) * 2005-09-30 2009-12-01 The United States Of America As Represented By The Secretary Of The Navy Automatic clock synchronization and distribution circuit for counter clock flow pipelined systems
US7681091B2 (en) * 2006-07-14 2010-03-16 Dft Microsystems, Inc. Signal integrity measurement systems and methods using a predominantly digital time-base generator
US7813297B2 (en) * 2006-07-14 2010-10-12 Dft Microsystems, Inc. High-speed signal testing system having oscilloscope functionality

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022524715A (ja) * 2019-01-31 2022-05-10 テクトロニクス・インコーポレイテッド 高速入出力マージン試験のためのシステム、方法及び装置
JP7728174B2 (ja) 2019-01-31 2025-08-22 テクトロニクス・インコーポレイテッド 試験装置、電気的マージン試験方法及びマージン・テスタ

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WO2008098202A2 (en) 2008-08-14
TW200935781A (en) 2009-08-16
EP2115940A2 (en) 2009-11-11
US20080192814A1 (en) 2008-08-14

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