JP4425735B2 - ジッタ印加回路、及び試験装置 - Google Patents
ジッタ印加回路、及び試験装置 Download PDFInfo
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- JP4425735B2 JP4425735B2 JP2004214888A JP2004214888A JP4425735B2 JP 4425735 B2 JP4425735 B2 JP 4425735B2 JP 2004214888 A JP2004214888 A JP 2004214888A JP 2004214888 A JP2004214888 A JP 2004214888A JP 4425735 B2 JP4425735 B2 JP 4425735B2
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- Prior art keywords
- jitter
- frequency
- phase
- circuit
- low
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- 238000012360 testing method Methods 0.000 title claims description 36
- 238000002347 injection Methods 0.000 title claims description 32
- 239000007924 injection Substances 0.000 title claims description 32
- 230000010355 oscillation Effects 0.000 claims description 36
- 239000000284 extract Substances 0.000 claims description 6
- 229920005994 diacetyl cellulose Polymers 0.000 description 25
- 238000010586 diagram Methods 0.000 description 10
- 230000001934 delay Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31727—Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Tests Of Electronic Circuits (AREA)
Description
Claims (7)
- 与えられるジッタデータに応じた位相ジッタ成分を含むクロック信号を生成するジッタ印加回路であって、
与えられる基準信号に応じて発振信号を生成するPLL回路と、
前記発振信号を遅延させた前記クロック信号を出力する可変遅延回路と、
前記ジッタデータの低周波成分に基づいて前記PLL回路の発振周波数を制御し、前記発振信号に前記位相ジッタ成分の低周波成分を印加する低周波印加部と、
前記ジッタデータの高周波成分に基づいて前記可変遅延回路における遅延量を制御し、前記クロック信号に前記位相ジッタ成分の高周波成分を印加する高周波印加部と
を備えるジッタ印加回路。 - 前記PLL回路は、
与えられる制御電圧に応じた周波数を有する前記発振信号を生成する電圧制御発振器と、
与えられる基準信号の位相と、前記発振信号の位相との比較結果に基づいた前記制御電圧を生成する位相比較器と、
前記制御電圧の高周波成分を除去して前記電圧制御発振器に与えるローパスフィルタと
を有し、
前記低周波印加部は、前記位相比較器が生成した前記制御電圧に前記ジッタデータに応じた電圧を重畳して前記ローパスフィルタに入力する
請求項1に記載のジッタ印加回路。 - 前記高周波印加部は、前記ジッタデータの高周波成分を抽出するハイパスフィルタを有する請求項1に記載のジッタ印加回路。
- 前記低周波印加部は、前記ジッタデータの低周波成分を抽出するローパスフィルタを有する請求項3に記載のジッタ印加回路。
- 前記ジッタデータは複数ビットのデジタルデータであって、
前記高周波印加部は、前記ジッタデータの所定の桁数の下位ビットに基づいて前記可変遅延回路における遅延量を制御し、
前記低周波印加部は、前記ジッタデータの所定の桁数の上位ビットに基づいて前記PLL回路の発振周波数を制御する
請求項1に記載のジッタ印加回路。 - 前記PLL回路は、
与えられる制御電圧に応じた周波数を有する前記発振信号を生成し、前記可変遅延回路に入力する電圧制御発振器と、
与えられる基準信号の位相と、前記可変遅延回路が出力する前記クロック信号の位相との比較結果に基づいた前記制御電圧を生成する位相比較器と、
前記制御電圧の高周波成分を除去して前記電圧制御発振器に与えるローパスフィルタと
を有する
請求項1に記載のジッタ印加回路。 - 電子デバイスのジッタ耐力を試験する試験装置であって、
前記電子デバイスを試験するための試験パターンを生成するパターン発生器と、
与えられるジッタデータに応じた位相ジッタ成分を含むクロック信号を生成するタイミング発生器と、
前記試験パターンに基づく試験信号を、前記クロック信号に応じたタイミングで前記電子デバイスに入力する波形成形器と、
前記試験信号に応じて前記電子デバイスが出力する出力信号に応じて、前記電子デバイスのジッタ耐力を判定する判定部と
を備え、
前記タイミング発生器は、
与えられる基準信号に応じて発振信号を生成するPLL回路と、
前記発振信号を遅延させた前記クロック信号を出力する可変遅延回路と、
前記ジッタデータの低周波成分に基づいて前記PLL回路の発振周波数を制御し、前記発振信号に前記位相ジッタ成分の低周波成分を印加する低周波印加部と、
前記ジッタデータの高周波成分に基づいて前記可変遅延回路における遅延量を制御し、前記クロック信号に前記位相ジッタ成分の高周波成分を印加する高周波印加部と
を有する試験装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004214888A JP4425735B2 (ja) | 2004-07-22 | 2004-07-22 | ジッタ印加回路、及び試験装置 |
PCT/JP2005/011589 WO2006008908A1 (ja) | 2004-07-22 | 2005-06-24 | ジッタ印加回路、及び試験装置 |
KR1020077003628A KR20070043843A (ko) | 2004-07-22 | 2005-06-24 | 지터 인가 회로, 및 시험 장치 |
DE112005001762T DE112005001762T5 (de) | 2004-07-22 | 2005-06-24 | Jittereinfügungsschaltung und Prüfvorrichtung |
TW094122051A TWI353115B (en) | 2004-07-22 | 2005-06-30 | Circuit for applying jitter and test device |
US11/178,226 US7287200B2 (en) | 2004-07-22 | 2005-07-08 | Jitter applying circuit and test apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004214888A JP4425735B2 (ja) | 2004-07-22 | 2004-07-22 | ジッタ印加回路、及び試験装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006041640A JP2006041640A (ja) | 2006-02-09 |
JP4425735B2 true JP4425735B2 (ja) | 2010-03-03 |
Family
ID=35785031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004214888A Expired - Fee Related JP4425735B2 (ja) | 2004-07-22 | 2004-07-22 | ジッタ印加回路、及び試験装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7287200B2 (ja) |
JP (1) | JP4425735B2 (ja) |
KR (1) | KR20070043843A (ja) |
DE (1) | DE112005001762T5 (ja) |
TW (1) | TWI353115B (ja) |
WO (1) | WO2006008908A1 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI277748B (en) * | 2005-08-29 | 2007-04-01 | Via Tech Inc | Time jitter injection testing circuit and related testing method |
JP4508072B2 (ja) * | 2005-10-18 | 2010-07-21 | 株式会社デンソー | シリアル通信回路及びa/d変換システム |
US8327204B2 (en) * | 2005-10-27 | 2012-12-04 | Dft Microsystems, Inc. | High-speed transceiver tester incorporating jitter injection |
US7394277B2 (en) * | 2006-04-20 | 2008-07-01 | Advantest Corporation | Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method |
US7813297B2 (en) * | 2006-07-14 | 2010-10-12 | Dft Microsystems, Inc. | High-speed signal testing system having oscilloscope functionality |
US7681091B2 (en) * | 2006-07-14 | 2010-03-16 | Dft Microsystems, Inc. | Signal integrity measurement systems and methods using a predominantly digital time-base generator |
US7835479B2 (en) | 2006-10-16 | 2010-11-16 | Advantest Corporation | Jitter injection apparatus, jitter injection method, testing apparatus, and communication chip |
US20080192814A1 (en) * | 2007-02-09 | 2008-08-14 | Dft Microsystems, Inc. | System and Method for Physical-Layer Testing of High-Speed Serial Links in their Mission Environments |
JPWO2008133238A1 (ja) * | 2007-04-24 | 2010-07-29 | 株式会社アドバンテスト | 試験装置および試験方法 |
US20090158100A1 (en) * | 2007-12-13 | 2009-06-18 | Advantest Corporation | Jitter applying circuit and test apparatus |
US7808252B2 (en) * | 2007-12-13 | 2010-10-05 | Advantest Corporation | Measurement apparatus and measurement method |
KR100960118B1 (ko) * | 2007-12-17 | 2010-05-27 | 한국전자통신연구원 | 클럭 지터 발생 장치 및 이를 포함하는 시험 장치 |
US7917319B2 (en) * | 2008-02-06 | 2011-03-29 | Dft Microsystems Inc. | Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits |
US8207765B2 (en) | 2009-07-20 | 2012-06-26 | Advantest Corporation | Signal generation apparatus and test apparatus |
US8683254B2 (en) | 2011-01-07 | 2014-03-25 | Anue Systems, Inc. | Systems and methods for precise event timing measurements |
US8533518B2 (en) | 2011-01-07 | 2013-09-10 | Anue Systems, Inc. | Systems and methods for precise timing measurements using high-speed deserializers |
US8788867B2 (en) | 2011-01-07 | 2014-07-22 | Anue Systems, Inc. | Systems and methods for playback of detected timing events |
US8850259B2 (en) | 2011-01-07 | 2014-09-30 | Anue Systems, Inc. | Systems and methods for precise generation of phase variation in digital signals |
TWI444636B (zh) * | 2011-02-18 | 2014-07-11 | Realtek Semiconductor Corp | 內建抖動測試功能之時脈與資料回復電路及其方法 |
DE102020102773B4 (de) | 2019-02-04 | 2023-11-02 | Tektronix, Inc. | Jitter-einfügungssystem zur wellenformerzeugung |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02252316A (ja) * | 1989-03-27 | 1990-10-11 | Nec Corp | ジッタシミュレーション機能付きpll回路 |
JPH06104708A (ja) * | 1992-09-21 | 1994-04-15 | Advantest Corp | ジッタ発生装置 |
JPH06112785A (ja) * | 1992-09-28 | 1994-04-22 | Advantest Corp | ジッタ発生装置 |
US6686879B2 (en) * | 1998-02-12 | 2004-02-03 | Genghiscomm, Llc | Method and apparatus for transmitting and receiving signals having a carrier interferometry architecture |
JP4445114B2 (ja) * | 2000-01-31 | 2010-04-07 | 株式会社アドバンテスト | ジッタ測定装置及びその方法 |
JP2002124873A (ja) * | 2000-10-18 | 2002-04-26 | Mitsubishi Electric Corp | 半導体装置 |
JP3830020B2 (ja) * | 2000-10-30 | 2006-10-04 | 株式会社日立製作所 | 半導体集積回路装置 |
US6993107B2 (en) * | 2001-01-16 | 2006-01-31 | International Business Machines Corporation | Analog unidirectional serial link architecture |
US20030231707A1 (en) * | 2002-06-05 | 2003-12-18 | French John Sargent | Method and apparatus for jitter creation and testing |
-
2004
- 2004-07-22 JP JP2004214888A patent/JP4425735B2/ja not_active Expired - Fee Related
-
2005
- 2005-06-24 WO PCT/JP2005/011589 patent/WO2006008908A1/ja active Application Filing
- 2005-06-24 KR KR1020077003628A patent/KR20070043843A/ko not_active Application Discontinuation
- 2005-06-24 DE DE112005001762T patent/DE112005001762T5/de not_active Withdrawn
- 2005-06-30 TW TW094122051A patent/TWI353115B/zh active
- 2005-07-08 US US11/178,226 patent/US7287200B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TW200605512A (en) | 2006-02-01 |
US7287200B2 (en) | 2007-10-23 |
WO2006008908A1 (ja) | 2006-01-26 |
TWI353115B (en) | 2011-11-21 |
KR20070043843A (ko) | 2007-04-25 |
US20060041797A1 (en) | 2006-02-23 |
DE112005001762T5 (de) | 2007-06-21 |
JP2006041640A (ja) | 2006-02-09 |
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