JP2010206100A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2010206100A JP2010206100A JP2009052476A JP2009052476A JP2010206100A JP 2010206100 A JP2010206100 A JP 2010206100A JP 2009052476 A JP2009052476 A JP 2009052476A JP 2009052476 A JP2009052476 A JP 2009052476A JP 2010206100 A JP2010206100 A JP 2010206100A
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Abstract
【解決手段】主たるトランジスタとして接合FET10を備え、制御用トランジスタとしてMISFET20を備えた半導体装置であって、接合FET10は第1ゲート電極G1、第1ソース電極S1、および、第1ドレイン電極D1を有し、MISFET20は第2ゲート電極G2、第2ソース電極S2、および、第2ドレイン電極D2を有する。また、MISFET20はnチャネル型であり、エンハンスメント型の電気特性を有する。また、MISFET20の第2ゲート電極G2と第2ドレイン電極D2とは短絡接続され、接合FET10の第1ゲート電極G1とMISFET20の第2ソース電極S2とは短絡接続されている。
【選択図】図1
Description
図1には、本実施の形態1の半導体装置を説明するための回路図を示している。本実施の形態1の半導体装置は、接合FET10を主たるトランジスタとして有している。接合FET10は、そのゲート電極である第1ゲート電極G1、ソース電極である第1ソース電極S1、ドレイン電極である第1ドレイン電極D1を有している。なお、本実施の形態1の接合FET10はnチャネル型であり、チャネルとなるドリフト層はn型半導体、ドリフト層に空乏層を生じさせるためのゲート層はp型半導体、ソース・ドレイン層はn型半導体によって構成されている。また、本実施の形態1の接合FET10は母体材料としてSiCを用いて形成されている。
本実施の形態2の半導体装置は、上記実施の形態1の半導体装置と同様に、上記図1の回路図を用いて説明したような接合FET10とMISFET20とからなる複合半導体素子を有している。
本実施の形態3では、上記実施の形態1で説明した、接合FET10およびMISFET20からなる半導体素子を適用して有効な半導体装置について説明する。本実施の形態3の半導体装置の回路図を図20に示す。本実施の形態3の半導体装置では、独立な二つの個別半導体素子からなる接合FET10およびMISFET20を、構成要素として有している。即ち、接合FET10とMISFET20とは、異なるパッケージによって構成されている。そして、接合FET10およびMISFET20などの半導体素子の端子を、同一の回路ボード(またはプリント基板)60上に配置し、回路ボード60上の配線により接続させて構成されている。
本実施の形態4では、上記実施の形態1で説明した、接合FET10およびMISFET20からなる半導体素子を適用して有効な、他の半導体装置について説明する。本実施の形態4の半導体装置の回路図を図21に示す。図21に示すのは、単相インバータ(あるいは3相インバータの1相分)を示した回路図である。以下、単にインバータINVと記す。
10a 第1接合FET
10b 第2接合FET
11 半導体基板
11a 第1半導体基板
11b 第2半導体基板
12 n型ドリフト層
13 分離部
14 p型ゲート層
15 第1n型ソース層
20 MISFET
20a 第1MISFET
20b 第2MISFET
21 p型ウェル層
22 ゲート絶縁膜
23 ゲート電極
24 サイドウォールスペーサ
25 第2n型ソース層
26 第2n型ドレイン層
27 チャネル層
30〜32,30a,30b ダイオード
31a 第1フライホイールダイオード(第1ダイオード)
31b 第2フライホイールダイオード(第1ダイオード)
33 コンデンサ
34 コイル
35 ゲート駆動回路
35a 第1ゲート駆動回路
35b 第2ゲート駆動回路
36a 高圧側の主配線
36b 低圧側の主配線
36c,36d,36e,36f,36g 配線
60 回路ボード(プリント基板)
70 放熱基板
71S ソース端子電極
72D ドレイン端子電極
73G ゲート端子電極
74 中間端子電極
75a,75b,75c,75d 金属ワイヤ
81〜84,91,92 酸化シリコン膜
90 トレンチ
93 フォトレジスト膜
A1 上アーム
A2 下アーム
D1,D1a,D1b 第1ドレイン電極
D2,D2a,D2b 第2ドレイン電極
G1,G1a,G1b 第1ゲート電極
G2,G2a,G2b 第2ゲート電極
ID1S1 第1ドレインソース電流
ID2S1 素子ゲートソース電流
ID2S2 第2ドレインソース電流
IG1S1 第1ゲートソース電流
INV インバータ
M1 裏面電極
M2 第1表面電極
M3 第2表面電極
M4 第3表面電極
MA 表面電極膜
S1,S1a,S2b 第1ソース電極
S2,S2a,S2b 第2ソース電極
sw スイッチング素子
UC 昇圧回路
VD2S1 素子ゲートソース間電圧
VD2S2 第2ドレインソース間電圧
VG1S1 第1ゲートソース間電圧
Claims (13)
- 接合FETを主たるトランジスタとし、MISFETを制御用トランジスタとして有する半導体装置であって、
前記接合FETは、第1ゲート電極、第1ソース電極、および、第1ドレイン電極を有し、
前記MISFETは、第2ゲート電極、第2ソース電極、および、第2ドレイン電極を有し、
前記MISFETはnチャネル型であり、かつ、エンハンスメント型の電気特性を有し、
前記MISFETの前記第2ゲート電極と前記第2ドレイン電極とは短絡接続され、
前記接合FETの前記第1ゲート電極と、前記MISFETの前記第2ソース電極とは短絡接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記接合FETと前記MISFETとは、同一の半導体基板に配置され、
前記接合FETは、前記半導体基板において、
(a1)n型ドリフト層と、
(a2)前記n型ドリフト層に形成された第1n型ソース層と、
(a3)前記n型ドリフト層に形成され、前記第1n型ソース層に電気的に接続するp型ゲート層とを有し、
前記MISFETは、前記半導体基板において、
(b1)前記n型ドリフト層に形成されたp型ウェル層と、
(b2)前記p型ウェル層上にゲート絶縁膜を介して形成されたゲート電極と、
(b3)前記ゲート電極の側方下部の前記p型ウェル層に形成された、第2n型ソース層および第2n型ドレイン層とを有し、
前記p型ゲート層と前記第2n型ソース層とは、接合部を有するようにして形成され、
前記p型ゲート層と前記p型ウェル層とは、接合部を有するようにして形成され、
前記第1ソース電極は前記第1n型ソース層に電気的に接続するようにして形成され、
前記第1ドレイン電極は前記半導体基板に電気的に接続するようにして形成され、
前記第1ゲート電極および前記第2ソース電極は一体的であり、かつ、前記p型ゲート層および前記第2n型ソース層に対して電気的に接続するようにして形成され、
前記第2ゲート電極および前記第2ドレイン電極は一体的であり、かつ、前記ゲート電極および前記第2n型ドレイン層に対して電気的に接続するようにして形成されていることを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記半導体基板は、SiCを主体とする半導体材料であることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記接合FETは第1半導体基板に配置され、
前記MISFETは第2半導体基板に配置され、
前記第1半導体基板と前記第2半導体基板とは同一パッケージに封止されていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記接合FETは、前記第1半導体基板において、
(a1)n型ドリフト層と、
(a2)前記n型ドリフト層に形成された第1n型ソース層と、
(a3)前記n型ドリフト層に形成され、前記第1n型ソース層に電気的に接続するp型ゲート層とを有し、
前記MISFETは、前記第2半導体基板において、
(b1)p型ウェル層と、
(b2)前記p型ウェル層上にゲート絶縁膜を介して形成されたゲート電極と、
(b3)前記ゲート電極の側方下部の前記p型ウェル層に形成された、第2n型ソース層および第2n型ドレイン層とを有することを特徴とする半導体装置。 - 請求項5記載の半導体装置において、
前記第1半導体基板は、SiCを主体とする半導体材料であることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1半導体基板と前記第2半導体基板とは、同一の放熱基板上に配置され、
前記放熱基板上には、前記パッケージの外部に電気的に接続できるような、ソース端子電極、ドレイン端子電極、および、ゲート端子電極が配置され、
前記放熱基板上には、中間端子電極が配置され、
前記第1ソース電極は、前記第1n型ソース層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ゲート電極は、前記p型ゲート層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ドレイン電極は、前記第1半導体基板に電気的に接続するようにして、前記第1半導体基板の下面に形成され、
前記第2ソース電極は、前記第2n型ソース層に電気的に接続するようにして、前記第2半導体基板の上面および下面の2箇所に形成され、
前記第2ゲート電極は、前記ゲート電極に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第2ドレイン電極は、前記第2n型ドレイン層に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第1半導体基板の下面の前記第1ドレイン電極と前記ドレイン端子電極とは、半田により電気的に接合され、
前記第2半導体基板の下面の前記第2ソース電極と前記中間端子電極とは、前記半田により電気的に接合され、
前記第1ソース電極と前記ソース端子電極とは、金属ワイヤによって電気的に接続され、
前記第1ゲート電極と前記第2ソース電極および前記中間端子電極とは、前記金属ワイヤによって電気的に接続され、
前記第2ゲート電極および前記第2ドレイン電極と前記ゲート端子電極とは、前記金属ワイヤによって電気的に接続されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1半導体基板と前記第2半導体基板とは、同一の放熱基板上に配置され、
前記放熱基板上には、前記パッケージの外部に電気的に接続できるような、ソース端子電極、ドレイン端子電極、および、ゲート端子電極が配置され、
前記放熱基板上には、中間端子電極が配置され、
前記第1ソース電極は、前記第1n型ソース層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ゲート電極は、前記p型ゲート層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ドレイン電極は、前記第1半導体基板に電気的に接続するようにして、前記第1半導体基板の下面に形成され、
前記第2ソース電極は、前記第2n型ソース層に電気的に接続するようにして、前記第2半導体基板の下面に形成され、
前記第2ゲート電極は、前記ゲート電極に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第2ドレイン電極は、前記第2n型ドレイン層に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第1半導体基板の下面の前記第1ドレイン電極と前記ドレイン端子電極とは、半田により電気的に接合され、
前記第2半導体基板の下面の前記第1ソース電極と前記中間端子電極とは、前記半田により電気的に接合され、
前記第1ソース電極と前記ソース端子電極とは、金属ワイヤによって電気的に接続され、
前記第1ゲート電極と前記中間端子電極とは、前記金属ワイヤによって電気的に接続され、
前記第2ゲート電極および前記第2ドレイン電極と前記ゲート端子電極とは、前記金属ワイヤによって電気的に接続されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第1半導体基板と前記第2半導体基板とは、同一の放熱基板上に配置され、
前記放熱基板上には、前記パッケージの外部に電気的に接続できるような、ソース端子電極、ドレイン端子電極、および、ゲート端子電極が配置され、
前記第1ソース電極は、前記第1n型ソース層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ゲート電極は、前記p型ゲート層に電気的に接続するようにして、前記第1半導体基板の上面に形成され、
前記第1ドレイン電極は、前記第1半導体基板に電気的に接続するようにして、前記第1半導体基板の下面に形成され、
前記第2ソース電極は、前記第2n型ソース層に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第2ゲート電極は、前記ゲート電極に電気的に接続するようにして、前記第2半導体基板の上面に形成され、
前記第2ドレイン電極は、前記第2n型ドレイン層に電気的に接続するようにして、前記第2半導体基板の下面に形成され、
前記第1半導体基板の下面の前記第1ドレイン電極と前記ドレイン端子電極とは、半田により電気的に接合され、
前記第2半導体基板の下面の前記第2ドレイン電極と前記ゲート端子電極とは、前記半田により接合され、
前記第1ソース電極と前記ソース端子電極とは、金属ワイヤによって電気的に接続され、
前記第1ゲート電極と前記第2ソース電極とは、前記金属ワイヤによって電気的に接続され、
前記第2ゲート電極と前記ゲート端子電極とは、前記金属ワイヤによって電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記接合FETと前記MISFETとは、異なるパッケージによって構成され、同一のプリント基板状に配置されていることを特徴とする半導体装置。 - 昇圧回路を有する半導体装置であって、
前記昇圧回路はスイッチング素子を有し、
前記スイッチング素子は、主たるトランジスタである接合FETと、制御用トランジスタであるMISFETとにより構成され、
前記接合FETは、第1ゲート電極、第1ソース電極、および、第1ドレイン電極を有し、
前記MISFETは、第2ゲート電極、第2ソース電極、および、第2ドレイン電極を有し、
前記MISFETはnチャネル型であり、かつ、エンハンスメント型の電気特性を有し、
前記MISFETの前記第2ゲート電極と前記第2ドレイン電極とは短絡接続され、
前記接合FETの前記第1ゲート電極と、前記MISFETの前記第2ソース電極とは短絡接続されていることを特徴とする半導体装置。 - インバータを有する半導体装置であって、
前記インバータは複数のスイッチング素子を有し、
前記複数のスイッチング素子は、主たるトランジスタである接合FETと、制御用トランジスタであるMISFETとにより構成され、
前記接合FETは、第1ゲート電極、第1ソース電極、および、第1ドレイン電極を有し、
前記MISFETは、第2ゲート電極、第2ソース電極、および、第2ドレイン電極を有し、
前記MISFETはnチャネル型であり、かつ、エンハンスメント型の電気特性を有し、
前記MISFETの前記第2ゲート電極と前記第2ドレイン電極とは短絡接続され、
前記接合FETの前記第1ゲート電極と、前記MISFETの前記第2ソース電極とは短絡接続されていることを特徴とする半導体装置。 - 請求項12記載の半導体装置において、
前記複数のスイッチング素子は、更に第1ダイオードを有し、
前記第1ダイオードは、前記接合FETと並列に接続されていることを特徴とする半導体装置。
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JP2013219306A (ja) * | 2012-04-12 | 2013-10-24 | Advanced Power Device Research Association | 半導体ダイオード装置 |
KR20180125404A (ko) * | 2017-05-15 | 2018-11-23 | 인피니언 테크놀로지스 아게 | 트랜지스터 셀 및 드리프트 구조체를 갖는 반도체 장치 및 제조 방법 |
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JP5844956B2 (ja) * | 2009-03-05 | 2016-01-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5492518B2 (ja) * | 2009-10-02 | 2014-05-14 | 株式会社日立製作所 | 半導体駆動回路、及びそれを用いた半導体装置 |
WO2011061918A1 (ja) * | 2009-11-17 | 2011-05-26 | パナソニック株式会社 | 半導体素子及びその製造方法 |
US9362905B2 (en) * | 2011-03-21 | 2016-06-07 | Infineon Technologies Americas Corp. | Composite semiconductor device with turn-on prevention control |
US9859882B2 (en) | 2011-03-21 | 2018-01-02 | Infineon Technologies Americas Corp. | High voltage composite semiconductor device with protection for a low voltage device |
JP5743739B2 (ja) | 2011-06-22 | 2015-07-01 | 株式会社東芝 | 蓄電装置 |
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JP6542174B2 (ja) * | 2016-09-21 | 2019-07-10 | 株式会社東芝 | 半導体装置及び半導体装置の制御方法 |
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