TWI634620B - 於共同基板上之功率裝置整合 - Google Patents

於共同基板上之功率裝置整合 Download PDF

Info

Publication number
TWI634620B
TWI634620B TW102127300A TW102127300A TWI634620B TW I634620 B TWI634620 B TW I634620B TW 102127300 A TW102127300 A TW 102127300A TW 102127300 A TW102127300 A TW 102127300A TW I634620 B TWI634620 B TW I634620B
Authority
TW
Taiwan
Prior art keywords
region
anode
cathode
active region
gate
Prior art date
Application number
TW102127300A
Other languages
English (en)
Other versions
TW201409610A (zh
Inventor
杰席克 寇瑞克
楊鉑儀
Original Assignee
新加坡商西拉娜亞洲私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/887,704 external-priority patent/US8994105B2/en
Application filed by 新加坡商西拉娜亞洲私人有限公司 filed Critical 新加坡商西拉娜亞洲私人有限公司
Publication of TW201409610A publication Critical patent/TW201409610A/zh
Application granted granted Critical
Publication of TWI634620B publication Critical patent/TWI634620B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0635—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors and diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42304—Base electrodes for bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7302—Bipolar junction transistors structurally associated with other devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/8605—Resistors with PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
    • H01L29/7821—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

本發明揭示一種半導體結構，其用於促進在一共同基板上整合功率裝置，該半導體結構包含：一第一絕緣層，其形成於該基板上；及一作用區域，其具有一第一導電類型且形成於該第一絕緣層之至少一部分上。一第一端子形成於該結構之一上部表面上，且與形成於該作用區域中之具有該第一導電類型之至少一個其他區域電連接。具有一第二導電類型之一經埋入井形成於該作用區域中且與形成於該結構之該上部表面上之一第二端子耦合。該經埋入井與該作用區域形成一箝位二極體，該箝位二極體將一突崩潰區域定位於該經埋入井與該第一端子之間。該等功率裝置中之至少一者之一崩潰電壓隨該經埋入井之特性而變。

Description

於共同基板上之功率裝置整合 相關申請案之交叉參考
此專利申請案係於2013年5月6日提出申請且標題為「Power Device Integration on a Common Substrate」之美國專利申請案序列號第13/887,704號之一部分接續案，且主張該美國專利申請案之權益，美國專利申請案序列號第13/887,704號又主張優先於2012年7月31日提出申請且標題為「Power Management Integrated Circuit for Portable Electronic Devices」之美國臨時專利申請案序列號第61/677,660號，該等申請案中之每一者之揭示內容皆出於各種目的以全文引用的方式併入本文中。
本發明大體而言係關於電子電路，且更特定而言係關於功率裝置整合。
包含但不限於智慧電話、膝上型電腦及平板電腦計算裝置、小筆電等之現代便攜式電子裝置係電池操控的，且通常需要用於穩定施加至裝置中之子系統之供應電壓之電力供應組件，諸如(舉例而言)微處理器、圖形顯示器、記憶體晶片等。所需功率範圍通常在約1瓦特(W)與約50W之間。
電力供應/管理組件通常被分割成若干功能塊；即控制電路、驅動級及功率切換器。自裝置小型化(此係諸多便攜式電子裝置之一所 期望目標)之觀點，將電力供應/管理組件整合至一單個積體電路(IC)晶片中係有利的。此解決方案在極低功率消耗產品中係尤其佔優勢的，其中供應電流限於數百毫安(mA)。圖1係圖解說明一例示性功率級之一方塊圖，該功率級包含功率管理控制電路102、一驅動級104以及功率切換器106及108，該等組件皆單片整合於一單個IC 100中。
通常，使用金屬-氧化物-半導體場效應電晶體(MOSFET)裝置來實施該等功率切換器。製造一MOSFET需要相對少的遮罩步驟(例如，少於約十個遮罩層級)，而IC中之控制電路與MOSFET裝置相比通常需要相對多個遮罩步驟(例如，約26至36個遮罩層級)。結果，將一大晶粒區分配至功率切換器導致一高生產成本，此係不期望的。
本發明之實施例提供用於促進將電路及/或組件(例如，驅動器及功率切換器)整合於與用於實施一功率控制裝置之對應控制電路相同的矽基板上之新穎半導體結構及技術。為達成此，本發明之實施例開發實施於具有介電質橫向隔離之絕緣體上矽(SOI)基板之一BiCMOS IC製作技術之特徵。
根據本發明之一實施例，用於促進在一共同基板上整合功率裝置之一半導體結構包含：一第一絕緣層，其形成於該基板上；及一作用區域，其具有一第一導電類型且形成於該第一絕緣層之至少一部分上。一第一端子形成於該半導體結構之一上部表面上，且與形成於該作用區域中之具有該第一導電類型之至少一個其他區域電連接。該半導體結構進一步包含：一經埋入井，其具有一第二導電類型且形成於該作用區域中，該經埋入井與形成於該半導體結構之上部表面上之一第二端子耦合。該經埋入井經組態以結合該作用區域形成一箝位二極體，該等功率裝置中之至少一者之一崩潰電壓隨該經埋入井之一或多個特性而變。該箝位二極體操作以將一突崩潰區域定位於該半導體結 構中在該經埋入井與該第一端子之間。
根據本發明之另一實施例，提供用於促進在一共同基板上整合功率裝置之一半導體結構，該等功率裝置中之至少一者包含一雙極型接面電晶體(BJT)。該半導體結構包含：一第一絕緣層，其形成於該基板上；一作用區域，其具有一第一導電類型且形成於該第一絕緣層之至少一部分上；及一第一區域，其具有該第一導電類型且形成於該作用區域中鄰近該作用區域之一上部表面。具有該第一導電類型之一集極區域形成於該第一區域之至少一部分中鄰近該第一區域之一上部表面，該集極區域與該第一區域相比具有一較高摻雜濃度。形成於該半導體結構之一上部表面上之一集極端子與該第一區域電連接。該半導體結構進一步包含：一經埋入井，其具有一第二導電類型且形成於該作用區域中。該經埋入井經組態以結合該作用區域形成一箝位二極體，該箝位二極體操作以將一突崩潰區域定位於該經埋入井與該集極端子之間，該BJT之一崩潰電壓隨該經埋入井之一或多個特性而變。具有該第二導電類型之一基極區域形成於該作用區域中在該經埋入井之至少一部分上且橫向於該第一區域延伸。具有該第一導電類型之一射極區域形成於該基極區域之一上部表面中，該射極區域與形成於該半導體結構之上部表面上之一射極端子連接。一基極結構形成於該半導體結構之上部表面上在該基極區域與該第一區域之間的一接面上方，該基極結構與該經埋入井電連接且一基極端子形成於該半導體結構之上部表面上。
根據本發明之另一實施例，用於促進在一共同基板上整合功率裝置之一半導體結構包含：一第一絕緣層，其形成於該基板上；一作用區域，其具有一第一導電類型且形成於該第一絕緣層之至少一部分上；一第一端子，其形成於該半導體結構之一上部表面上且與形成於該作用區域中之具有該第一導電類型之至少一個其他區域電連接；及 一經埋入井，其具有一第二導電類型且形成於該作用區域中。該經埋入井經組態以結合該作用區域形成一箝位二極體，該箝位二極體操作以將一突崩潰區域定位於該經埋入井與該第一端子之間，該等功率裝置中之至少一者之一崩潰電壓隨該經埋入井之一或多個特性而變。該半導體結構進一步包含：一閘極結構，其形成於該半導體結構之該上部表面上在該經埋入井之至少一部分上方且鄰近該作用區域之一上部表面。該閘極結構與該作用區域電隔離且與該經埋入井電連接。
根據本發明之另一實施例，將一或多個功率裝置整合於一共同基板上之一方法包含以下步驟：在該基板上形成一第一絕緣層；在該第一絕緣層之至少一部分上形成具有一第一導電類型之一作用層；穿過該作用層在該作用層中之至少第一作用區域與第二作用區域之間形成一橫向介電質隔離，該第一作用區域與該第二作用區域藉由該橫向介電質隔離而彼此電隔離；在至少該第一作用區域中鄰近該作用層與該第一絕緣層之間的一界面形成具有一第二導電類型之至少一個經埋入井；在該半導體結構之一上部表面上在該經埋入井之至少一部分上方且鄰近該第一作用區域之一上部表面形成一閘極結構，該閘極結構與該第一作用區域電隔離且與該經埋入井電連接；在該第一作用區域之至少一部分中鄰近該第一作用區域之該上部表面形成具有該第一導電類型之至少一第一區域，該第一區域具有高於該第一作用區域之一摻雜濃度，該閘極結構至少部分地重疊於介於該第一作用區域與該第一區域之間的一界面；及在該半導體結構之該上部表面上形成至少第一端子及第二端子，該第一端子與該經埋入井電連接，且該第二端子與該第一區域電連接；其中該經埋入井經組態以結合該第一作用區域形成一箝位二極體，該箝位二極體操作以將一突崩潰區域定位於該經埋入井與該第二端子之間，該等功率裝置中之至少一者之一崩潰電壓隨該經埋入井之一或多個特性而變。
根據結合附圖一起閱讀之以下本發明之詳細說明，本發明之實施例將變得易於理解。
100‧‧‧積體電路晶片
102‧‧‧控制電路/功率管理控制電路
104‧‧‧驅動級
106‧‧‧功率切換器
108‧‧‧功率切換器
200‧‧‧第一積體電路/第一(控制)積體電路
202‧‧‧離散積體電路裝置/功率切換積體電路
204‧‧‧離散積體電路裝置/功率切換積體電路
206‧‧‧互連件
218‧‧‧經高摻雜之源極區域
220‧‧‧汲極區域
300‧‧‧功率級
302‧‧‧功率管理控制電路
304‧‧‧第一積體電路/控制積體電路
306‧‧‧驅動級
308‧‧‧功率切換器/離散功率切換器
310‧‧‧功率切換器/離散功率切換器
312‧‧‧第二積體電路/功率塊
400‧‧‧橫向擴散金屬-氧化物-半導體電晶體
500‧‧‧橫向擴散金屬-氧化物-半導體電晶體
600‧‧‧橫向擴散金屬-氧化物-半導體電晶體/絕緣體上矽橫向擴散之金屬-氧化物-半導體裝置
602‧‧‧作用絕緣體上矽層
700‧‧‧橫向擴散金屬-氧化物-半導體電晶體/絕緣體上矽橫向擴散之金屬-氧化物-半導體裝置
702‧‧‧作用絕緣體上矽層
800‧‧‧結構/裝置/金屬-氧化物-半導體場效應半導體結構
801‧‧‧N型或P型基板/基板
802‧‧‧經埋入井
804‧‧‧作用層/N-作用層/主體區域/作用層
806‧‧‧溝渠/溝渠條帶/溝渠閘極條帶/閘極溝渠/溝渠閘極
808‧‧‧閘極氧化物/氧化物襯裡
810‧‧‧多晶矽閘極層/多晶矽材料/多晶矽填料/所沈積多晶矽材料
812‧‧‧頂部表面
814‧‧‧多晶金屬矽化物電極/多晶金屬矽化物電極之矽化物層/具有低電阻率之矽化物材料
816‧‧‧橫向隔離結構/深溝渠結構/橫向隔離溝渠/另一溝渠結構
818‧‧‧經埋入氧化物層
900‧‧‧N通道橫向擴散之金屬-氧化物-半導體電晶體/橫向擴散之金屬-氧化物-半導體電晶體/電晶體/橫向擴散之金屬-氧化物-半導體裝置/金屬-氧化物-半導體場效應半導體/N通道金屬-氧化物-半導體場效應半導體
902‧‧‧經埋入井/經埋入P+井/深井
904‧‧‧作用層
905‧‧‧源極區域
906‧‧‧結構/溝渠閘極
908‧‧‧經輕摻雜之汲極延伸區域/經輕摻雜汲極延伸區域/N汲極延伸區域(亦即，經輕摻雜汲極區域)
910‧‧‧汲極觸點/汲極接觸區域/汲極及源極觸點
912‧‧‧場板/閘極屏蔽層/屏蔽/屏蔽場板
914‧‧‧多晶矽閘極結構/閘極/閘極(例如，多晶矽結構)
916‧‧‧汲極及源極觸點
918‧‧‧矽化物層
920‧‧‧P型主體區域
922‧‧‧閘極氧化物
924‧‧‧橫向隔離結構
1000‧‧‧n通道金屬-絕緣體-半導體場效應電晶體裝置/橫向擴散之金屬-氧化物-半導體電晶體/橫向擴散之金屬-氧化物-半導體裝置/金屬-氧化物-半導體場效應半導體/金屬-氧化物-半導體場效應半導體裝置/橫向擴散之金屬-氧化物-半導體裝置/說明性裝置/金屬-氧化物-半導體場效應半導體結構/N通道橫向擴散之金屬-氧化物-半導體電晶體
1000A‧‧‧橫向擴散之金屬-氧化物-半導體裝置
1012‧‧‧閘極屏蔽
1014‧‧‧經提升之階部分
1016‧‧‧較厚氧化物
1100‧‧‧金屬-氧化物-半導體場效應半導體
1102‧‧‧P主體區域/早先主體區域/早先P主體/P主體/深P+井/經埋入井
1104‧‧‧N區域/N汲極/N汲極區域
1200‧‧‧雙極型接面電晶體
1201‧‧‧基極區域
1202‧‧‧射極觸點/溝渠觸點
1204‧‧‧深P+井/深P+層
1250‧‧‧雙極型接面電晶體裝置/例示性雙極型接面電晶體
1250A‧‧‧雙極型接面電晶體實施例
1252‧‧‧連接
1252A‧‧‧連接/連接層
1254‧‧‧多晶金屬矽化物結構
1256‧‧‧基極觸點
1258‧‧‧按鈕狀觸點
1300‧‧‧PN二極體/二極體
1300A‧‧‧PN二極體裝置/PN二極體
1302‧‧‧陽極溝渠觸點//溝渠觸點
1302A‧‧‧經修改之溝渠觸點/導電層/閘極屏蔽/屏蔽結構
1302B‧‧‧陽極溝渠觸點/延伸
1304‧‧‧按鈕觸點/按鈕狀觸點
1400‧‧‧肖特基二極體/二極體
1400A‧‧‧肖特基二極體
1402‧‧‧陽極(A)觸點/陽極觸點/陽極觸點(金屬)
1404‧‧‧N-作用層/N-作用區域/作用區域/N-層/N-台面區域
1406‧‧‧多晶金屬矽化物閘極結構/多晶金屬矽化物結構/頂部多晶金屬矽化物層
1408‧‧‧深P+井/深井
1410‧‧‧N植入區域/N區域
1412‧‧‧N+區域
1414‧‧‧屏蔽結構
1450‧‧‧肖特基二極體
1452‧‧‧N區域
1500‧‧‧肖特基二極體/二極體/二極體結構/切換式肖特基二 極體
1500A‧‧‧切換式肖特基二極體
1502‧‧‧閘極溝渠/閘極溝渠結構/溝渠
1504‧‧‧多晶金屬矽化物電極
1510‧‧‧N植入區域/N區域
1514‧‧‧橫向隔離區域
1552‧‧‧N植入區域/N區域
1600‧‧‧電阻器結構
1602‧‧‧電阻器路徑/N-電阻器路徑
1603‧‧‧深P+井/P+井
1604‧‧‧N-區域
1606‧‧‧閘極溝渠
1608‧‧‧N+接觸區域
1610‧‧‧N+接觸區域
1612‧‧‧溝渠觸點
1614‧‧‧橫向隔離區域
1702‧‧‧經埋入P+深井/井
1800‧‧‧電容器結構
1802‧‧‧電容器電極/溝渠
1804‧‧‧深N+井
1806‧‧‧作用層
1808‧‧‧橫向隔離區域
1900‧‧‧橫向擴散之金屬-氧化物-半導體裝置/金屬-氧化物-半導體場效應半導體/P通道金屬-氧化物-半導體場效應半導體
1902‧‧‧閘極溝渠
2002‧‧‧作用層
2004‧‧‧經埋入井/經埋入層/局域深P+井
2006‧‧‧經埋入氧化物
2008‧‧‧閘極溝渠
2010‧‧‧多晶矽
2012‧‧‧多晶金屬矽化物層/矽化物層
2014‧‧‧主體區域
2016‧‧‧汲極延伸區域/經輕摻雜汲極延伸/汲極(經輕摻雜汲極)延伸
2022‧‧‧電場氧化物
2024‧‧‧場板
2026‧‧‧淺源極接觸溝渠
2028‧‧‧矽化物膜
2030‧‧‧層間介電質膜
2032‧‧‧厚鋁層/閘極、汲極及源極頂部電極
2102‧‧‧作用區域
2104‧‧‧作用區域
2106‧‧‧作用層/作用區域/N-作用區域
2108‧‧‧橫向隔離溝渠
2110‧‧‧經埋入氧化物層/共同經埋入氧化物層
2112‧‧‧N型或P型基板
2114‧‧‧經埋入P+井/經埋入井/經埋入之P+井
2116‧‧‧P主體區域
2118‧‧‧N作用區域/N區域
2120‧‧‧閘極氧化物層
2122‧‧‧多晶矽閘極結構/多晶矽層
2124‧‧‧矽化物層
2126‧‧‧經摻雜N+區域/N+經摻雜區域
2128‧‧‧氧化物層
2130‧‧‧溝渠
2132‧‧‧矽化物層/矽化物或鈦/氮化鈦層
2134‧‧‧屏蔽場板
2136‧‧‧氧化物層
2138‧‧‧裝置觸點
2302‧‧‧導通孔
2304‧‧‧再分佈層
2306‧‧‧球觸點/個別觸點/閘極及汲極觸點
2308‧‧‧電流匯流排結構/源極匯流排
A‧‧‧陽極端子/陽極觸點
B‧‧‧單獨塊體端子
C‧‧‧陰極端子
D‧‧‧汲極端子
G‧‧‧閘極端子
S‧‧‧源極端子
僅以實例而非限定之方式呈現以下圖式，其中相同元件符號(當使用時)貫穿數個視圖指示對應元件，且其中：圖1係圖解說明一例示性功率管理電路之一方塊圖，該功率管理電路包含實施於一單個IC中之控制電路、一驅動級及功率切換器；圖2係圖解說明包含例示性功率管理控制電路之一功率級及實施於一IC中、與在該IC外部之離散功率切換器耦合之一驅動級之一方塊圖；圖3係圖解說明適合於根據本發明之實施例使用之包含實施於一第一IC中之例示性功率管理控制電路之一功率級以及實施於與該第一IC耦合之一第二IC中之一驅動級及功率切換器之一方塊圖；圖4及圖5係繪示習用之橫向擴散金屬-氧化物-半導體(LDMOS)電晶體裝置之剖面圖；圖6及圖7係繪示形成於SOI基板上之習用LDMOS電晶體裝置之剖面圖；圖8係繪示根據本發明之一實施例之一例示性BiCMOS結構之至少一部分之一剖面圖；圖9A及圖9B係繪示根據本發明之一實施例之一例示性N通道LDMOS電晶體之至少一部分之剖面圖；圖10係繪示根據本發明之另一實施例之一例示性N通道LDMOS電晶體之至少一部分之一剖面圖；圖10A係繪示根據本發明之另一實施例之一例示性N通道LDMOS電晶體之至少一部分之一剖面圖；圖11係繪示根據本發明之一實施例之一例示性低電壓信號 MOSFET之至少一部分之一剖面圖；圖12A至圖12E係繪示根據本發明之實施例之一例示性雙極型接面電晶體(BJT)之至少一部分之剖面圖；圖13係繪示根據本發明之一實施例之一例示性PN二極體之至少一部分之一剖面圖；圖13A係繪示一例示性PN二極體之另一實施例之至少一部分之一剖面圖；圖13B及圖13C係繪示用以根據一PN二極體之實施例將閘極耦合至陽極端子之方法之剖面圖；圖14A係繪示根據本發明之一實施例之一例示性肖特基(Schottky)二極體之至少一部分之一剖面圖；圖14B係繪示根據本發明之另一實施例之一例示性肖特基二極體之至少一部分之一剖面圖；圖14C係繪示一例示性肖特基二極體之一替代實施例之至少一部分之一剖面圖；圖15係繪示根據本發明之一第三實施例之一例示性肖特基二極體之至少一部分之一剖面圖；圖15A係繪示圖15之閘極溝渠結構之一剖面圖；圖15B係繪示一例示性肖特基二極體之另一實施例之至少一部分之一剖面圖；圖15C係圖解說明針對一例示性肖特基二極體之一實施例之傳導電流之一改變之一圖表；圖16及圖17分別係繪示根據本發明之一實施例在一螺旋佈局中之一例示性電阻器結構之至少一部分之俯視圖及剖面圖；圖18係繪示根據本發明之一實施例之一例示性電容器結構之至少一部分之一剖面圖； 圖19係繪示根據本發明之一實施例之一例示性P通道MOSFET之至少一部分之一剖面圖；圖20A至圖20F係繪示根據本發明之一實施例之一例示性BiCMOS程序流程之剖面圖；且圖21A至圖21E係繪示根據本發明之一實施例用於將兩個功率裝置整合於同一SOI基板上之一例示性BiCMOS程序流程之至少一部分之剖面圖；圖22A至圖22C圖解說明用於各種屏蔽結構之閘極與汲極區域之間的電場分佈；且圖23係圖解說明一晶片級總成之一剖面圖。
應瞭解，出於簡單及清晰之目的圖解說明圖中之元件。可不展示在一商業上可行之實施例中有用或必需之常見但易於理解之元件，以便促進所圖解說明實施例之一較清晰視圖。
本文中將以用於形成適合用於說明性功率管理電路中之說明性功率管理電路及半導體製作方法為上下文來闡述本發明之實施例。然而，應瞭解，本發明之實施例不限於本文中所展示及闡述之特定電路及/或方法。相反，本發明之實施例更廣義地係關於用於以達成各種各樣的功率管理應用(舉例而言，諸如一DC/DC功率轉換器)之高頻率效能之一方式來製作一積體電路之技術，且有利地減小可用於結合本發明之實施例使用之外部組件(舉例而言，諸如一輸出濾波器)之實體大小及成本以及其他益處。此外，在本文中之教示下，熟習此項技術者將易於理解，可對在所主張發明之範疇內之所展示實施例做出眾多修改。亦即，不意欲或不應推斷出關於本文中所展示及闡述之實施例之任何限制。
出於描述及主張本發明之態樣之目的，如本文中所使用之術語 MOSFET意欲廣義地視為涵蓋任何類型之金屬-絕緣體-半導體場效應電晶體(MISFET)。舉例而言，術語MOSFET意欲涵蓋利用一個氧化物材料作為其閘極介電質之半導體場效應電晶體以及並不利用氧化物材料作為其閘極介電質之半導體場效應電晶體。另外，儘管在縮寫字MOSFET及MISFET中提及術語「金屬」，但根據本發明之實施例之一MOSFET及/或MISFET亦意欲涵蓋具有由一非金屬(例如，諸如多晶矽)形成之一閘極之半導體場效應電晶體。
儘管本文中所闡述之本發明之實施方案可使用p通道MISFET(下文中稱為「PMOS」或「PFET」裝置)及n通道MISFET(下文中稱為「NMOS」或「NFET」裝置)來實施，如同可使用一BiCMOS(雙極型互補金屬氧化物半導體)製作程序來形成，但應瞭解，本發明不限於此等電晶體裝置及/或此一製作程序，且如熟習此項技術者在給定本文中之教示時將瞭解，可類似地採用其他合適的裝置，諸如(舉例而言)橫向擴散之金屬-氧化物-半導體(LDMOS)裝置、雙極型接面電晶體(BJT)等，及/或製作程序(例如雙極型、互補金屬-氧化物-半導體(CMOS)等)。此外，儘管本發明之實施例係製作於矽晶圓中，但本發明之實施例亦可替代地製作於包括其他材料之晶圓上，該等其他材料包含但不限於砷化鎵(GaAs)、氮化鎵(GaN)、磷化銦(InP)、硒化鎘(CdSe)、碲化鎘(CdTe)、硫化鋅(ZnS)等。
如先前提及，在將裝置電流限於數百毫安(亦即，裝置功率消耗小於約二瓦特)時，說明性功率級可單片整合於如圖1中所展示之一功率管理電路架構中，其中控制電路102、驅動級104及功率切換器106、108皆製作於同一IC晶片100上。然而，在裝置功率消耗增加超過約五瓦特左右(例如，大於約兩安培(A))時，功率管理電路之一替代分割係有利的及/或所需要的。
舉例而言，圖2係圖解說明一例示性功率級之一方塊圖，該例示 性功率級包括實施於一第一IC 200中之功率管理控制電路102及一驅動級104，以及實施於經個別封裝之離散IC裝置202及204中、與第一IC耦合且在其外部之功率切換器。不幸地是，儘管此解決方案使得能夠與功率切換器分離地製作控制電路，且因此受益於個別地最佳化每一IC之製作程序之一能力，但相關聯於介於第一(控制)IC 200與功率切換IC 202及204之間的互連件206(例如，印刷電路跡線、接合導線、球形柵格陣列(BGA)等)之寄生阻抗(主要為寄生電感)本質上阻止將此方法用於高頻率應用(例如，高於約一百萬赫)中。然而，此方法通常用於介於約5瓦特至約30瓦特之間的範圍內之功率轉換。
圖3係圖解說明根據本發明之一實施例之一例示性功率級300之至少一部分之一方塊圖，該例示性功率級包括實施於一第一IC 304中之功率管理控制電路302，以及實施於與該第一IC耦合之一第二IC 312中之一驅動級306及功率切換器308及310。舉例而言，將如圖3中所展示之功率級300之分割應用於DC/DC轉換器以及具有大於約30瓦特之一功率轉換之其他電路及子系統。更特定而言，將功率級300分割成：一控制IC 304，其係以一較複雜之數位VLSI(極大規模整合)技術程序製作；及一功率塊312，其實施為一多晶片模組(MCM)，該MCM包含以一類比技術製作之驅動級306以及整合為該MCM中之裸晶粒之離散功率切換器308及310。
圖3之MCM方法用於針對大功率應用(例如，用於桌上型電腦)之功率管理系統。於此情形中，該模組含有三個單獨晶粒：驅動器晶片以及兩個MOSFET功率切換器。便攜式電子裝置強烈地要求所實施子系統之小型化(亦即，小體積)，且強烈地要求減小在功率轉換階段中所產生之功率損失。因此，本發明之態樣提供允許具有功率切換器之驅動級之一單片整合之一成本有效技術，此達成根據圖3中所展示之分割方案之一雙晶粒解決方案。亦即，可針對電池操控之便攜式電子 裝置所需要的中型功率應用而在同一晶粒上製造驅動器及FET功率切換器。當前不存在任何技術能夠達成針對高於約五瓦特之一功率範圍之此系統分割。
通常，以最大化整合密度及信號處理速度之一目標來開發一數位/類比程序(諸如，舉例而言，一BiCMOS技術)。可使用現有摻雜輪廓及程序步驟來設計之選用功率切換器通常不能在一功率管理應用中達成充分效能。電晶體接通電阻之減小及切換功率損失之減小需要摻雜結構之一專屬最佳化及一經定製之程序步驟序列之使用。此通常僅在離散功率切換器之設計中完成。另一方面，離散功率切換器之處理並不允許不同電子組件(包含NFET、PFET、雙極型接面電晶體、P-N接面及肖特基二極體等)之一單片整合。
功率管理系統(例如，DC/DC轉換器)通常使用功率切換器以執行輸入功率之一高頻率截波及使用包括電感器及電容器之一輸出濾波器來穩定在可變負載條件下之輸出電壓。切換頻率越高，功率轉換效能越好，且所需要之輸出濾波器之體積及成本越小。切換頻率自當前可獲得之約1百萬赫(MHz)增加至約5MHz係期望的，但由於用於實施功率切換之功率電晶體中之相關聯切換功率損失(其至少部分地歸因於裝置寄生阻抗(例如，內部電容、電感及電阻))而尚不可達成。
已知可藉由減少一內部主體二極體中所儲存之內部電容及電荷來顯著地改良功率MOSFET之切換效能(例如，見美國專利第7,420,247號及第7,842,568號)。圖4及圖5係分別繪示此項技術中已知的橫向擴散金屬-氧化物-半導體(LDMOS)電晶體400及500之剖面圖。一絕緣體上矽(SOI)基板上之一功率MOSFET之設計通常為MOSFET之效能提供一顯著技術優勢。圖6及圖7係分別繪示形成於此項技術中已知的SOI基板上之LDMOS電晶體600及700之剖面圖。將二極體埋入於一作用SOI層(例如，圖6中之602及圖7中之702)下方會降低輸出電容 (Coss)且明顯地減小一主體二極體體積，藉此與標準裝置結構相比減小二極體所儲存電荷(Qrr)及在整流期間(亦即，反轉跨越電晶體之偏壓)之相關功率損失。該兩個特徵減小相關聯之切換損失且達成裝置之操作頻率之一增加。儘管有使用SOI基板之此等技術優勢，但所提議之電晶體由於產品之成本增加而尚未廣泛地調適用於製造離散及/或積體功率MOSFET。而且，藉由關於由於在突崩條件下之熱載子注入(HCI)所致的閘極氧化物在閘極之閘極側拐角處之長期可靠性之問題而阻礙此方法之接受。
因此，需要開發一種關注於橫向功率裝置之最佳切換效能之類比整合程序，其允許不同類型之功率切換器連同相關聯驅動級以及(選用地)某些監視及保護功能一起的一單片整合。根據本發明之態樣製造之功率級為介於約一伏特(V)與約十伏特(V)之間的一輸入電壓範圍及介於約一安培與約五安培之間的一輸出電流提供一增強的功率管理解決方案。相應地，所遞送之功率將涵蓋粗略地介於三瓦特與30瓦特之間的一範圍，但本發明之實施例並不限於此或任何特定功率範圍。
如在下文中將進一步詳細闡釋，本文中所闡述之本發明之實施例係基於對具有介電質橫向隔離之SOI基板實施之一20伏特BiCMOS技術。根據本發明之實施例，將圖3中所呈現之系統分割作為一雙晶粒解決方案而達成。一晶片級總成(亦即，晶片級封裝(CSP)或晶圓級封裝(WLP))較佳地避免與個別組件之封裝相關聯之體積及成本。在本發明之實施例中，藉由積體驅動器之一較低成本來制衡功率切換器之較高成本，且藉由增加操作頻率來達成濾波器組件之體積及成本之一明顯減小。
圖8係繪示併入有根據本發明之一實施例之態樣之一例示性結構800之至少一部分之一剖面圖。結構800可使用一BiCMOS處理技術製 作於一N型或P型基板801上。參照圖8，結構800包含以下各項之一組合：一經埋入井802，其本端地植入於一作用層804之底部處；及複數個溝渠(亦即，溝渠條帶)806，其具有襯砌有閘極氧化物808或一替代介電質且填充有多晶矽材料810或一替代導電材料之側壁及底壁。溝渠806較佳地形成為一群組之平行條帶，該等平行條帶在經適當加偏壓時影響其之間的一電流流動(例如，在一FET或肖特基二極體實施例之情形中)，或其起作用以增加結構之每單位面積之一電容(例如，在一電容器實施例之情形中)。在此實例中，如在給定本文中之教示時將對熟習此項技術者顯而易見，作用層804形成為一N-區域，且經埋入井802形成為一P+井，但其他實施例可利用一替代摻雜方案(例如，N-區域及N+經埋入井，或P-區域及P+或N+經埋入井)。
結構800之組態有利地允許整合各種各樣的組件，諸如(舉例而言)FET、BJT、PN二極體、肖特基二極體、電阻器及電容器。溝渠806中之每一者實質上垂直地自結構800之一頂部表面812延伸，穿過作用層804，且至少部分地進入至經埋入井802中。在替代實施例中，溝渠806可延伸穿過經埋入井802進入至經埋入之氧化物層818中。覆蓋溝渠806之側壁及底壁之氧化物襯裡808阻止填充溝渠之多晶矽材料810與經埋入井802之間的直接電連接。多晶矽填料810較佳地用作一閘極端子，其可如(舉例而言)FET及肖特基二極體實施例中來加偏壓。
經埋入井802在操作以維持一所施加之阻遏電壓之裝置(諸如電晶體或二極體)中具有一重要功能。更特定而言，以使得實質上固定(亦即，箝制)形成於經埋入井之一上部右側(亦即，尖端)與作用層804之一N-背景摻雜之間的PN接面處之一崩潰電壓之一方式來組態經埋入井802之一摻雜位準、摻雜類型及/或一位置。藉由選擇性地控制經埋入井802之一或多個特性，控制該裝置中之一電場分佈。
將具有襯砌有閘極氧化物808之壁(亦即，側壁及底壁)之溝渠條帶806放置於形成於其中之功率裝置之主端子之間。如本文中所使用之術語「主端子」意欲廣義地指代對該裝置之外部連接，諸如(舉例而言)在一MOS裝置之情形中之源極及汲極端子或在二極體之情形中之陽極及陰極端子。在圖8中所展示之說明性實施例中，實質上平行於一電流路徑來形成(例如，蝕刻)溝渠閘極條帶806。結果，在(舉例而言)一橫向肖特基二極體之情形中，一傳導電流流動於閘極溝渠806之間的N-作用層804中且可藉由一所施加閘極電位來控制(例如，調變)。在根據本發明之一或多項實施例形成之一FET結構之情形中，溝渠閘極806操作以耗乏或增強一閘極/主體界面，從而控制穿過形成於裝置中之一反轉通道之電流流動。
填充該等溝渠之經摻雜多晶矽材料810用於形成將閘極區域沿一第三維度(未明確地展示)連接至一閘極端子之一閘極匯流排。對於根據本發明之一實施例形成之一NFET裝置而言，多晶矽材料810較佳地摻雜有磷，其中摻雜濃度大於約1019/cm3，而對於一PFET裝置而言，多晶矽材料較佳地摻雜有硼，具有約1019/cm3之摻雜濃度。多晶矽閘極層810之頂部表面展示為視情況由具有低電阻率之矽化物材料814(例如，矽化鈦(TiSi)或矽化鎢(WSi))覆蓋，該矽化物材料可使用一習知矽化物沈積程序(例如，化學汽相沈積(CVD)、濺鍍沈積等)沈積於其上。在裝置800中形成多晶金屬矽化物(polycide)電極之矽化物層814減小該裝置之一閘極電阻。
在一較佳實施例中，窄的閘極溝渠806沿著主體區域804中之電流流動之一路徑形成於多晶金屬矽化物電極814下方。以此方式，溝渠806增加MOSFET結構800中之一有效閘極寬度，以及其他優勢。
比溝渠806更深地形成之另一溝渠結構816較佳地用於形成積體組件之間的一橫向隔離區域。深溝渠結構816(在本文中亦稱為一橫 向隔離溝渠)可藉由(舉例而言)自該結構之頂部表面812蝕刻穿過作用層804至形成於基板801上之一經埋入氧化物層818而形成。橫向隔離溝渠816可填充有氧化物，或氧化物與多晶矽之一組合。分割(亦即，蝕刻)(未明確地展示)穿過經埋入氧化物層818至基板801之一選用深溝渠可用作一基板接觸。此選用溝渠較佳地填充有經摻雜多晶矽或一替代導電材料以確保對基板801之良好歐姆(亦即，低電阻)接觸。
可使用根據本發明之實施例之一說明性BiCMOS程序流程來形成各種各樣的電子組件。在下文中參照圖9A至圖19來闡述併入有本發明之若干態樣之可形成之某些組件之實例。
圖9A係繪示根據本發明之一實施例之一例示性N通道LDMOS電晶體900之至少一部分之一剖面圖。與標準LDMOS裝置相比，至少部分地由於閘極屏蔽層之效應，LDMOS電晶體900具有減小的閘極至汲極電容(Cgd)。此外，至少部分地由於減小的二極體儲存電荷，LDMOS電晶體900展示對主體二極體之反向復原(Qrr)之一小影響。電晶體900包含一積體PN箝位二極體(亦即，藉由深井902之端部及汲極區域形成之二極體)作為每一作用井之一組成部分，該積體PN箝位二極體將突崩潰固定為遠離閘極氧化物且接近於一經埋入P+井902之上部右拐角。亦即，在阻遏條件下，突崩碰撞離子化位於經埋入井902之尖端與汲極接觸區域之拐角之間，在作用層之體積內且遠離頂部及底部氧化物界面。此使得在不致使任何可靠性問題之情況下增加功率電晶體之耐突崩性。此電晶體設計最小化熱載子至氧化物中之注入，從而改良功率切換器之長期可靠性。一傳導電流自一溝渠閘極906之壁之間的一源極區域905流動至一經輕摻雜汲極(LDD)延伸區域908中進入至一汲極觸點910中。一類似形成之溝渠閘極(剖面係沿溝渠截取)之一替代視圖展示為圖9B中所繪示之結構906。圖9B圖解說明實質上垂直地穿過一P型主體區域920且進入至形成於主體區域之底部處 之經埋入P+井902中而形成之溝渠閘極906。溝渠閘極906具有襯砌有閘極氧化物922之壁(亦即，側壁及底壁)。圖9B中亦展示一橫向隔離結構924，該橫向隔離結構可以與圖8中所展示之橫向隔離結構816一致的方式形成，其提供積體組件之間的隔離。在處理期間，SOI基板中之一P-處置晶圓沿著一P-基板/經埋入氧化物界面被耗乏，此降低MOSFET之一輸出電容Coss。
應瞭解，在一簡單MOS裝置之情形中，由於MOS裝置本質上係對稱的，且因此係雙向的，因此MOS裝置中之源極及汲極設計之指派係本質上任意的。因此，源極及汲極區域可分別大體稱為第一及第二源極/汲極區域，其中在此上下文中「源極/汲極」標識一源極區域或一汲極區域。在通常並非雙向之一LDMOS裝置中，此等源極及汲極設計可並非任意指派的。
經埋入井902(如同圖8中所展示之經埋入井802)尤其在操作以維持一所施加之阻遏電壓之裝置(例如，電晶體及二極體)中具有一重要功能。更特定而言，以使得實質上箝制形成於經埋入井之一上部右側與該裝置中之一作用層904之一N-背景摻雜之間的PN接面處之崩潰電壓之一方式來組態經埋入井902之一摻雜位準、摻雜類型及/或一位置。藉由選擇性地控制經埋入井902之一或多個特性，控制裝置中之一電場分佈。例如，該裝置可經有利地配置以使得一最大電場分佈於經埋入井902之上部右拐角與一汲極接觸區域910之一右底部拐角之間。在以此方式組態時，一箝位PN二極體整合於該裝置內，此使得保持藉由突崩碰撞離子化而產生之熱載子遠離一頂部矽/氧化物界面。此特徵使得在不形成裝置中之可靠性問題之情況下增加裝置吸收突崩能量之一能力。
當將圖6及圖7中展示之說明性SOI LDMOS裝置600及700分別推動至突崩中時，碰撞離子化將發生於閘極之一底部拐角處，覆蓋裝置 中之一經輕摻雜汲極(LDD)區域，且熱載子至該裝置中之一閘極氧化物中之注入將通常導致可靠性問題，如此項技術中所熟知。至少出於此原因，SOI上之習用LDMOS結構不適合用作功率切換器。藉由提供用以將突崩箝制於一LDMOS電晶體裝置中之一所期望位置處之一能力，根據本發明之一或多項態樣形成之LDMOS結構良好地適合用於一功率切換應用中。
繼續參照圖9A及圖9B，LDMOS電晶體900包含一屏蔽場板912或替代屏蔽結構，該屏蔽結構在此實施例中形成為襯砌有源極溝渠接觸壁之一導電層之一橫向延伸，與一閘極(例如，多晶矽結構)914重疊且緊鄰近沿著N汲極延伸區域(亦即，LDD區域)908之氧化物界面。該導電層較佳地沈積為鈦(Ti)/氮化鈦(TiN)堆疊，但亦可由其他材料形成，諸如(舉例而言)鈦(Ti)/矽化鎢(WSi)膜。在此說明性實施例中，源極溝渠形成於LDMOS電晶體900之左手側上，具有襯砌有閘極屏蔽層912且填充有頂部金屬之側壁及一底部壁。
屏蔽912主要地起一場板之作用，沿著遠離閘極914之一邊緣(例如，底部右拐角)最接近於汲極處之一頂部氧化物界面分佈(例如，伸展)一電場分佈，且亦用作幫助減小汲極之一正偏壓處之閘極至汲極電容Cgd(所謂的米勒電容，其判定電晶體之切換速度)且進一步改良閘極氧化物可靠性之一屏蔽。顯現於閘極914之汲極側拐角處之電場峰值現在在閘極拐角與場板之端部之間分開，從而減小電場峰值且抑制熱載子至氧化物中之提早注入。汲極及源極觸點910及916分別形成為經金屬填充之導通體，該等導通體接達一圖案化頂部金屬層(未明確展示，但已暗示)且分別形成LDMOS裝置900之汲極(D)及源極(S)端子。亦以施加至汲極觸點910之一正偏壓來耗乏經輕摻雜之汲極延伸區域(908)亦有助於減小Cgd。形成於多晶矽閘極結構914上、藉此形成多晶金屬矽化物層(亦稱為經矽化之多晶矽)之矽化物層918用於形成 通向一閘極端子(G)之沿一第三維度(未明確展示，但已暗示)定位之一閘極匯流排。矽化物層918較佳地使用一習知沈積程序(例如，CVD、濺鍍等)形成。
圖10係繪示根據本發明之另一實施例之一例示性N通道LDMOS電晶體1000之至少一部分之一剖面圖。此LDMOS電晶體1000設計為圖9A及圖9B中所展示之LDMOS裝置900之一簡化。如自圖10顯而易見，與圖9A及圖9B中所展示之LDMOS裝置900相比，在LDMOS裝置1000之製作中之一項簡化包括移除閘極溝渠(圖9A及圖9B中之906)。對MOSFET 1000之效能之一主要影響係每單位面積之一較小閘極寬度，此增加所得裝置之接通電阻RON。此可藉由因移除與閘極多晶矽在閘極溝渠尾端上之一重疊有關的對準約束而使得通道長度較短來制衡。MOSFET裝置1000之其他特徵及特性保持與LDMOS裝置900本質上相同。
圖10A圖解說明圖10之LDMOS裝置1000之一替代實施例。具體而言，此實施例包含將崩潰電壓擴展至高於20V之一修改。在圖10A之LDMOS裝置1000A中，在閘極端子與汲極端子之間引入一窄條帶之較厚氧化物1016。此允許閘極屏蔽1012形成二階場板(亦即，添加經提升之階部分1014)，此進一步改良電場分佈。
圖22A至圖22C展示在各種組態下閘極與汲極區域之間的電場分佈。圖22A展示在無場板之影響之情況下閘極與汲極區域之間的電場分佈。在閘極之拐角處之高電場峰值允許將熱載子注入至閘極氧化物中，此降低電晶體之可靠性。圖22B展示在設計用於20V崩潰之一電晶體中之藉由閘極屏蔽層形成之場板消除此臨界電場。在圖22C中展示場板在屏蔽結構中之進一步改良，其中引入一較厚氧化物條帶達成將峰值電場推動遠離該閘極拐角之二階場板輪廓。如上文所提及，此結構較佳地用於設計用於高於20V之一崩潰電壓之電晶體中。
圖11係繪示根據本發明之一實施例之一例示性低電壓信號MOSFET 1100之至少一部分之一剖面圖。如下文中將進一步詳細闡述，MOSFET 1100包含可用於形成其他電路組件之一P主體區域1102及一N汲極區域1104。在此實施例中，P+經埋入井並非如圖10中所展示之例示性MOSFET 1000中之情形與源極端子直接連接，而是與一單獨塊體(B)端子連接。此組態允許將不同於施加至源極端子之電壓電位之一電壓電位施加至經埋入井。藉由圖10中所展示之說明性裝置1000之另一簡化來形成MOSFET 1100。具體而言，已減小基本單元之一節距，藉此允許將放置於電路中之此等裝置之一較高密度。作為對較高密度之一折中，MOSFET 1100具有減小的高電壓能力及減小的耐突崩性，但此等特徵通常對功率切換應用而言更為重要。
在結合圖9A至圖11於上文闡述之MOSFET之特定實施例中，將電晶體設計為12V與60V之間的一目標崩潰電壓規範。在低電壓功率管理系統中，此等MOSFET經最佳化用於如具有最小導電性及切換功率損失之功率切換器之應用。本文中所闡述之實施例達成在實施圖3之積體方案時DC/DC轉換器自1.5MHz至5MHz之切換頻率增加。
現在參照圖12A，一剖面圖繪示根據本發明之一實施例之一例示性SOI雙極型接面電晶體(BJT)1200之至少一部分。BJT 1200形成為圖10中所展示之MOSFET裝置1000之一修改。此處，將圖11中所展示之MOSFET 1100之一早先主體區域1102用作BJT 1200之一基極區域1201。已移除源極溝渠觸點。相反，跨越基極區域1201分割溝渠觸點1202以實現一深P+層1204與多晶金屬矽化物結構(亦即，經矽化之多晶矽)之間的一連接。圖12B繪示圖解說明根據本發明之一實施例用以形成深P+層1204與多晶金屬矽化物結構之間的連接之一種方式之一例示性BJT 1250。具體而言，藉由沿著指狀佈局(例如，在指狀物之間)中斷射極觸點1202而將深P+層1204與多晶金屬矽化物結構1254之間的 一連接1252形成為若干點(亦即，觸點)。在此實施例中，連接1252形成為鈦(Ti)/氮化鈦(TiN)層(以類似於圖9中所展示之場板912之一方式)之一橫向延伸且與多晶金屬矽化物結構1254重疊。此等觸點較佳地沿著多晶金屬矽化物條帶以所規定間隔放置(例如，在一MOSFET之情形中，該多晶金屬矽化物區域將係圖案化為一條帶之閘極，且用於建構一基極匯流排觸點)，且該多晶金屬矽化物層用於形成具有低電阻率之一基極匯流排。使用該多晶金屬矽化物材料作為將基極區域接觸至基極端子之電流匯流排確保了低基極電阻，此改良電晶體之切換效能。
圖12C圖解說明一BJT實施例1250A，其中將一基極觸點1256部分地形成於形成於作用區域中之一溝渠區域中且與連接1252電接觸。
在圖12D之部分剖面圖中所圖解說明之一實施例中，連接1252A並不直接接觸多晶金屬矽化物基極，而是與其間隔開。提供一按鈕狀觸點1258且使其接觸多晶金屬矽化物基極之上部表面與連接層1252A之上部表面(及視情況地，側表面)兩者。此等按鈕觸點1304中之一或多者可經間隔(以沿著基極多晶金屬矽化物條帶之一第三維度，且與射極觸點交錯)以實現具有深P+井1204之多晶金屬矽化物基極結構經由連接層1252A與基極觸點1256之間的接觸。
使用此BJT組態來保存MOSFET結構之初始高電壓能力及耐突崩性。將形成於深P+井之尖端與集極區域之間的PN接面用作箝位二極體。如在MOSFET之情形中，BJT之PN箝位二極體將突崩潰之區固定於矽層之體積內，從而侷限藉由對此位置之突崩碰撞離子化所產生之熱載子。
參照圖12A，可觀察到，BJT包含在多晶金屬矽化物堆疊下方之一MOS通道，該MOS通道形成與雙極型電晶體並聯之一MOSFET結構。若施加至BJT基極端子之正偏壓大於MOSFET之臨限電壓，則藉 由流動穿過MOS通道之電子電流來增加集極電流，此改良BJT之增益(β)。
儘管未展示，但如結合本文中所闡述之其他實施例所論述之一屏蔽結構亦可併入至此設計中以改良BJT裝置之崩潰/可靠性效能。
如圖12E中所展示，可藉由反轉所植入之摻雜區域之極性而將圖12A中所展示之NPN BJT電晶體結構轉換成一PNP BJT。
如上文所提及，基本MOSFET結構可經調適以提供功率二極體。不同於以一VLSI技術設計之習用功率PN二極體，本文中所闡述之功率PN二極體展現耐突崩性。此外，該基本MOSFET結構可經調適以提供通常並不在設計者之VLSI組件工具箱中之肖特基二極體。本文中所揭示之結構藉由實施能夠維持整個所施加電壓之PN及肖特基二極體來增加功率管理IC設計之靈活性。此等二極體展現在供應電壓軌中之電壓尖波驅動該電路超過所允許的最大阻遏電壓值時的獨特耐突崩性。此等所提議之二極體與針對SOI-MOSFET所揭示之程序流程相容，且係彼結構之直接修改。
圖13係繪示根據本發明之一實施例之一例示性PN二極體1300之至少一部分之一剖面圖。作為對圖10中所展示之例示性MOSFET結構1000之一修改而獲得PN二極體1300。此處，已省略N+源極區域，且藉由早先P主體1102與N汲極1104之一接面來形成用於形成二極體1300之PN接面。形成具有經調適用於與P主體1102電連接之一溝渠觸點1302之一陽極(A)端子。一陰極(C)端子經調適以提供與二極體之N區域1104之電連接。保存MOSFET結構之初始高電壓能力及耐突崩性。
圖13A係繪示根據一替代實施例之一PN二極體1300A之一例示性實施例之至少一部分之一剖面圖。PN二極體1300A與PN二極體1300一致，但經修改之溝渠觸點1302A除外，該經修改之溝渠觸點延伸以 至少部分地與閘極重疊以提供包含一場板之一屏蔽結構，如上文結合圖9A及圖10所闡述。圖13A之PN二極體藉由使沿著作用層界面放置之深P+井1102朝向經埋入氧化物來保存LDMOS結構之完全電壓阻遏能力。在阻遏條件下，突崩碰撞離子化局域化於經埋入井1102之尖端與陰極接觸區域之拐角之間，在作用層之體積內且遠離頂部及底部氧化物界面。二極體之此設計最小化熱載子至氧化物中之注入，從而改良功率裝置之長期可靠性。藉由深P+井1102之端部與陰極區域而形成之PN接面用作作為該二極體之每一作用單元之一組成部分之一箝位二極體。藉由此箝位二極體定義之突崩潰固定於矽材料之體積內，從而增加功率裝置之耐突崩性。積體屏蔽結構降低閘極端子與陰極端子之間的電容耦合，且充當沿著與Ldd區域之頂部氧化物界面伸展出該電場分佈之一場板。顯現於閘極堆疊之陰極側拐角處之電場峰值現在在閘極拐角與場板之端部之間分開，從而減小電場峰值且抑制熱載子至氧化物中之提早注入。
在圖13及圖13A之實施例中，多晶金屬矽化物閘極及深P+井1102可沿一第三維度連接至陽極端子。如圖13B之部分剖面圖中所展示，多晶金屬矽化物閘極可經由延伸穿過導電層/閘極屏蔽1302a之一按鈕狀觸點1304連接至陽極及深P+井1102，其中按鈕狀觸點1304實現與閘極結構之多晶金屬矽化物及與導電層/閘極屏蔽1302a之電接觸(例如，藉由部分地形成於導電層1302a之頂部表面上)。此等按鈕觸點1304中之一或多者可經間隔(沿一第三維度)以實現沿著多晶金屬矽化物條帶以所規定間隔(例如，以一指狀佈局)接觸至閘極多晶金屬矽化物，而非藉助一連續接觸來中斷屏蔽結構1302A。圖13C圖解說明用以將閘極多晶金屬矽化物耦合至陽極及深P+井之一替代方法。具體而言，陽極溝渠觸點1302B具有延伸以將閘極多晶金屬矽化物連接至陽極及深P+井1102之一橫向延伸(如同圖12B中所展示之延伸)。此延伸1302B亦 延伸以形成具有如上文結合圖13B之實施例所闡述之場板之屏蔽結構。在另一實施例中，閘極匯流排可經組態為與陽極分離之一端子，且該兩者可一起在外部短路。在某些實施例中，此方法可提供用於較簡單的處理。
已針對功率MOSFET來觀察肖特基二極體之單片整合，其中肖特基二極體箝制整個主體二極體。此方法旨在避免與在功率MOSFET之汲極至源極偏壓之整流期間的所儲存電荷Qrr有關的功率損失。在美國專利第6,049,108號及第6,078,090號之方法中，一肖特基二極體整合於一溝渠-MOSFET結構內，其中使用在肖特基接觸下方之兩個溝渠壁之鄰近以在阻遏條件下屏蔽肖特基接觸界面免受由汲極電壓所誘發之一高電場。此TMBS結構(溝渠-MOS-障壁-肖特基)之優勢係：肖特基接觸之電屏蔽達成在無阻遏能力之任何劣化之情況下使用較高摻雜之半導體(較低Vf)。而且，一TMBS二極體之洩漏電流具有扁平電壓特性，該電壓最高為由一相鄰單元中存在之PN接面所定義之崩潰電壓。
美國專利第7,745,846號揭示整合為一LDMOS電晶體結構中之一專屬單元之一肖特基二極體。該結構具有在晶圓之後側處朝向汲極觸點之一垂直電流流動。形成於頂部金屬與LDD-1區域之間的肖特基接觸之電屏蔽藉由閘極及P緩衝區域之阻遏影響而達成。肖特基二極體之前向I-V特性可由閘極電位影響。所整合之肖特基二極體具有與親代LDMOS電晶體相同的阻遏電壓能力。在此項技術中不提議任何可比之肖特基二極體用於功率管理IC。
圖14A係繪示根據本發明之一實施例之一例示性肖特基二極體1400之至少一部分之一剖面圖。肖特基二極體1400形成為圖13中所展示之PN二極體1300之一修改。具體而言，省略陽極溝渠觸點1302以及P主體區域1102(見圖13)，從而允許在陽極觸點(金屬)1402與一N- 作用層1404之間的一界面處形成一肖特基障壁。在實施例中，藉由一兩步式快速熱退火(在650℃及820℃處之RTP)來穩定該肖特基障壁，此導致在接觸界面處形成矽化物相位(例如，TiSi2)。頂部多晶金屬矽化物層1406及深P+井1408電連接至陽極(A)端子且在陰極(C)端子之一所施加阻遏偏壓下誘發電場分佈之一收縮。藉由將閘極堆疊放置於N區域之頂部處及將深P+井放置於N區域之底部處(此類似於一JFET通道之一動作)而形成之此收縮效應在阻遏條件下屏蔽該肖特基接觸界面免受任何高電場。該屏蔽效應在阻遏電壓之整個範圍(例如，約12伏特至約20伏特，但本發明並不限於任何特定電壓或電壓範圍)中保持二極體1400中之洩漏電流為低的。二極體中之洩漏電流之值將隨肖特基接觸處之N-作用區域1404之摻雜特性而變，如熟習此項技術者將知曉。(例如，見美國專利第5,365,102號，其揭示內容之整個內容以引用的方式併入本文中。)肖特基接觸之屏蔽達成半導體在肖特基界面處之一較高摻雜(如下文結合圖14B所論述)，且改良二極體之電效能。
深P+井1408及多晶金屬矽化物結構1406與陽極觸點1402之連接可以與圖12B中針對說明性BJT裝置1250所展示之連接1252相一致的一方式形成。具體而言，較佳地藉由中斷沿著一指狀佈局之陽極觸點1402而將深P+層1408與多晶金屬矽化物結構1406之間的連接形成為點。在此實施例中，將該連接形成為鈦(Ti)/氮化鈦(TiN)層之一橫向延伸(在圖14A中未明確展示，但以類似於圖12B中所展示之連接1252之一方式暗示)，且使其與多晶金屬矽化物結構1406重疊。此等觸點較佳地沿著多晶金屬矽化物條帶以所規定間隔放置(例如，在一MOSFET之情形中，該多晶金屬矽化物區域將係圖案化為一條帶之閘極)，且該多晶金屬矽化物層用於形成一低電阻率屏蔽結構，該低電阻率屏蔽結構操作以在阻遏條件下屏蔽該肖特基接觸免受任何高電 場，如先前所提及。
圖14C圖解說明繪示根據一替代實施例之一例示性肖特基二極體1400A之至少一部分之一剖面圖。肖特基二極體1400A與肖特基二極體1400相一致，但包含屏蔽結構1414，該屏蔽結構充當肖特基二極體1400A之一閘極屏蔽及一場板兩者。深P+井1408及多晶金屬矽化物閘極結構1406與陽極觸點1402之連接可以與圖13B或圖13C中針對說明性PN二極體裝置1300A所展示之連接相一致之一方式形成，或可如程序所指定而實現外部連接。在實施例中，屏蔽結構1414亦可併入至圖14B中所展示之肖特基二極體結構中。
由於藉由頂部多晶金屬矽化物電極之陰極(早先汲極)側上之裝置結構來維持阻遏電壓，且藉由深P+井1408之上部右拐角(亦即，尖端)處之PN接面來箝制突崩潰，因此保存MOSFET結構之初始高電壓能力及耐突崩性。深井1408較佳地係接近於Si/經埋入氧化物界面之具有一最大摻雜濃度之一植入井。在一較佳實施例中，最大摻雜濃度係在約5e16cm-3與5e17cm-3之間的範圍內，且摻雜輪廓經組態以朝向表面向下傾斜。然而，應瞭解，本發明並不限於深井1408之一特定摻雜濃度或輪廓。在此實施例中，PN接面係由深P+井1408、N-作用層1404、N區域1410及N+區域1412朝向陰極端子而形成。
圖14B係繪示根據本發明之另一實施例之一例示性肖特基二極體1450之至少一部分之一剖面圖。肖特基二極體1450與圖14A中所繪示之肖特基二極體1400本質上相同，但以類似於N區域1410之一方式在N-作用層1404中鄰近N-作用層之一上部表面形成一額外N區域1452。與圖14A中所展示之肖特基二極體1400相比，肖特基二極體1450之一優勢係：可藉由增加鄰近該肖特基接觸之N-作用層1404之摻雜濃度來降低圖14A中所繪示之肖特基二極體1400之前向電壓降。在一較佳實施例中，此係藉由將多晶矽化物區域之陰極側處之N植入區域1410延 伸至陽極(A)觸點1402下方之區域(在圖14B中展示為N區域1452)而達成。
如上文中結合圖10至圖14C中所繪示之例示性結構所闡述，根據本發明之一或多項實施例之一重要益處係包含深井，該深井經組態以箝制該崩潰電壓遠離矽/氧化物界面。此配置有利地使得該結構在不經歷可靠性問題之情況下吸收突崩能量。根據本發明之其他實施例之額外結構併入有一類似組態之汲極區域，因此繼承在(舉例而言)圖9A及圖9B中所展示之親代MOSFET設計之耐突崩性。
圖15係繪示根據本發明之另一實施例之一例示性肖特基二極體1500之至少一部分之一剖面圖。肖特基二極體1500形成為圖14A中所繪示之說明性肖特基二極體1400之一修改。具體而言，以與圖9中所展示之MOSFET 900之修改相一致之一方式，較佳地沿著形成於二極體1500之作用層之一上部表面上之一多晶金屬矽化物電極1504下方之N-台面區域(亦即，作用層)1404中之一電流流動路徑將閘極溝渠1502形成於裝置中。閘極溝渠結構1502額外地改良肖特基接觸免受施加至陰極(C)端子之阻遏電壓之屏蔽效應。在肖特基二極體1500中，閘極電極自一陽極(A)端子解耦合且可用於進一步修改閘極溝渠1502之間的一傳導路徑。該陽極端子沿一第三維度連接至深P+井1408，此並未明確地展示但已暗示。肖特基二極體1500可在本文中稱為切換式肖特基二極體且表示根據本發明之一實施例之一新類型之功率裝置。
圖15A係更詳細地繪示圖15之切換式肖特基二極體裝置之溝渠結構之一剖面圖。電流在傳導條件下在閘極溝渠1502之間自陽極(源極)觸點流動至陰極(汲極)區域。若溝渠寬度小於溝渠1502之間的N-平台區域(亦即，作用區域1404)之寬度，則增加每一作用單元之有效閘極寬度。閘極寬度之增加對應於MOSFET之互導之一增加，且分別對應於電晶體之接通電阻之一減小。如圖15及圖15A中所展示，在SOI-肖 特基二極體結構中實施閘極溝渠以藉由組合N-層1404之垂直耗乏及橫向耗乏來進一步增強屏蔽效應。可將閘極區域作為一第三端子來存取以藉由將一對應偏壓施加至此電極來接通及關斷橫向耗乏效應。如上文結合其他實施例來論述，陽極端子可沿第三維度連接至深P+井1408。橫向隔離區域1514(其可包括氧化物或其他介電質材料)形成於二極體結構1500中以電隔離該二極體與晶粒上之其他電路組件。
圖15B圖解說明一切換式肖特基二極體1500A之一替代實施例。切換式肖特基二極體1500A與圖15中所繪示之肖特基二極體1500本質上相同，但以類似於N區域1510之一方式在N-作用層1404中鄰近N-作用層之一上部表面形成一額外N植入區域1552。亦即，在肖特基接觸之附近將作用層摻雜至一較高N摻雜濃度，同時將閘極溝渠1502之間的作用層之摻雜保持於原始較低N-位準處。與圖15中所展示之切換式肖特基二極體1500相比，切換式肖特基二極體1500A之一優勢係：可藉由增加鄰近該肖特基接觸之N-作用層1404之摻雜濃度來減小圖15中所繪示之肖特基二極體1500之前向電壓降(Vf)，且屏蔽效應保持不受影響。在一較佳實施例中，此係藉由將多晶矽化物區域之陰極側處之N植入區域1510延伸至陽極(A)觸點下方之區域(在圖15B中展示為N區域1552)而達成。儘管在諸如美國專利第7,745,846號中所揭示之習知裝置中，前向特性可藉由施加至閘極電極之閘極至陽極偏壓來修改，但如圖15C中所圖解說明，來自圖15B之二極體結構展現在接通及關斷閘極偏壓時傳導電流之四個數量級之一改變。此切換式肖特基二極體可由於圖15A所圖解說明之閘極溝渠結構剖面而被稱為一π切換器。儘管並未展示，但如結合其他實施例所論述之一閘極屏蔽結構亦可併入至此設計中以改良該裝置之崩潰/可靠性效能。
圖16及圖17分別係繪示根據本發明之一實施例在一螺旋佈局中之一例示性電阻器結構1600之至少一部分之俯視圖及剖面圖。電阻器 路徑1602由閘極溝渠1606之間的一N-區域1604界定，該N-區域在螺旋形之兩端處連接至N+接觸區域1608及1610。該等N+接觸區域中之一者(例如，1608)包含至一深P+井1603(在圖16中並未明確地展示，但在圖17中展示為井1702)之一溝渠觸點1612。P+井1603隔離N-電阻器路徑1602與一底部，如在圖17之剖面圖中所展示。如圖17中所展示，經埋入P+深井1702操作以電隔離藉由溝渠之間的N-區域而形成之電阻器。橫向隔離區域1614(其可包括氧化物或其他介電質材料)形成於電阻器結構1600中以電隔離該電阻器與晶粒上之其他電路組件。
現在參照圖18，一剖面圖繪示根據本發明之一實施例之一例示性電容器結構1800之至少一部分。電容器結構1800可具有類似於圖16中所展示之電阻器結構1600之一螺旋佈局，或其可包括藉由溝渠1802形成之多個平行條帶。電容器電極1802藉由填充於閘極溝渠中之多晶矽及藉由作用層1806之底部處之深N+井1804形成。兩個區域皆連接至螺旋佈局之端部處之端子，此並未明確地展示但已暗示。橫向隔離區域1808(其可包括氧化物或其他介電質材料)形成於電容器結構1800中以電隔離該電容器與晶粒上之其他電路組件。
圖19係繪示根據本發明之一實施例之一例示性P通道MOSFET 1900之至少一部分之一剖面圖。MOSFET 1900形成為圖9中所展示之N通道MOSFET 900之一修改，其中已反轉用於摻雜主體(圖9中之P主體)以及源極及汲極區域之材料之一極性類型以形成一P通道LDMOS電晶體。如熟習此項技術者將瞭解，與僅用於製作N通道LDMOS電晶體900之程序相比，專屬用於形成平行於該N通道電晶體之一P通道MOSFET之植入物增加遮罩計數。如同N通道LDMOS電晶體1000，在製作LDMOS裝置1900中之一項簡化包括移除閘極溝渠1902。對所得MOSFET之效能之一主要影響係每單位面積之一較小閘極寬度，此增加所得裝置之接通電阻RON。此可藉由因移除與閘極多晶矽在閘極溝 渠尾端上之一重疊有關的對準約束而使得通道長度較短來制衡。
圖9至圖19中所繪示之例示性電子組件可用於建構包含功率切換器、二極體及某些相關聯電路之一BiCMOS電路。該BiCMOS程序流程包含允許製造圖9至圖17中呈現之組件之一基本遮罩組，以及允許組件組合包含圖18及圖19中所展示之結構之一額外遮罩子組。如本文中所使用，短語「基本遮罩組」經廣義地定義以係指用以基於根據本發明之實施例之一NFET結構來製作一組裝置所需要的最小數目個遮罩層級。
現在參照圖20A至圖20F，剖面圖共同地繪示根據本發明之一實施例之一例示性BiCMOS程序流程。該程序流程使用一基本遮罩組用於基於圖9中所展示之N通道LDMOS裝置之修改來製造電路組件，如上文中所闡述。該程序係基於具有一P-處置晶圓及一N-作用層之一SOI基板。僅以實例而非限制之方式，根據本發明之一實施例之一說明性程序流程包含下列主要步驟：使用一第一遮罩步驟(LTI遮罩)藉由蝕刻一溝渠穿過一作用層2002且用氧化物或氧化物與多晶矽之一組合來填充該溝渠而形成一橫向介電質隔離(亦稱為橫向溝渠隔離(LTI))，如圖20A中所展示；沈積一厚電場氧化物且藉助作用區遮罩(作用遮罩)來圖案化該厚電場氧化物；使用一第二遮罩步驟(深井遮罩)深植入硼或一替代摻雜物以形成一局域深P+井2004或替代地隨所採用之摻雜物而變之一N+井，其中在接近於P+井(經埋入層(BL))2004與一經埋入氧化物2006之間的一界面處具有一濃度峰值，如圖20A中所展示；使用一第三遮罩步驟(溝渠閘極遮罩)圖案化一遮罩以界定穿過作用層2002至經埋入井2004中之一或多個閘極溝渠2008之一定位，如圖20B中所展示；蝕刻具有經修圓之底部及頂部拐角之閘極溝渠，在該 閘極溝渠之側壁及底壁上生長一熱閘極氧化物，及用多晶矽2010填充該溝渠，此並未明確展示但已在圖20B中暗示；在一替代實施例中，可省略用於形成該閘極溝渠之步驟，藉此簡化圖9中所形成之NFET結構以形成圖10中所展示之結構。
藉由磷光體植入物或一替代摻雜物及退火來摻雜多晶矽2010，及將矽化物層2012沈積於頂部上，如圖20B中所展示；使用一第四遮罩層級(多晶矽遮罩)圖案化多晶金屬矽化物層2012以形成一閘極結構，如圖20B中所展示；使用一第五遮罩步驟(主體遮罩)植入硼以形成自對準至多晶金屬矽化物層2012之邊緣之一主體區域2014。藉助(舉例而言)一專屬熱退火來執行主體擴散，如圖20C中所展示；使用一第六遮罩步驟(LDD遮罩)植入磷光體或砷或一替代摻雜物以在多晶金屬矽化物層2012之另一邊緣處形成一經輕摻雜汲極(LDD)延伸2016，與用於形成主體區域2014之邊緣相對，如圖20C中所展示；使用一第七遮罩步驟(源極/汲極遮罩)藉由淺砷植入而分別地形成主體區域2014及LDD延伸2016中之經高摻雜源極區域218及汲極區域220，如圖20D中所展示；將電場氧化物2022沈積於該結構之一頂部表面上方以確保一場板2024與汲極延伸區域2016之表面之一預定義間距，如圖20E中所展示；使用一第八遮罩步驟(溝渠接觸遮罩)蝕刻一淺源極接觸溝渠2026且透過該溝渠底部植入BF2(插塞植入)以確保對主體及深P+區域之一良好歐姆接觸，如圖20E中所展示；沈積及燒結襯砌於溝渠接觸壁之矽化物膜2028(例如，Ti/WSix或Ti/TiN)以形成源極區域與主體區域之間的一電短路，如圖20E中所展 示。在燒結程序期間，在Si/Ti界面處形成矽化物(例如，TiSix)。此一接觸形成方法係熟習此項技術者所熟知；使用一第九遮罩步驟(場板(FPL)遮罩)圖案化該接觸矽化物層，從而允許一橫向延伸以與閘極結構重疊且在LDD/氧化物界面之鄰近處形成一場板，如圖20E中所展示；沈積一層間介電質膜(ILD)2030且應用一化學機械拋光步驟(CMP)或一替代平面化程序，以達成一實質上平面之頂部表面，如圖20F中所展示；使用一第十遮罩步驟(導通孔遮罩)來蝕刻導通孔開口以存取源極、汲極及閘極接觸區。用鎢插塞(Ti/TiN/W)或一替代導電材料填充導通孔，且應用一CMP步驟以再次平面化該頂部表面，如圖20F中所展示；及使用一第十一遮罩步驟(金屬遮罩)來沈積及圖案化一厚鋁層2032以形成具有源極、汲極及閘極匯流排結構之頂部電極，如圖20F中所展示。
如上文所論述，在此實施例中，一N通道LDMOS(NFET)電晶體之處理需要十一個遮罩層級(亦即，步驟)。如上文所提及，若省略閘極溝渠處理，則遮罩層級之數目可減小至十。可使用一選用遮罩以藉由蝕刻一深溝渠穿過作用層及經埋入氧化物且用氧化物及經摻雜多晶矽來填充該深溝渠而形成對基板之一電接觸。
為了使用同一程序流程形成一P通道MOSFET(PFET)，需要一額外遮罩子組。根據本發明之一說明性實施例，使用下列遮罩層級來進行專屬額外植入：P-BL、P-POLYDOP、P-BODY、P-LDD、P-S/D及P-CONT，其中P-BL係指經埋入層之一P型摻雜，且P-POLYDOP係指達成針對PFET裝置之多晶矽之P+摻雜之一遮罩層級。在此情形中，針對NFET裝置之多晶矽之N+摻雜使用一額外N-POLYDOP遮罩層 級。
因此，根據本發明之實施例，該例示性BiCMOS程序中之完整遮罩組包含最多18至20個層級。此程序流程允許圖9至圖19中所展示之所有例示性電子組件之一設計，該設計可用於製造一功率IC。
使用製造本文中所闡述之二極體功率裝置所需要之基本遮罩組之程序流程與上文針對BiCMOS技術所論述之程序流程相同。在一Nch MOSFET之情形中，該程序係基於具有一P-處置晶圓及一N-作用層之一SOI基板。在形成本文中所揭示之二極體結構時，此程序流程可包含下列主要步驟：基由蝕刻一溝渠穿過該作用層且用氧化物或氧化物與多晶矽之一組合來填充該溝渠而達成之橫向介電質隔離(LTI遮罩)；深植入硼以形成在接近於經埋入氧化物界面處具有一濃度峰值之一局域深P+井(BL遮罩)；圖案化一遮罩以界定閘極溝渠之位置(TRG遮罩-選用)；蝕刻具有經修圓之底部及頂部拐角之閘極溝渠，生長一熱閘極氧化物，及用多晶矽填充該溝渠(選用-針對如圖15至圖15B之僅包含閘極溝渠之結構)；藉由磷光體植入及退火來摻雜該經沈積之多晶矽，及將矽化物層沈積於頂部上；圖案化該多晶金屬矽化物層(POLY遮罩)；植入硼以形成自對準至針對PN二極體之多晶金屬矽化物層之邊緣且自對準至用於在肖特基二極體中形成一按鈕主體觸點之多晶金屬矽化物層開口之一主體區域。藉助一專屬熱退火來執行主體擴散；植入磷光體或砷以在多晶金屬矽化物層之另一邊緣處形成一經輕摻雜汲極延伸(稱為經輕摻雜汲極(LDD))(LDD遮罩)；藉由淺砷植入來形成經高摻雜陰極區域(S/D遮罩)； 沈積電場氧化物以確保閘極堆疊結構之一電隔離；蝕刻一淺源極(陽極)接觸溝渠(CONT遮罩)且透過溝渠底部植入BF2(插塞植入)以確保對主體及深P+區域之一良好歐姆接觸。
沈積及燒結襯砌於溝渠接觸壁之矽化物膜(例如，Ti/TiN)以形成陽極、主體與深P+區域之間的一電短路；圖案化該接觸矽化物層(FPL遮罩)；沈積一層間介電質膜(ILD)且應用化學機械拋光步驟(CMP)以達成一平面頂部表面；蝕刻導通孔開口以存取陽極、陰極及閘極接觸區(導通孔遮罩)。用鎢插塞(Ti/TiN/W)填充導通孔且應用CMP步驟以再次平面化該頂部表面。
執行一兩步式RTP退火以穩定肖特基接觸障壁。
沈積及圖案化厚Al層以形成具有陽極、陰極及閘極匯流排結構之頂部電極(金屬遮罩)。
如上文所論述，此技術需要少量遮罩層級。可使用一選用遮罩以藉由蝕刻一深溝渠穿過作用層及經埋入氧化物且用氧化物及經摻雜多晶矽來填充該深溝渠而形成對基板之一電接觸。
處理細節係熟習此項技術者所熟知，且因此將不再於本文中進一步詳細呈現。僅以實例而非限制之方式，在下文針對製作一例示性20伏特N通道MOSFET之情形列舉針對某些技術程序參數之說明性值：
￭SOI基板：經輕摻雜之處置晶圓(例如，<5e14cm-3)，0.3μm之經埋入氧化物，及具有約1e16cm-3之一摻雜之0.6μm作用膜。
￭經埋入之P + 井：具有2e13cm-2之一劑量及180keV之能量之硼植入物。
￭閘極溝渠：0.3μm寬，0.3μm深，及0.3μm長。
￭多晶金屬矽化物層：0.3μm多晶矽及0.1μm WSi2。多晶金屬矽化物條帶寬度為0.45μm以覆蓋閘極溝渠，或針對無閘極溝渠之NFET之情形為0.35μm
￭主體區域：具有3e13cm-2之一劑量及30keV之能量之硼植入物，後續接著具有4e13cm-2之一劑量及90keV之能量之一第二硼植入物，及在1000℃處之60分鐘退火。
￭LDD區域：具有6e12cm-2之一劑量及60keV之能量之磷光體植入物。
￭S/D區域：具有5e15cm-2之一劑量及30keV之能量之砷植入物。
￭接觸溝渠：0.4μm寬及0.25μm深。
￭矽化物膜：在800℃處退火之Ti(300埃)/TiN(800埃)。
￭插塞植入物：具有7e14cm-2之一劑量及30keV之能量之BF2植入物。
￭頂部金屬：圖案化有0.5μm金屬至金屬間距之AlSiCu(1.5μm厚度)。
製造如上文所論述之一NPN電晶體所需要之基本遮罩組可用於結合圖12A至圖12D或圖12E(視具體情況而定)如上文所闡述形成一功率SOI BJT。該程序係基於具有一P-處置晶圓及一N-作用層之一SOI基板，且可包含下列主要步驟：
基由蝕刻一溝渠穿過該作用層且用氧化物或氧化物與多晶矽之一組合來填充該溝渠而達成之橫向介電質隔離(LTI遮罩)。
深植入硼以形成在接近於經埋入氧化物界面處具有一濃度峰值之一局域深P+井(BL遮罩)。
藉由磷光體植入及退火來沈積及摻雜一多晶矽層。將矽化物層沈積於頂部上。
圖案化該多晶金屬矽化物層(POLY遮罩)。
植入硼以形成自對準至多晶金屬矽化物層之邊緣之一基極區域(BODY遮罩)。藉助一專屬熱退火來執行基極擴散(例如，1000℃達60分鐘)以在基極/閘極之整個長度下驅動植入物。
植入磷或砷以形成一經輕摻雜集極延伸(類似於LDMOS結構中之LDD)(LDD遮罩)。
藉由淺砷植入來形成經高摻雜之射極及集極區域(S/D遮罩)。
蝕刻一淺按鈕接觸溝渠(CONT遮罩)且透過溝渠底部植入BF2(插塞植入)以確保對基極及深P+區域之一良好歐姆接觸。
沈積及燒結襯砌於溝渠接觸壁之矽化物膜(例如Ti/TiN)。
圖案化該接觸矽化物層，從而允許一橫向延伸與多晶金屬矽化物層之一小重疊，以形成深P+井與多晶金屬矽化物層之間的一電接觸。如同該MOSFET程序，此同一遮罩可用於界定選用之場板延伸。
沈積一層間介電質膜(ILD)且應用化學機械拋光步驟(CMP)以達成一平面頂部表面。
蝕刻導通孔開口以存取射極、集極及基極接觸區(導通孔遮罩)。用鎢插塞(Ti/TiN/W)填充導通孔且應用CMP步驟以再次平面化該頂部表面。
沈積及圖案化厚Al層以形成具有射極、集極及基極匯流排結構之頂部電極(金屬遮罩)。
如上文所論述，一NPN電晶體之處理需要10個遮罩層級。可使用一選用遮罩以藉由蝕刻一深溝渠穿過作用層及經埋入氧化物且用氧化物及經摻雜多晶矽來填充該深溝渠而形成對基板之一電接觸。
為了在同一程序流程中形成一PNP BJT，必須使用一經修改之遮罩子組。使用下列遮罩層級來實現專屬、額外植入：P-BL、P-POLYDOP、P-BODY、P-LDD、P-S/D及P-CONT。
兩種類型之BJT電晶體皆可整合於如對SOI-BiCMOS之揭示內容中所論述具有最多18個遮罩層級之一SOI-BiCMOS程序流程內。此程序流程允許設計可用於製造一功率IC之各種各樣的電子組件。
處理細節係熟習此項技術者所熟知。上文針對用作一實例之一20V BiCMOS技術之情形列舉臨界技術參數之值。
在實施例中，將源極及汲極匯流排放置於電晶體作用單元之相對端處，其中藉由多晶金屬矽化物層形成之一閘極匯流排沿著佈局之中心延伸。該等源極及汲極金屬觸點具有一交錯指狀結構，且其節距等於如(舉例而言)圖9A、圖10、圖10A、圖11或圖19中所展示之一個作用單元之節距。預定義數目個作用單元透過匯流排結構連接在一起至具有數百微米之橫向尺寸之一大的巨集單元(例如300×300μm)。此巨集單元方法達成可藉由預定義巨集單元之重複及連接而比例縮放至一大的面積(例如1mm2至5mm2)之一電晶體佈局。舉例而言，在2008年11月4日發佈之美國專利第7,446,375號中闡述用於形成包括大量個別作用單元(例如，棋盤佈局)之巨集單元且將彼等巨集單元一起重複分群以用作一個別裝置之各種技術，該美國專利之整個內容以引用的方式併入本文中。然而，不同於描述具有至一後側電極之垂直電流流動之一裝置之'375專利，本發明LDMOS功率裝置實施例(其採用橫向電流流動)之源極及汲極端子以及源極及汲極匯流排兩者將形成於半導體基板之一頂部側上。應瞭解，此巨集單元方法可適用於本文中所揭示之所有功率裝置，包含MOSFET及BJT電晶體及二極體。
根據本發明之實施例達成之特徵及優勢包含不限於下列各項中之一或多者，但一既定實施例可未必包含所有此等特徵或未必僅包含此等特徵：￭開發BiCMOS程序之唯一態樣，如同藉助同一組程序步驟來製造所有積體功率裝置； ￭深的經埋入井之摻雜及放置界定所有SOI功率裝置內之崩潰電壓及突崩碰撞離子化之位置；亦即，一箝位二極體有效地整合於該裝置中，藉此確保高的耐突崩性；￭以最小化SMPS應用中之SOI-LDMOS功率損失之一目的來界定BiCMOS程序流程。藉由修改SOI-LDMOS結構而獲得其他功率裝置，如PN二極體、肖特基二極體及BJT；￭藉由自N通道LDMOS結構移除N+源極區域而獲得PN二極體；￭藉由自PN二極體結構移除P主體區域而獲得肖特基二極體；￭藉由移除源極區域與主體區域之間的電短路而獲得雙極型電晶體。將閘極堆疊連接至主體區域且建構用作一基極端子之一電流匯流排結構；￭採用晶片級封裝(CSP)或晶圓級封裝(WLP)以在所完成之晶粒之頂部表面上形成電流端子。
在一佈線封裝之情形中，電流匯流排條帶通向端子襯墊區。若採用具有一較小產品佔用面積及較少寄生分量(如封裝電阻及電感)之優勢之一晶片級總成(CSP或WLP)，則電流匯流排結構2308(舉例而言，其對應於閘極、汲極及源極頂部電極2032)(或在二極體或BJT實施例之情形中之其他觸點)透過導通孔2302及一再分佈層2304連接至一球觸點2306，如圖23中示意性地展示。返回至關於巨集單元之先前論述，個別源極、汲極及閘極匯流排可連接至多個相似或一致裝置之多個源極、汲極及閘極端子，藉此允許彼多個裝置作為一單個巨集裝置操作。多個巨集單元裝置則可連接在一起以便由(舉例而言)再分佈層2304操作為一個功率裝置。亦即，一個別觸點2306可針對閘極及汲極觸點2306連接至(舉例而言)多個源極匯流排2308及諸如此類。
如先前提及，本發明之實施例之一重要益處係容易地促進在與用於實施一功率控制裝置之對應控制電路相同的矽基板上整合功率電 路及/或組件(例如，驅動器及功率切換器)的能力。僅以實例而非限制之方式，圖21A至圖22E係繪示根據本發明之一實施例用於將兩個功率裝置整合於同一基板上之一例示性BiCMOS處理流程之至少一部分之剖面圖。具體而言，圖21A至圖22E概念性地圖解說明利用相同程序步驟以將一功率N通道MOSFET及一功率肖特基二極體整合於一共同SOI基板上之一例示性程序流程。可在同一程序步驟序列內製作諸如(舉例而言)PN二極體及BJT之其他裝置。
參照圖21A，展示至少兩個作用區域2102及2104。在此實施例中，其中將形成若干裝置之作用區域2102及2104中之每一者包括藉由一橫向隔離溝渠2108分離之各別N-作用區域2106，但在其他實施例中，作用區域2106可係為一不同導電類型。橫向隔離溝渠2108用於分離用於形成其他裝置及/或結構之其他毗鄰作用區域2106。使用先前闡述之程序步驟，在一共同經埋入氧化物層2110上形成作用區域2106，該共同經埋入氧化物層又形成於一N型或P型基板2112上。經埋入之P+井2114形成於各別N-作用區域2106中，鄰近經埋入氧化物層2110與作用區域之間的一界面。
在圖21B中，一閘極氧化物層2120形成於SOI結構之表面上方。一多晶矽層2122沈積於閘極氧化物層2120上且經圖案化以形成閘極結構。矽化物層2124視情況沈積於多晶矽閘極結構2122上。然後藉由摻雜經埋入井2114之至少一部分上方之作用區域2106來形成P主體區域2116，藉此使用於形成P主體區域之P植入物自對準至多晶金屬矽化物區域之一個邊緣。N區域2118亦形成於作用層2106中。在作用區域2102中，N區域2118形成於經分配以建構一MOSFET結構之P主體區域2116之間(例如，在圖10中展示之NMOS裝置1000)。如圖14B中先前所展示，同一植入步驟用於在一肖特基二極體之結構中形成N區域2118。圖21C展示形成於P主體區域2116及N區域2118中之經摻雜N+ 區域2126。氧化物層2128形成於SOI結構之上部表面之至少一部分上方。
參照圖21D，實質上垂直地穿過氧化物層2128、P主體區域2116且接觸經埋入P+井2114形成溝渠2130。矽化物或鈦/氮化鈦層2132形成於溝渠2130之側壁及一底壁上。襯砌於溝渠2130之矽化物層2132接觸P主體區域2116中之N+經摻雜區域2126。屏蔽場板2134(其在此實施例中形成為襯砌於溝渠2130之矽化物層2132之橫向延伸)與閘極結構重疊且變得緊鄰近於沿著N作用區域2118之氧化物界面。氧化物層2136則形成於SOI結構之上部表面之至少一部分上方。圖21E繪示經蝕刻以形成接觸溝渠(亦即，導通體)之氧化物層2136，該等接觸溝渠實質性填充有一金屬(例如，鋁)或一替代導電金屬以形成裝置觸點2138。
本發明之實施例之至少一部分可以一積體電路實施。在形成積體電路時，通常在一半導體晶圓之一表面上以一重複型樣製作一致的晶粒。每一晶粒包含本文中所闡述之至少一個裝置，且可包含其他結構及/或電路。自該晶圓分割或切割個別晶粒，然後將該個別晶粒封裝成一積體電路。熟習此項技術者將知曉如何切割晶圓及封裝晶粒以產生積體電路。將如此製造之積體電路視為本發明之部分。
根據本發明之實施例之一積體電路本質上可用於其中可採用功率管理技術之任一應用及/或電子系統中。用於實施根據本發明之實施例之技術之適合應用及系統可包含(但不限於)便攜式裝置(包含智慧電話)、膝上型電腦及平板電腦計算裝置、小筆電等。將併入有此等積體電路之系統視為本發明之實施例之部分。在本文中所提供之本發明之實施例之教示下，熟習此項技術者將能夠預計本發明之實施例之技術之其他實施方案及應用。
本文中所闡述之本發明之實施例之圖解說明意欲提供各種實施 例之結構之一般理解，且其並不意欲充當可利用本文中所闡述之結構之設備及系統之所有元件及特徵之一完整說明。在本文中之教示下，諸多其他實施例將變得對熟習此項技術者顯而易見；利用且自其導出其他實施例，以使得在不背離本發明之範疇之情況下可做出結構及邏輯替換及改變。該等圖式亦僅係代表性的且未按比例繪製。相應地，應將說明書及圖式視為具有一說明意義而非一約束意義。
發明性標的物之實施例僅出於便利之目的而在本文中個別地及/或共同地由術語「實施例」指代，且若事實上已展示一個以上實施例或發明性概念，則並不意欲將此申請案之範疇限制於任一單項實施例或發明性概念。因此，儘管已在本文中圖解說明及闡述特定實施例，但應理解，可用達成同一目的之一配置替換所展示之特定實施例；亦即，此揭示內容意欲涵蓋各種實施例之任何及所有變更或變化。在本文中之教示下，上述實施例之組合及本文中未具體闡述之其他實施例將變得對熟習此項技術者顯而易見。
摘要部分經提供以符合37 C.F.R.§ 1.72(b)，其要求將允許讀者快速獲取該技術揭示內容之本質之一摘要。提交本摘要係基於以下理解：其並非用於解譯或限定申請專利範圍之範疇或含義。另外，在前述較佳實施例之詳細說明中，可看出，出於簡化該揭示內容之目的而將各種特徵一起分群於一單項實施例中。揭示內容之此方法不應解譯為反映以下內容之一意圖：所主張實施例需要比每一請求項中所明確陳述之特徵更多的特徵。
在本文中所提供之本發明之實施例之教示下，熟習此項技術者將能夠預計本發明之實施例之技術之其他實施方案及應用。儘管已參考附圖在本文中闡述本發明之說明性實施例，但應理解，本發明之實施例不限於彼等精確實施例，且在不背離本發明之範疇之情況下熟習此項技術者可做出各種其他改變及修改。

Claims (23)

  1. 一種包括至少一個PN二極體功率裝置之半導體結構，該半導體結構包括：一第一絕緣層，其形成於一基板上；一作用區域，其形成於該第一絕緣層之至少一部分上；一經埋入井，其具有一第一導電類型且形成於該作用區域中；一陽極區域，其穿過該作用區域之一上部表面形成於該作用區域中，該陽極區域電連接至該經埋入井；一陰極區域，其具有一第二導電類型且形成於該作用區域中鄰近該作用區域之該上部表面且與該陽極區域橫向間隔開；一主體區域，其具有該第一導電類型且形成於該作用區域中於該陽極區域與該陰極區域之間在該經埋入井之至少一部分上，其中該陽極區域電連接至該主體區域；一陰極端子，其形成於該作用區域之一上部表面上且與該陰極區域電連接；一陽極端子，其與該陽極區域電連接；且該經埋入井經組態以結合該作用區域形成一箝位二極體，該箝位二極體操作以將一突崩潰區域定位於該經埋入井與該陰極端子之間，該PN二極體功率裝置之一崩潰電壓隨該經埋入井之一或多個特性而變，其中該經埋入井係形成鄰近於該第一絕緣層及該作用區域之間的一界面且沿該絕緣層自該陽極區域延伸至鄰近於該陰極區域之一位置，其中該主體區域係形成於該經埋入井上方且沿該作用區域之該上部表面延伸至該陽極區域以電接觸該陽極區域及該陰極區域以形成具有該陰極區域之該PN 二極體功率裝置之一PN接面。
  2. 如請求項1之半導體結構，其中該二極體進一步包括：一閘極結構，其形成於該作用區域上方鄰近該作用區域之該上部表面且至少部分地在該陰極區域與該陽極區域之間，該閘極結構與該陽極端子電連接，該閘極結構重疊於介於該陽極區域與該主體區域之間的該PN接面，該閘極結構經組態以控制鄰近該陰極區域與該主體區域之間的該PN接面之一電場分佈。
  3. 如請求項2之半導體結構，其進一步包括：一屏蔽結構，其經形成鄰近該作用區域之該上部表面在該閘極結構與該陰極區域之間，該屏蔽結構包括經組態以控制沿著一頂部氧化物界面遠離最接近於該陰極端子之該閘極結構之一邊緣之一電場分佈的一場板。
  4. 如請求項3之半導體結構，其中該屏蔽結構電連接至該閘極結構且形成為接觸該陽極端子之一導電層之一延伸。
  5. 如請求項4之半導體結構，其中該導電層在該陽極區域中將該陽極端子電連接至該經埋入井。
  6. 如請求項5之半導體結構，其進一步包括形成於該作用層中之一陽極溝渠，其中該陽極端子至少部分地形成於該陽極溝渠中且藉由該導電層在該陽極溝渠中電連接至該經埋入井及該主體區域。
  7. 如請求項6之半導體結構，其中該導電層包括該陽極溝渠之壁上之一導電襯裡。
  8. 如請求項3之半導體結構，其中該屏蔽結構電連接至該陽極端子，該半導體結構進一步包括穿過該屏蔽結構且至少部分地在該屏蔽結構之一上部表面上形成之一觸點，該觸點將該閘極結構電連接至該陽極端子。
  9. 如請求項1之半導體結構，其進一步包括形成於該作用層中之一陽極溝渠，其中該陽極端子至少部分地形成於該陽極溝渠中且藉由一導電層在該陽極溝渠中電連接至該經埋入井及該主體區域。
  10. 如請求項9之半導體結構，其中該二極體進一步包括：一閘極結構，其形成於該作用區域上方鄰近該作用區域之該上部表面且至少部分地在該陰極區域與該陽極區域之間，該閘極結構與該陽極端子電連接，該閘極結構重疊於介於該陽極區域與該主體區域之間的該PN接面，該閘極結構經組態以控制鄰近該陰極區域與該主體區域之間的該PN接面之一電場分佈，其中該陽極端子藉由該陽極溝渠外部之該導電層之一橫向延伸而電連接至該閘極結構。
  11. 如請求項1之半導體結構，其中該經埋入井經形成鄰近該第一絕緣層與該作用區域之間的一界面。
  12. 如請求項1之半導體結構，其中該至少一個PN二極體功率裝置包括形成於其中且組織成一巨集單元之複數個該至少一個PN二極體功率裝置，且該半導體結構包括連接在一起以作為一單個PN二極體功率裝置操作之複數個該等巨集單元。
  13. 如請求項1之半導體結構，其中該至少一個PN二極體功率裝置包括形成於其中且透過一匯流排結構連接在一起以作為一單個PN二極體功率裝置操作之複數個相似的PN二極體功率裝置，其中該半導體結構係一晶片級總成之部分，該晶片級總成包括將該匯流排結構耦合至陽極及陰極外部觸點之一再分佈層。
  14. 一種包括至少一個肖特基二極體功率裝置之半導體結構，該半導體結構包括：一第一絕緣層，其形成於一基板上； 一作用區域，其形成於該第一絕緣層之至少一部分上；一經埋入井，其具有一第一導電類型且形成於該作用區域中；一陰極區域，其具有一第二導電類型且形成於該作用區域中鄰近該作用區域之上部表面；一陰極端子，其形成於作用區域之一上部表面上且與該陰極區域電連接；一陽極端子，其在與該陰極區域橫向間隔開之一區域處與該作用區域及該經埋入井電連接，其中一肖特基障壁形成於該陽極端子與該作用區域之間；且該經埋入井經組態以結合該作用區域形成一箝位二極體，該箝位二極體操作以將一突崩潰區域定位於該經埋入井與該陰極端子之間，該肖特基二極體功率裝置之一崩潰電壓隨該經埋入井之一或多個特性而變。
  15. 如請求項14之半導體結構，其中該肖特基二極體進一步包括：一閘極結構，其形成於該作用區域上方鄰近該作用區域之該上部表面且至少部分地在該陰極端子與該陽極端子之間，該閘極結構與該經埋入井及該陰極區域之至少一部分重疊，該閘極結構與該陽極端子電連接，其中該閘極結構經組態以控制鄰近該陰極區域與該作用區域之間的接面之一電場分佈。
  16. 如請求項15之半導體結構，其進一步包括一屏蔽結構，該屏蔽結構經形成鄰近該作用區域之該上部表面在該閘極結構與該陰極區域之間，該屏蔽結構包括經組態以控制沿著一頂部氧化物界面遠離最接近於該陰極端子之該閘極結構之一邊緣之一電場分佈之一場板。
  17. 如請求項16之半導體結構，其中該陰極區域包含部分地下伏於 該閘極結構下且延伸至一經較重摻雜之第二陰極植入區域之一第一陰極植入區域，該經較重摻雜之第二陰極植入區域電接觸至該陰極端子且下伏於其下。
  18. 如請求項17之半導體結構，其進一步包括鄰近該作用區域之一上部表面形成之該第二導電類型之一植入區域，該第二導電類型之該植入區域部分地下伏於該閘極結構下且延伸以下伏於該陽極端子下且實現對該陽極端子之電接觸，其中該肖特基障壁形成於該陽極端子與該第二導電類型之該植入區域之間。
  19. 如請求項14之半導體結構，其中該肖特基二極體進一步包括：該第二導電類型之一植入區域，其經形成鄰近該作用區域之一上部表面且實現對該陽極端子之電接觸，其中該肖特基障壁形成於該陽極端子與該第二導電類型之該植入區域之間；一閘極結構，其形成於該作用區域上方鄰近該作用區域之該上部表面且至少部分地在該陰極端子與該陽極端子之間，該閘極結構與該第二導電類型之該植入區域、該作用區域及該陰極區域之至少一部分重疊，該閘極結構與該陽極端子電隔離，閘極結構操作以在該陰極端子之一所施加阻遏偏壓下誘發該電場分佈之一收縮，以藉此在阻遏條件下屏蔽該肖特基障壁免受大於一所規定位準之一電場。
  20. 如請求項19之半導體結構，其中該肖特基二極體進一步包括：複數個溝渠結構，其實質上垂直穿過該作用區域且進入至該經埋入井中而形成，該等溝渠中之每一者包含其上形成有一絕緣材料之側壁及一底壁，該等溝渠中之每一者填充有一導電材料，該等溝渠與該閘極結構連接，其中施加至該閘極結構之一電壓操作以調變流動於該等溝渠中之至少兩者之間的一傳導電流，隨該所施加電壓而變地控制該傳導電流之一振幅。
  21. 如請求項14之半導體結構，其中該經埋入井經形成鄰近該第一絕緣層與該作用區域之間的一界面。
  22. 如請求項14之半導體結構，其中該至少一個肖特基二極體功率裝置包括形成於其中且組織成一巨集單元之複數個該至少一個肖特基二極體功率裝置，且該半導體結構包括連接在一起以作為一單個肖特基二極體功率裝置操作之複數個該等巨集單元。
  23. 如請求項14之半導體結構，其中該至少一個肖特基二極體功率裝置包括形成於其中且透過一匯流排結構連接在一起以作為一單個肖特基二極體功率裝置操作之複數個相似的肖特基二極體功率裝置，其中該半導體結構係一晶片級總成之部分，該晶片級總成包括將該匯流排結構耦合至陽極及陰極外部觸點之一再分佈層。
TW102127300A 2012-07-31 2013-07-30 於共同基板上之功率裝置整合 TWI634620B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201261677660P 2012-07-31 2012-07-31
US61/677,660 2012-07-31
US13/887,704 2013-05-06
US13/887,704 US8994105B2 (en) 2012-07-31 2013-05-06 Power device integration on a common substrate
US13/939,451 US9412881B2 (en) 2012-07-31 2013-07-11 Power device integration on a common substrate
US13/939,451 2013-07-11

Publications (2)

Publication Number Publication Date
TW201409610A TW201409610A (zh) 2014-03-01
TWI634620B true TWI634620B (zh) 2018-09-01

Family

ID=50024637

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102127300A TWI634620B (zh) 2012-07-31 2013-07-30 於共同基板上之功率裝置整合

Country Status (2)

Country Link
US (7) US9412881B2 (zh)
TW (1) TWI634620B (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941962B2 (en) * 2011-09-13 2015-01-27 Fsp Technology Inc. Snubber circuit and method of using bipolar junction transistor in snubber circuit
US10290702B2 (en) 2012-07-31 2019-05-14 Silanna Asia Pte Ltd Power device on bulk substrate
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
KR102100928B1 (ko) * 2013-10-17 2020-05-15 삼성전자주식회사 고전자 이동도 트랜지스터
US20150118810A1 (en) * 2013-10-24 2015-04-30 Madhur Bobde Buried field ring field effect transistor (buf-fet) integrated with cells implanted with hole supply path
TWI546970B (zh) * 2014-05-13 2016-08-21 帥群微電子股份有限公司 半導體元件的終端結構及其製造方法
DE102014117556B4 (de) 2014-11-28 2020-10-01 Infineon Technologies Dresden Gmbh Halbleitervorrichtung mit vergrabenem dotiertem Bereich und Kontaktstruktur und Verfahren
US20160247879A1 (en) * 2015-02-23 2016-08-25 Polar Semiconductor, Llc Trench semiconductor device layout configurations
KR101975630B1 (ko) * 2015-04-03 2019-08-29 매그나칩 반도체 유한회사 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법
US10784372B2 (en) * 2015-04-03 2020-09-22 Magnachip Semiconductor, Ltd. Semiconductor device with high voltage field effect transistor and junction field effect transistor
US10205024B2 (en) * 2016-02-05 2019-02-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure having field plate and associated fabricating method
DE102016106872A1 (de) * 2016-04-13 2017-10-19 Infineon Technologies Ag Verfahren zum herstellen einer integrierten schaltung einschliesslich eines lateralen graben-transistors und eines logikschaltungselements
US10032750B2 (en) 2016-06-29 2018-07-24 International Business Machines Corporation Integrated DC-DC power converters through face-to-face bonding
US9923059B1 (en) 2017-02-20 2018-03-20 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors
US10083897B2 (en) 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US10177243B1 (en) * 2017-06-19 2019-01-08 Nxp B.V. Extended drain NMOS transistor with buried P type region
US10622492B2 (en) 2018-01-15 2020-04-14 Qualcomm Incorporated Variable capacitor flat-band voltage engineering
US10770391B2 (en) 2018-03-27 2020-09-08 Qualcomm Incorporated Transistor with gate extension to limit second gate effect
KR102458310B1 (ko) 2018-06-19 2022-10-24 삼성전자주식회사 집적회로 소자
US10707345B2 (en) 2018-09-13 2020-07-07 Silanna Asia Pte Ltd Laterally diffused MOSFET with low Rsp*Qg product
US10985244B2 (en) * 2019-06-25 2021-04-20 Globalfoundries U.S. Inc. N-well resistor
TWI719538B (zh) * 2019-07-17 2021-02-21 世界先進積體電路股份有限公司 半導體裝置及其操作方法
US10964788B1 (en) 2019-11-27 2021-03-30 Vanguard International Semiconductor Corporation Semiconductor device and operating method thereof
TWI818371B (zh) 2021-01-12 2023-10-11 立錡科技股份有限公司 高壓元件及其製造方法
CN117751455A (zh) * 2021-08-05 2024-03-22 罗姆股份有限公司 半导体器件
WO2023161384A1 (en) * 2022-02-25 2023-08-31 Analog Devices International Unlimited Company Monolithically integrated lateral bipolar device with voltage scaling

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773852A (en) * 1996-03-20 1998-06-30 Korea Electronics Co., Ltd. Shorted anode lateral insulated gate bipolar transistor
US20040245633A1 (en) * 2003-06-03 2004-12-09 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures
US20060261382A1 (en) * 2005-05-19 2006-11-23 Khemka Vishnu K Structure and method for RESURF diodes with a current diverter
US20070034942A1 (en) * 2005-08-12 2007-02-15 Shuming Xu Power LDMOS transistor
US20080122006A1 (en) * 2002-09-29 2008-05-29 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20080246086A1 (en) * 2005-07-13 2008-10-09 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
US20100127347A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Shielding for integrated capacitors
US20110303976A1 (en) * 2010-06-15 2011-12-15 Texas Instruments Incorporated High voltage channel diode

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4738936A (en) 1983-07-01 1988-04-19 Acrian, Inc. Method of fabrication lateral FET structure having a substrate to source contact
US5386136A (en) * 1991-05-06 1995-01-31 Siliconix Incorporated Lightly-doped drain MOSFET with improved breakdown characteristics
US5559044A (en) 1992-09-21 1996-09-24 Siliconix Incorporated BiCDMOS process technology
US5548150A (en) 1993-03-10 1996-08-20 Kabushiki Kaisha Toshiba Field effect transistor
DE69326543T2 (de) 1993-04-28 2000-01-05 Co.Ri.M.Me. Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania Monolithisch integrierte Struktur einer elektronischen Vorrichtung mit einer bestimmten unidirektionalen Konduktionsschwellenspannung
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5378912A (en) 1993-11-10 1995-01-03 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a lateral drift region
US5382818A (en) 1993-12-08 1995-01-17 Philips Electronics North America Corporation Lateral semiconductor-on-insulator (SOI) semiconductor device having a buried diode
US6078090A (en) 1997-04-02 2000-06-20 Siliconix Incorporated Trench-gated Schottky diode with integral clamping diode
US6049108A (en) 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
DE19647324B4 (de) 1995-11-15 2013-06-27 Denso Corporation Halbleiterbauelement
US6831331B2 (en) 1995-11-15 2004-12-14 Denso Corporation Power MOS transistor for absorbing surge current
US5814858A (en) * 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
US5818084A (en) 1996-05-15 1998-10-06 Siliconix Incorporated Pseudo-Schottky diode
KR100225411B1 (ko) 1997-03-24 1999-10-15 김덕중 LDMOS(a lateral double-diffused MOS) 트랜지스터 소자 및 그의 제조 방법
US5889310A (en) 1997-04-21 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with high breakdown voltage island region
US5869875A (en) 1997-06-10 1999-02-09 Spectrian Lateral diffused MOS transistor with trench source contact
JP3405681B2 (ja) 1997-07-31 2003-05-12 株式会社東芝 半導体装置
US6692998B2 (en) 2000-11-30 2004-02-17 International Business Machines Corporation Integrated high quality diode
US6794719B2 (en) 2001-06-28 2004-09-21 Koninklijke Philips Electronics N.V. HV-SOI LDMOS device with integrated diode to improve reliability and avalanche ruggedness
WO2003006699A1 (fr) 2001-07-13 2003-01-23 Nkk Corporation Tube d'acier a resistance elevee, superieure a celle de la norme api x6
AU2002337297A1 (en) 2001-10-23 2003-05-06 Cambridge Semiconductor Limited Lateral semiconductor-on-insulator structure and corresponding manufacturing methods
KR100867574B1 (ko) * 2002-05-09 2008-11-10 페어차일드코리아반도체 주식회사 고전압 디바이스 및 그 제조방법
US7719054B2 (en) 2006-05-31 2010-05-18 Advanced Analogic Technologies, Inc. High-voltage lateral DMOS device
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
KR100948139B1 (ko) * 2003-04-09 2010-03-18 페어차일드코리아반도체 주식회사 높은 브레이크다운 전압 및 낮은 온 저항을 위한 다중전류 이동 경로를 갖는 수평형 이중-확산 모스 트랜지스터
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US7273771B2 (en) 2004-02-09 2007-09-25 International Rectifier Corporation Common MOSFET process for plural devices
JP2006019518A (ja) 2004-07-01 2006-01-19 Seiko Instruments Inc 横型トレンチｍｏｓｆｅｔ
EP1742270A1 (en) 2005-07-06 2007-01-10 STMicroelectronics S.r.l. MOS transistor having a trench-gate and method of manufacturing the same
US7589378B2 (en) 2005-07-13 2009-09-15 Texas Instruments Lehigh Valley Incorporated Power LDMOS transistor
US7282765B2 (en) 2005-07-13 2007-10-16 Ciclon Semiconductor Device Corp. Power LDMOS transistor
US7235845B2 (en) 2005-08-12 2007-06-26 Ciclon Semiconductor Device Corp. Power LDMOS transistor
US7560808B2 (en) 2005-10-19 2009-07-14 Texas Instruments Incorporated Chip scale power LDMOS device
DE102006053145B4 (de) 2005-11-14 2014-07-10 Denso Corporation Halbleitervorrichtung mit Trennungsbereich
US20070170897A1 (en) 2006-01-26 2007-07-26 Advanced Analogic Technologies, Inc. High-Frequency Power MESFET Buck Switching Power Supply
US7446375B2 (en) 2006-03-14 2008-11-04 Ciclon Semiconductor Device Corp. Quasi-vertical LDMOS device having closed cell layout
US7842568B2 (en) 2006-06-28 2010-11-30 Great Wall Semiconductor Corporation Lateral power semiconductor device for high frequency power conversion system, has isolation layer formed over substrate for reducing minority carrier storage in substrate
US7605446B2 (en) * 2006-07-14 2009-10-20 Cambridge Semiconductor Limited Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation
US10062788B2 (en) 2008-07-30 2018-08-28 Maxpower Semiconductor Inc. Semiconductor on insulator devices containing permanent charge
US7952145B2 (en) 2007-02-20 2011-05-31 Texas Instruments Lehigh Valley Incorporated MOS transistor device in common source configuration
JP2008251067A (ja) 2007-03-29 2008-10-16 Hitachi Ltd ディスクアレイ装置
US7745846B2 (en) 2008-01-15 2010-06-29 Ciclon Semiconductor Device Corp. LDMOS integrated Schottky diode
US8174071B2 (en) 2008-05-02 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage LDMOS transistor
US7626231B1 (en) 2008-06-23 2009-12-01 Force Mos Technology Co., Ltd. Integrated trench MOSFET and junction barrier schottky rectifier with trench contact structures
US20100171543A1 (en) 2009-01-08 2010-07-08 Ciclon Semiconductor Device Corp. Packaged power switching device
US8101993B2 (en) 2009-03-18 2012-01-24 Force Mos Technology Co., Ltd. MSD integrated circuits with shallow trench
US7898026B2 (en) 2009-03-23 2011-03-01 Force Mos Technology Co., Ltd. LDMOS with double LDD and trenched drain
JP2010258210A (ja) 2009-04-24 2010-11-11 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP5503897B2 (ja) 2009-05-08 2014-05-28 三菱電機株式会社 半導体装置
US8138049B2 (en) 2009-05-29 2012-03-20 Silergy Technology Fabrication of lateral double-diffused metal oxide semiconductor (LDMOS) devices
JP5534298B2 (ja) * 2009-06-16 2014-06-25 ルネサスエレクトロニクス株式会社 半導体装置
US8120105B2 (en) 2009-07-31 2012-02-21 Micrel, Inc. Lateral DMOS field effect transistor with reduced threshold voltage and self-aligned drift region
US8174070B2 (en) 2009-12-02 2012-05-08 Alpha And Omega Semiconductor Incorporated Dual channel trench LDMOS transistors and BCD process with deep trench isolation
US8859337B2 (en) 2009-12-15 2014-10-14 Soitec Thermal matching in semiconductor devices using heat distribution structures
US20110148376A1 (en) 2009-12-23 2011-06-23 Texas Instruments Incorporated Mosfet with gate pull-down
US8547162B2 (en) 2009-12-23 2013-10-01 Texas Instruments Incorporated Integration of MOSFETs in a source-down configuration
JP5043990B2 (ja) * 2010-06-18 2012-10-10 シャープ株式会社 半導体装置およびその製造方法
US8722503B2 (en) 2010-07-16 2014-05-13 Texas Instruments Incorporated Capacitors and methods of forming
US8217452B2 (en) 2010-08-05 2012-07-10 Atmel Rousset S.A.S. Enhanced HVPMOS
US8669613B2 (en) 2010-09-29 2014-03-11 Alpha & Omega Semiconductor, Inc. Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method
US8614480B2 (en) 2011-07-05 2013-12-24 Texas Instruments Incorporated Power MOSFET with integrated gate resistor and diode-connected MOSFET
US9412881B2 (en) 2012-07-31 2016-08-09 Silanna Asia Pte Ltd Power device integration on a common substrate
US8928116B2 (en) 2012-07-31 2015-01-06 Silanna Semiconductor U.S.A., Inc. Power device integration on a common substrate
US8674440B2 (en) 2012-07-31 2014-03-18 Io Semiconductor Inc. Power device integration on a common substrate
US8994105B2 (en) 2012-07-31 2015-03-31 Azure Silicon LLC Power device integration on a common substrate
US9412911B2 (en) 2013-07-09 2016-08-09 The Silanna Group Pty Ltd Optical tuning of light emitting semiconductor junctions

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5773852A (en) * 1996-03-20 1998-06-30 Korea Electronics Co., Ltd. Shorted anode lateral insulated gate bipolar transistor
US20080122006A1 (en) * 2002-09-29 2008-05-29 Advanced Analogic Technologies, Inc. Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology
US20040245633A1 (en) * 2003-06-03 2004-12-09 Martin Alter Integrating chip scale packaging metallization into integrated circuit die structures
US20060261382A1 (en) * 2005-05-19 2006-11-23 Khemka Vishnu K Structure and method for RESURF diodes with a current diverter
US20080246086A1 (en) * 2005-07-13 2008-10-09 Ciclon Semiconductor Device Corp. Semiconductor devices having charge balanced structure
US20070034942A1 (en) * 2005-08-12 2007-02-15 Shuming Xu Power LDMOS transistor
US20100127347A1 (en) * 2008-11-21 2010-05-27 Xilinx, Inc. Shielding for integrated capacitors
US20110303976A1 (en) * 2010-06-15 2011-12-15 Texas Instruments Incorporated High voltage channel diode

Also Published As

Publication number Publication date
US9412881B2 (en) 2016-08-09
US20160343802A1 (en) 2016-11-24
US20220208964A1 (en) 2022-06-30
US11791377B2 (en) 2023-10-17
TW201409610A (zh) 2014-03-01
US9825124B2 (en) 2017-11-21
US10290703B2 (en) 2019-05-14
US20230420497A1 (en) 2023-12-28
US8994115B2 (en) 2015-03-31
US20140291762A1 (en) 2014-10-02
US20180069077A1 (en) 2018-03-08
US20140035047A1 (en) 2014-02-06
US20190245034A1 (en) 2019-08-08
US11302775B2 (en) 2022-04-12

Similar Documents

Publication Publication Date Title
TWI634620B (zh) 於共同基板上之功率裝置整合
TWI443836B (zh) 於共同基板上之功率裝置整合
TWI623083B (zh) 於共同基板上之功率裝置整合
US10290702B2 (en) Power device on bulk substrate
US8994105B2 (en) Power device integration on a common substrate
EP2880688B1 (en) Power device integration on a common substrate
US10249759B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors
US10535730B2 (en) High voltage metal-oxide-semiconductor (HVMOS) device integrated with a high voltage junction termination (HVJT) device
US8193583B2 (en) Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method
US11335627B2 (en) Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
US11670693B2 (en) Trench gate field-effect transistors with drain runner
CN104769715B (zh) 共用衬底上的功率裝置集成