JP2010205978A - 半導体装置、及び該半導体装置を備えた実装体 - Google Patents
半導体装置、及び該半導体装置を備えた実装体 Download PDFInfo
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- JP2010205978A JP2010205978A JP2009050573A JP2009050573A JP2010205978A JP 2010205978 A JP2010205978 A JP 2010205978A JP 2009050573 A JP2009050573 A JP 2009050573A JP 2009050573 A JP2009050573 A JP 2009050573A JP 2010205978 A JP2010205978 A JP 2010205978A
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- barrier metal
- insulating film
- interlayer insulating
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Abstract
【解決手段】半導体装置は、半導体基板1と、半導体基板1の上に形成された層間絶縁膜2,3と、層間絶縁膜2,3の上に形成された電極パッド4と、層間絶縁膜2,3の上に電極パッド4の周縁部を覆うように形成され、電極パッド4の中央部を露出する第1の開口部5を有する保護膜6と、電極パッド4における第1の開口部5から露出する部分の上に形成され、第1の開口部5を複数の第2の開口部5dに分割する分割体7と、保護膜6の上に第2の開口部5d内を埋め込むように形成されたバリアメタル8と、バリアメタル8の上に形成されたバンプ電極とを有している。分割体は、電極パッドとバリアメタルとの間に介在している。
【選択図】図4
Description
以下に、本発明の第1の実施形態に係る半導体装置について、図1、図2、図3、図4、図5(a) 〜(b) 、及び図6を参照しながら説明する。
本実施形態に係る半導体装置は、図1に示すように、半導体基板1と、半導体基板1の上に形成された第1の層間絶縁膜2と、第1の層間絶縁膜2の上に形成された第2の層間絶縁膜3と、第2の層間絶縁膜3の上に形成された電極パッド4と、第2の層間絶縁膜3の上に電極パッド4の周縁部を覆うように形成され、電極パッド4の中央部を露出する第1の開口部5を有する保護膜6と、電極パッド4における第1の開口部5から露出する部分の上に、保護膜6と一体に形成され、第1の開口部5を、複数の第2の開口部(図4:5d参照)に分割する分割体7と、保護膜6の上に第2の開口部内を埋め込むように形成されたバリアメタル8と、バリアメタル8の上に形成されたバンプ電極9とを備えている。
以下に、本発明の第1の実施形態に係る半導体装置における分割体を含む部分の構成について、図5(a) 〜(b) を参照しながら説明する。図5(a) 〜(b) は、分割体を含む部分の構成を示す拡大図である。図5(a) は、図5(b) に示すVa-Va線における断面図であり、図5(b) は、平面図である。図5(b) に示す平面図は、図5(a) に示す断面図と対応する平面図である。なお、図5(a) に示す断面図は、図4に示す断面図と同様の断面図である。また、図5(b) において、簡略的に図示する為に、電極パッドの下に形成された第2の層間絶縁膜、第1の層間絶縁膜、及び半導体基板の図示を省略する。
以下に、本発明の第2の実施形態に係る半導体装置について、図9を参照しながら説明する。図9は、本発明の第2の実施形態に係る半導体装置における分割体を含む部分の構成を示す拡大平面図である。図9において、第1の実施形態における構成要素と同一の構成要素には、図5(b) に示す符号と同一の符号を付す。従って、本実施形態では、第1の実施形態と重複する説明を省略する。
以下に、本発明の第1の実施形態の変形例1に係る半導体装置について、図10(a) 〜(b) を参照しながら説明する。図10(a) 〜(b) は、本発明の第1の実施形態の変形例1に係る半導体装置における分割体を含む部分の構成を示す拡大図である。図10(a) は、図10(b) に示すXa-Xa線における断面図であり、図10(b) は、平面図である。図10(b) に示す平面図は、図10(a) に示す断面図と対応する平面図である。なお、図10(b) において、簡略的に図示する為に、電極パッド下の第2の層間絶縁膜、第1の層間絶縁膜、及び半導体基板の図示を省略する。また、図10(a) 〜(b) において、第1の実施形態における構成要素と同一の構成要素には、図4〜図5(b) に示す符号と同一の符号を付す。従って、本変形例では、第1の実施形態と重複する説明を省略する。
以下に、本発明の第1の実施形態の変形例2に係る半導体装置について、図12(a) 〜(b) を参照しながら説明する。図12(a) 〜(b) は、本発明の第1の実施形態の変形例2に係る半導体装置における分割体を含む部分の構成を示す拡大図である。図12(a) は、図12(b) に示すXIIa-XIIa線における断面図であり、図12(b) は、平面図である。図12(b) に示す平面図は、図12(a) に示す断面図と対応する平面図である。なお、図12(b) において、簡略的に図示する為に、電極パッド下の第2の層間絶縁膜、第1の層間絶縁膜、及び半導体基板の図示を省略する。また、図12(a) 〜(b) において、第1の実施形態における構成要素と同一の構成要素には、図4〜図5(b) に示す符号と同一の符号を付す。従って、本変形例では、第1の実施形態と重複する説明を省略する。
以下に、本発明の第3の実施形態に係る半導体装置について、図13(a) 〜(b) を参照しながら説明する。図13(a) 〜(b) は、本発明の第3の実施形態に係る半導体装置における分割体を含む部分の構成を示す拡大図である。図13(a) は、図13(b) に示すXIIIa-XIIIa線における断面図であり、図13(b) は、平面図である。図13(b) に示す平面図は、図13(a) に示す断面図と対応する平面図である。なお、図13(b) において、簡略的に図示する為に、電極パッド下の第2の層間絶縁膜、第1の層間絶縁膜、及び半導体基板の図示を省略する。また、図13(a) 〜(b) において、第1の実施形態における構成要素と同一の構成要素には、図4〜図5(b) に示す符号と同一の符号を付す。従って、本実施形態では、第1の実施形態と重複する説明を省略する。
2 第1の層間絶縁膜
3 第2の層間絶縁膜
4,54,64 電極パッド
54d,64d 電極パッド部
5 第1の開口部
5d,35d,65d 第2の開口部
6 保護膜
7,37,67 分割体
7a1〜7a2,67a1〜67a6 線状部
37b 環状部
8,28,28X,48,68 バリアメタル
48d,68d バリアメタル部
8x Ti膜
8y Cu膜
8z Ni膜
9 バンプ電極
10 拡散層
11 LOCOS層
12 貫通電極
13 配線
14 貫通電極
15,65 分割溝
15a1,15a2 線状溝部
16,66 分割溝
16a1,16a2 線状溝部
V1〜V8 第1〜第8の辺
P1〜P8 第1〜第8の部分
T 膜厚
D 距離
W 幅
Claims (18)
- 半導体基板と、
前記半導体基板の上に形成された層間絶縁膜と、
前記層間絶縁膜の上に形成された電極パッドと、
前記層間絶縁膜の上に前記電極パッドの周縁部を覆うように形成され、前記電極パッドの中央部を露出する第1の開口部を有する保護膜と、
前記電極パッドにおける前記第1の開口部から露出する部分の上に形成され、前記第1の開口部を複数の第2の開口部に分割する分割体と、
前記保護膜の上に前記第2の開口部内を埋め込むように形成されたバリアメタルと、
前記バリアメタルの上に形成されたバンプ電極とを備え、
前記分割体は、前記電極パッドと前記バリアメタルとの間に介在していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記層間絶縁膜には、複数の配線が形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記層間絶縁膜は、低誘電率絶縁膜であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記層間絶縁膜は、多孔質の低誘電率絶縁膜であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記分割体は、前記保護膜と一体に形成されていることを特徴とする半導体装置。 - 請求項5に記載の半導体装置において、
前記分割体は、直線状に延びる複数の線状部を有し、
前記線状部の一端及び他端の各々は、前記保護膜における前記第1の開口部から露出する内側面と接続されていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記第1の開口部の開口形状は、多角形状であり、
前記線状部は、前記多角形状を構成する辺に直交するように配置されていることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記複数の線状部の各々は、互いに交差するように配置され、
前記複数の線状部の各々が互いに交差する角度は、90°であることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記分割体は、環状部をさらに有し、
前記線状部は、前記環状部に囲まれた領域を分割するように配置されていることを特徴とする半導体装置。 - 請求項9に記載の半導体装置において、
前記環状部の平面形状は、多角形状であり、
前記線状部は、前記環状部に直交していることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記分割体の側面は、下面の面積が上面の面積よりも大きくなるように、下面から上面に向かって傾斜する傾斜面であることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記分割体の熱膨張係数は、前記バリアメタルの熱膨張係数よりも小さいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記分割体の熱膨張係数は、前記電極パッドの熱膨張係数よりも小さいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記バリアメタルは、電解めっきにより形成され、
前記バリアメタルは、第1の膜、第2の膜、及び第3の膜が順次積層されてなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記バリアメタルは、無電解めっきにより形成され、
前記バリアメタルは、第1の膜からなることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記バリアメタルには、前記分割体の上面を露出する分割溝が形成されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記電極パッドには、分割溝が形成され、
前記分割溝は、前記分割体の下に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置と、
前記半導体装置が実装される実装基板とを備え、
前記実装基板は、前記半導体装置の前記バンプ電極に接続される電極を有していることを特徴とする実装体。
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JP3981089B2 (ja) | 2004-02-18 | 2007-09-26 | 株式会社東芝 | 半導体装置とその製造方法 |
TWI295498B (en) * | 2005-09-30 | 2008-04-01 | Siliconware Precision Industries Co Ltd | Semiconductor element with conductive bumps and fabrication method thereof |
US7901956B2 (en) * | 2006-08-15 | 2011-03-08 | Stats Chippac, Ltd. | Structure for bumped wafer test |
JP5411434B2 (ja) * | 2008-02-22 | 2014-02-12 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置とその製造方法 |
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2009
- 2009-03-04 JP JP2009050573A patent/JP5350022B2/ja not_active Expired - Fee Related
- 2009-12-03 WO PCT/JP2009/006595 patent/WO2010100700A1/ja active Application Filing
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WO2009013826A1 (ja) * | 2007-07-25 | 2009-01-29 | Fujitsu Microelectronics Limited | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021034557A (ja) * | 2019-08-23 | 2021-03-01 | 三菱電機株式会社 | 半導体装置 |
JP7226186B2 (ja) | 2019-08-23 | 2023-02-21 | 三菱電機株式会社 | 半導体装置 |
Also Published As
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US8508051B2 (en) | 2013-08-13 |
JP5350022B2 (ja) | 2013-11-27 |
US20110316153A1 (en) | 2011-12-29 |
WO2010100700A1 (ja) | 2010-09-10 |
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