JP2010040772A5 - - Google Patents
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- Publication number
- JP2010040772A5 JP2010040772A5 JP2008202139A JP2008202139A JP2010040772A5 JP 2010040772 A5 JP2010040772 A5 JP 2010040772A5 JP 2008202139 A JP2008202139 A JP 2008202139A JP 2008202139 A JP2008202139 A JP 2008202139A JP 2010040772 A5 JP2010040772 A5 JP 2010040772A5
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- groove
- etching stopper
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims 7
- 238000005530 etching Methods 0.000 claims 6
- 239000000956 alloy Substances 0.000 claims 5
- 239000004065 semiconductor Substances 0.000 claims 5
- 229910045601 alloy Inorganic materials 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 4
- 239000007769 metal material Substances 0.000 claims 4
- 238000000034 method Methods 0.000 claims 3
- 238000004544 sputter deposition Methods 0.000 claims 3
- 238000000151 deposition Methods 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 2
- 239000011229 interlayer Substances 0.000 claims 2
- 238000007747 plating Methods 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- 239000000203 mixture Substances 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008202139A JP2010040772A (ja) | 2008-08-05 | 2008-08-05 | 半導体装置の製造方法 |
| US12/535,665 US8039390B2 (en) | 2008-08-05 | 2009-08-04 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008202139A JP2010040772A (ja) | 2008-08-05 | 2008-08-05 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010040772A JP2010040772A (ja) | 2010-02-18 |
| JP2010040772A5 true JP2010040772A5 (enExample) | 2011-09-22 |
Family
ID=42013007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008202139A Pending JP2010040772A (ja) | 2008-08-05 | 2008-08-05 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2010040772A (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8531033B2 (en) | 2009-09-07 | 2013-09-10 | Advanced Interconnect Materials, Llc | Contact plug structure, semiconductor device, and method for forming contact plug |
| JP2021136271A (ja) * | 2020-02-25 | 2021-09-13 | キオクシア株式会社 | 半導体装置およびその製造方法 |
| CN117960529B (zh) * | 2023-10-09 | 2025-10-03 | 江西蓝微电子科技有限公司 | 一种绝缘覆膜抗腐蚀合金键合丝的制备方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6949461B2 (en) * | 2002-12-11 | 2005-09-27 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure |
| JP2006216787A (ja) * | 2005-02-03 | 2006-08-17 | Renesas Technology Corp | 半導体装置およびその製造方法 |
| JP2007027347A (ja) * | 2005-07-15 | 2007-02-01 | Sony Corp | 半導体装置およびその製造方法 |
| JP2007059660A (ja) * | 2005-08-25 | 2007-03-08 | Sony Corp | 半導体装置の製造方法および半導体装置 |
| JP2007081113A (ja) * | 2005-09-14 | 2007-03-29 | Sony Corp | 半導体装置の製造方法 |
| JP2007173511A (ja) * | 2005-12-22 | 2007-07-05 | Sony Corp | 半導体装置の製造方法 |
| JP5076482B2 (ja) * | 2006-01-20 | 2012-11-21 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP5076452B2 (ja) * | 2006-11-13 | 2012-11-21 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP5010265B2 (ja) * | 2006-12-18 | 2012-08-29 | 株式会社東芝 | 半導体装置の製造方法 |
| JP5103914B2 (ja) * | 2007-01-31 | 2012-12-19 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法及び半導体装置 |
| JP5141761B2 (ja) * | 2008-02-27 | 2013-02-13 | 富士通セミコンダクター株式会社 | 半導体装置及びその製造方法 |
-
2008
- 2008-08-05 JP JP2008202139A patent/JP2010040772A/ja active Pending
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