JP2009509319A5 - - Google Patents

Download PDF

Info

Publication number
JP2009509319A5
JP2009509319A5 JP2008530486A JP2008530486A JP2009509319A5 JP 2009509319 A5 JP2009509319 A5 JP 2009509319A5 JP 2008530486 A JP2008530486 A JP 2008530486A JP 2008530486 A JP2008530486 A JP 2008530486A JP 2009509319 A5 JP2009509319 A5 JP 2009509319A5
Authority
JP
Japan
Prior art keywords
opening
metal structure
dielectric cap
dielectric
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008530486A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009509319A (ja
JP5261647B2 (ja
Filing date
Publication date
Priority claimed from US11/162,666 external-priority patent/US7563704B2/en
Application filed filed Critical
Publication of JP2009509319A publication Critical patent/JP2009509319A/ja
Publication of JP2009509319A5 publication Critical patent/JP2009509319A5/ja
Application granted granted Critical
Publication of JP5261647B2 publication Critical patent/JP5261647B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008530486A 2005-09-19 2006-09-06 金属相互接続構造体 Expired - Fee Related JP5261647B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/162,666 2005-09-19
US11/162,666 US7563704B2 (en) 2005-09-19 2005-09-19 Method of forming an interconnect including a dielectric cap having a tensile stress
PCT/EP2006/066077 WO2007039385A1 (en) 2005-09-19 2006-09-06 Metal interconnect structure for a microelectronic element

Publications (3)

Publication Number Publication Date
JP2009509319A JP2009509319A (ja) 2009-03-05
JP2009509319A5 true JP2009509319A5 (enExample) 2009-04-16
JP5261647B2 JP5261647B2 (ja) 2013-08-14

Family

ID=37400882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008530486A Expired - Fee Related JP5261647B2 (ja) 2005-09-19 2006-09-06 金属相互接続構造体

Country Status (7)

Country Link
US (1) US7563704B2 (enExample)
EP (1) EP1943675B1 (enExample)
JP (1) JP5261647B2 (enExample)
KR (1) KR20080047383A (enExample)
CN (1) CN100583427C (enExample)
TW (1) TWI397149B (enExample)
WO (1) WO2007039385A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7262133B2 (en) * 2003-01-07 2007-08-28 Applied Materials, Inc. Enhancement of copper line reliability using thin ALD tan film to cap the copper line
US8178436B2 (en) * 2006-12-21 2012-05-15 Intel Corporation Adhesion and electromigration performance at an interface between a dielectric and metal
US7666753B2 (en) * 2007-01-11 2010-02-23 International Business Machines Corporation Metal capping process for BEOL interconnect with air gaps
US8592312B2 (en) * 2007-06-07 2013-11-26 Globalfoundries Inc. Method for depositing a conductive capping layer on metal lines
US7858532B2 (en) * 2007-08-06 2010-12-28 United Microelectronics Corp. Dielectric layer structure and manufacturing method thereof
US7732324B2 (en) * 2007-12-20 2010-06-08 Texas Instruments Incorporated Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer
US20090218644A1 (en) * 2008-02-29 2009-09-03 Gill Yong Lee Integrated Circuit, Memory Device, and Method of Manufacturing an Integrated Circuit
US8039966B2 (en) * 2009-09-03 2011-10-18 International Business Machines Corporation Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects
DE102009055439A1 (de) * 2009-12-31 2011-07-07 GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG, 01109 Halbleiterbauelement mit halbleiterbasierten e-Sicherungen mit besserer Programmiereffizienz durch erhöhte Metallagglomeration und/oder Hohlraumbildung
US8461683B2 (en) * 2011-04-01 2013-06-11 Intel Corporation Self-forming, self-aligned barriers for back-end interconnects and methods of making same
US9224643B2 (en) * 2011-09-19 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for tunable interconnect scheme
US8981466B2 (en) * 2013-03-11 2015-03-17 International Business Machines Corporation Multilayer dielectric structures for semiconductor nano-devices
KR102122593B1 (ko) * 2013-10-22 2020-06-15 삼성전자주식회사 반도체 소자
US9299605B2 (en) * 2014-03-07 2016-03-29 Applied Materials, Inc. Methods for forming passivation protection for an interconnection structure
US11756828B2 (en) 2018-11-20 2023-09-12 Applied Materials, Inc. Cluster processing system for forming a transition metal material
US20230335498A1 (en) * 2022-04-18 2023-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection structure and methods of forming the same

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5695810A (en) * 1996-11-20 1997-12-09 Cornell Research Foundation, Inc. Use of cobalt tungsten phosphide as a barrier material for copper metallization
JP3226816B2 (ja) * 1996-12-25 2001-11-05 キヤノン販売株式会社 層間絶縁膜の形成方法、半導体装置及びその製造方法
US6369423B2 (en) * 1998-03-03 2002-04-09 Kabushiki Kaisha Toshiba Semiconductor device with a thin gate stack having a plurality of insulating layers
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6342733B1 (en) 1999-07-27 2002-01-29 International Business Machines Corporation Reduced electromigration and stressed induced migration of Cu wires by surface coating
US6319819B1 (en) * 2000-01-18 2001-11-20 Advanced Micro Devices, Inc. Process for passivating top interface of damascene-type Cu interconnect lines
US6383925B1 (en) * 2000-02-04 2002-05-07 Advanced Micro Devices, Inc. Method of improving adhesion of capping layers to cooper interconnects
JP4350337B2 (ja) * 2001-04-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US6506677B1 (en) * 2001-05-02 2003-01-14 Advanced Micro Devices, Inc. Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance
US6429128B1 (en) * 2001-07-12 2002-08-06 Advanced Micro Devices, Inc. Method of forming nitride capped Cu lines with reduced electromigration along the Cu/nitride interface
CN1329972C (zh) * 2001-08-13 2007-08-01 株式会社荏原制作所 半导体器件及其制造方法
US6890850B2 (en) * 2001-12-14 2005-05-10 Applied Materials, Inc. Method of depositing dielectric materials in damascene applications
US7091137B2 (en) * 2001-12-14 2006-08-15 Applied Materials Bi-layer approach for a hermetic low dielectric constant layer for barrier applications
US20030134499A1 (en) * 2002-01-15 2003-07-17 International Business Machines Corporation Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
US6764951B1 (en) * 2002-02-28 2004-07-20 Advanced Micro Devices, Inc. Method for forming nitride capped Cu lines with reduced hillock formation
US6797652B1 (en) * 2002-03-15 2004-09-28 Advanced Micro Devices, Inc. Copper damascene with low-k capping layer and improved electromigration reliability
US6617690B1 (en) * 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
JP2004095865A (ja) * 2002-08-30 2004-03-25 Nec Electronics Corp 半導体装置およびその製造方法
JP4606713B2 (ja) * 2002-10-17 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7241696B2 (en) * 2002-12-11 2007-07-10 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer
US6818557B1 (en) * 2002-12-12 2004-11-16 Advanced Micro Devices, Inc. Method of forming SiC capped copper interconnects with reduced hillock formation and improved electromigration resistance
US7102232B2 (en) * 2004-04-19 2006-09-05 International Business Machines Corporation Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer

Similar Documents

Publication Publication Date Title
JP2009509319A5 (enExample)
JP3954974B2 (ja) 半導体デバイス
CN2741192Y (zh) 具有高品质因子的电感
TWI473233B (zh) 具有銅插塞的半導體元件
TW200811995A (en) Dielectric spacers for metal interconnects and method to form the same
JP2008537337A5 (enExample)
JP2006344703A5 (enExample)
JP2001267323A (ja) 半導体装置及びその製造方法
JP2020505770A5 (enExample)
TWI232523B (en) Damascene process and structure thereof
US20020047218A1 (en) Bond pad of semiconductor device and method of fabricating the same
TWI397149B (zh) 形成包括有具伸張應力之介電質蓋罩之介連接線的方法與結構
JP2001217242A (ja) 半導体装置およびその製造方法
JP2004140093A (ja) ボンディングパッド及びその形成方法
US20070114668A1 (en) Semiconductor device
TWI322471B (en) A semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method
KR101486143B1 (ko) 화학적 직접 패턴 도금 상호연결 금속화 및 이에 의해 생산된 금속 구조물
JP2011134885A (ja) 半導体装置およびその製造方法
CN102446811A (zh) 金属互连结构及金属层间通孔和互连金属线的形成方法
KR100772254B1 (ko) 병렬 구조를 이용한 다층 메탈 배선의 구조 및 형성 방법
US12159837B2 (en) Chemical direct pattern plating method
KR100808794B1 (ko) 반도체 소자의 제조 방법
KR100661220B1 (ko) 듀얼 절연막을 이용한 금속 배선 형성 방법
JP2008016464A (ja) 半導体装置及び半導体装置の製造方法
KR20240132776A (ko) 반도체 디바이스 및 그 제조 방법