JP2008537337A5 - - Google Patents
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- Publication number
- JP2008537337A5 JP2008537337A5 JP2008506549A JP2008506549A JP2008537337A5 JP 2008537337 A5 JP2008537337 A5 JP 2008537337A5 JP 2008506549 A JP2008506549 A JP 2008506549A JP 2008506549 A JP2008506549 A JP 2008506549A JP 2008537337 A5 JP2008537337 A5 JP 2008537337A5
- Authority
- JP
- Japan
- Prior art keywords
- core conductor
- conductive
- liner
- conductive liner
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims 41
- 238000000034 method Methods 0.000 claims 22
- 239000000463 material Substances 0.000 claims 19
- 229910052721 tungsten Inorganic materials 0.000 claims 9
- 239000002184 metal Substances 0.000 claims 7
- 229910052751 metal Inorganic materials 0.000 claims 7
- 238000000151 deposition Methods 0.000 claims 6
- 229910008482 TiSiN Inorganic materials 0.000 claims 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 5
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims 5
- 229910052707 ruthenium Inorganic materials 0.000 claims 5
- 238000000992 sputter etching Methods 0.000 claims 5
- 229910052715 tantalum Inorganic materials 0.000 claims 5
- 229910052718 tin Inorganic materials 0.000 claims 5
- 229910016570 AlCu Inorganic materials 0.000 claims 4
- 229910052782 aluminium Inorganic materials 0.000 claims 4
- 230000004888 barrier function Effects 0.000 claims 4
- 229910052802 copper Inorganic materials 0.000 claims 4
- 238000009792 diffusion process Methods 0.000 claims 4
- 229910052737 gold Inorganic materials 0.000 claims 4
- 229910052709 silver Inorganic materials 0.000 claims 4
- -1 Si 3 N 4 Inorganic materials 0.000 claims 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims 3
- 230000008021 deposition Effects 0.000 claims 2
- 238000007772 electroless plating Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- 229910052739 hydrogen Inorganic materials 0.000 claims 2
- 238000005498 polishing Methods 0.000 claims 2
- 229920000642 polymer Polymers 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 239000000126 substance Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- 229920000265 Polyparaphenylene Polymers 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims 1
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/107,074 US7335588B2 (en) | 2005-04-15 | 2005-04-15 | Interconnect structure and method of fabrication of same |
| US11/107,074 | 2005-04-15 | ||
| PCT/US2006/013179 WO2006113186A2 (en) | 2005-04-15 | 2006-04-07 | Interconnect structure and method of fabrication of same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008537337A JP2008537337A (ja) | 2008-09-11 |
| JP2008537337A5 true JP2008537337A5 (enExample) | 2009-02-19 |
| JP5089575B2 JP5089575B2 (ja) | 2012-12-05 |
Family
ID=37109075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008506549A Active JP5089575B2 (ja) | 2005-04-15 | 2006-04-07 | 相互接続構造体及びその製造方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (4) | US7335588B2 (enExample) |
| EP (1) | EP1869700B1 (enExample) |
| JP (1) | JP5089575B2 (enExample) |
| CN (1) | CN101390203B (enExample) |
| AT (1) | ATE535013T1 (enExample) |
| TW (1) | TWI389252B (enExample) |
| WO (1) | WO2006113186A2 (enExample) |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744424B1 (ko) * | 2006-08-29 | 2007-07-30 | 동부일렉트로닉스 주식회사 | 반도체소자의 제조방법 |
| JP4740080B2 (ja) * | 2006-09-26 | 2011-08-03 | 三洋電機株式会社 | 空気除菌装置 |
| US20080157268A1 (en) * | 2006-12-30 | 2008-07-03 | Kim Deok-Kee | Fuse Element Using Low-K Dielectric |
| JP2009111251A (ja) * | 2007-10-31 | 2009-05-21 | Tohoku Univ | 半導体装置およびその製造方法 |
| JP2009146958A (ja) * | 2007-12-12 | 2009-07-02 | Panasonic Corp | 半導体装置及びその製造方法 |
| US20090166867A1 (en) * | 2007-12-31 | 2009-07-02 | Harsono Simka | Metal interconnect structures for semiconductor devices |
| JP2009182181A (ja) * | 2008-01-31 | 2009-08-13 | Toshiba Corp | 半導体装置 |
| US8354751B2 (en) * | 2008-06-16 | 2013-01-15 | International Business Machines Corporation | Interconnect structure for electromigration enhancement |
| US7955971B2 (en) * | 2009-06-11 | 2011-06-07 | International Business Machines Corporation | Hybrid metallic wire and methods of fabricating same |
| US8786062B2 (en) * | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
| US20110084372A1 (en) | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
| KR101315173B1 (ko) | 2009-12-28 | 2013-10-08 | 후지쯔 가부시끼가이샤 | 배선 구조 및 그 형성 방법 |
| US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
| KR20110089731A (ko) * | 2010-02-01 | 2011-08-09 | 삼성전자주식회사 | 배선 랜더를 포함하는 반도체 소자 및 그 제조 방법 |
| US20110207323A1 (en) * | 2010-02-25 | 2011-08-25 | Robert Ditizio | Method of forming and patterning conformal insulation layer in vias and etched structures |
| TWI411075B (zh) | 2010-03-22 | 2013-10-01 | 日月光半導體製造股份有限公司 | 半導體封裝件及其製造方法 |
| FR2963160A1 (fr) * | 2010-07-22 | 2012-01-27 | St Microelectronics Crolles 2 | Procede de realisation d'un niveau de metallisation et d'un niveau de via et circuit integre correspondant |
| US8610285B2 (en) * | 2011-05-30 | 2013-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D IC packaging structures and methods with a metal pillar |
| US8916405B2 (en) * | 2011-10-11 | 2014-12-23 | International Business Machines Corporation | Light emitting diode (LED) using carbon materials |
| US9190316B2 (en) * | 2011-10-26 | 2015-11-17 | Globalfoundries U.S. 2 Llc | Low energy etch process for nitrogen-containing dielectric layer |
| US9349689B2 (en) | 2012-04-20 | 2016-05-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices including conductive features with capping layers and methods of forming the same |
| US10217644B2 (en) * | 2012-07-24 | 2019-02-26 | Infineon Technologies Ag | Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures |
| US8835305B2 (en) * | 2012-07-31 | 2014-09-16 | International Business Machines Corporation | Method of fabricating a profile control in interconnect structures |
| US9837701B2 (en) | 2013-03-04 | 2017-12-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package including antenna substrate and manufacturing method thereof |
| US9142456B2 (en) * | 2013-07-30 | 2015-09-22 | Lam Research Corporation | Method for capping copper interconnect lines |
| US9349636B2 (en) * | 2013-09-26 | 2016-05-24 | Intel Corporation | Interconnect wires including relatively low resistivity cores |
| US9135719B1 (en) * | 2014-06-26 | 2015-09-15 | Amazon Technologies, Inc. | Color name generation from images and color palettes |
| US9553044B2 (en) * | 2014-11-05 | 2017-01-24 | International Business Machines Corporation | Electrically conductive interconnect including via having increased contact surface area |
| US10727122B2 (en) * | 2014-12-08 | 2020-07-28 | International Business Machines Corporation | Self-aligned via interconnect structures |
| KR20160122364A (ko) * | 2015-04-14 | 2016-10-24 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
| WO2017111803A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Techniques for forming electrically conductive features with improved alignment and capacitance reduction |
| WO2017111847A1 (en) * | 2015-12-24 | 2017-06-29 | Intel Corporation | Techniques for forming electrically conductive features with improved alignment and capacitance reduction |
| KR102582671B1 (ko) | 2016-12-22 | 2023-09-25 | 삼성전자주식회사 | 반도체 소자 |
| US10096550B2 (en) | 2017-02-21 | 2018-10-09 | Raytheon Company | Nitride structure having gold-free contact and methods for forming such structures |
| US10224285B2 (en) | 2017-02-21 | 2019-03-05 | Raytheon Company | Nitride structure having gold-free contact and methods for forming such structures |
| US10510657B2 (en) | 2017-09-26 | 2019-12-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with interconnecting structure and method for manufacturing the same |
| US11004735B2 (en) * | 2018-09-14 | 2021-05-11 | International Business Machines Corporation | Conductive interconnect having a semi-liner and no top surface recess |
| TWI801631B (zh) * | 2018-11-09 | 2023-05-11 | 台灣積體電路製造股份有限公司 | 半導體裝置的製造方法和半導體裝置 |
| US11094580B2 (en) * | 2019-10-01 | 2021-08-17 | International Business Machines Corporation | Structure and method to fabricate fully aligned via with reduced contact resistance |
| WO2021174415A1 (en) * | 2020-03-03 | 2021-09-10 | Yangtze Memory Technologies Co., Ltd. | Protection structures in semiconductor chips and methods for forming the same |
| US12057395B2 (en) * | 2021-09-14 | 2024-08-06 | International Business Machines Corporation | Top via interconnects without barrier metal between via and above line |
| TWI825516B (zh) * | 2021-11-30 | 2023-12-11 | 南亞科技股份有限公司 | 製造半導體裝置的方法 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5300813A (en) * | 1992-02-26 | 1994-04-05 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| JP2663902B2 (ja) * | 1995-03-17 | 1997-10-15 | 日本電気株式会社 | 微細トレンチの埋め込み方法、微細電極の製造方法、微細ホールの埋め込み方法、及び微細金属配線の製造方法 |
| KR100189967B1 (ko) * | 1995-07-20 | 1999-06-01 | 윤종용 | 반도체장치의 다층배선 형성방법 |
| US5976970A (en) * | 1996-03-29 | 1999-11-02 | International Business Machines Corporation | Method of making and laterally filling key hole structure for ultra fine pitch conductor lines |
| JP3399786B2 (ja) * | 1996-06-04 | 2003-04-21 | シーメンス アクチエンゲゼルシヤフト | 原動機付き車両内の回路装置 |
| US5695810A (en) * | 1996-11-20 | 1997-12-09 | Cornell Research Foundation, Inc. | Use of cobalt tungsten phosphide as a barrier material for copper metallization |
| US5930669A (en) * | 1997-04-03 | 1999-07-27 | International Business Machines Corporation | Continuous highly conductive metal wiring structures and method for fabricating the same |
| US6140226A (en) * | 1998-01-16 | 2000-10-31 | International Business Machines Corporation | Dual damascene processing for semiconductor chip interconnects |
| US6211084B1 (en) * | 1998-07-09 | 2001-04-03 | Advanced Micro Devices, Inc. | Method of forming reliable copper interconnects |
| JP2000049116A (ja) * | 1998-07-30 | 2000-02-18 | Toshiba Corp | 半導体装置及びその製造方法 |
| US6333560B1 (en) | 1999-01-14 | 2001-12-25 | International Business Machines Corporation | Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies |
| US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
| US6197681B1 (en) * | 1999-12-31 | 2001-03-06 | United Microelectronics Corp. | Forming copper interconnects in dielectric materials with low constant dielectrics |
| US6482733B2 (en) * | 2000-05-15 | 2002-11-19 | Asm Microchemistry Oy | Protective layers prior to alternating layer deposition |
| US7115531B2 (en) * | 2000-08-21 | 2006-10-03 | Dow Global Technologies Inc. | Organosilicate resins as hardmasks for organic polymer dielectrics in fabrication of microelectronic devices |
| US6461963B1 (en) * | 2000-08-30 | 2002-10-08 | Micron Technology, Inc. | Utilization of disappearing silicon hard mask for fabrication of semiconductor structures |
| TW471107B (en) * | 2000-11-27 | 2002-01-01 | Nanya Technology Corp | Dual damascene manufacturing method of porous low-k dielectric material |
| US6674170B1 (en) * | 2000-12-18 | 2004-01-06 | Advanced Micro Devices, Inc. | Barrier metal oxide interconnect cap in integrated circuits |
| US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
| US6486059B2 (en) * | 2001-04-19 | 2002-11-26 | Silicon Intergrated Systems Corp. | Dual damascene process using an oxide liner for a dielectric barrier layer |
| US6696222B2 (en) * | 2001-07-24 | 2004-02-24 | Silicon Integrated Systems Corp. | Dual damascene process using metal hard mask |
| JP3648480B2 (ja) * | 2001-12-26 | 2005-05-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
| JP3812891B2 (ja) * | 2002-01-30 | 2006-08-23 | 株式会社荏原製作所 | 配線形成方法 |
| JP2004128239A (ja) * | 2002-10-03 | 2004-04-22 | Renesas Technology Corp | スタティック型半導体記憶装置 |
| US7023093B2 (en) * | 2002-10-24 | 2006-04-04 | International Business Machines Corporation | Very low effective dielectric constant interconnect Structures and methods for fabricating the same |
| US6706625B1 (en) * | 2002-12-06 | 2004-03-16 | Chartered Semiconductor Manufacturing Ltd. | Copper recess formation using chemical process for fabricating barrier cap for lines and vias |
| US6975032B2 (en) | 2002-12-16 | 2005-12-13 | International Business Machines Corporation | Copper recess process with application to selective capping and electroless plating |
| US6784105B1 (en) * | 2003-04-09 | 2004-08-31 | Infineon Technologies North America Corp. | Simultaneous native oxide removal and metal neutral deposition method |
| JP4057972B2 (ja) * | 2003-07-25 | 2008-03-05 | 富士通株式会社 | 半導体装置の製造方法 |
| US7094669B2 (en) * | 2004-08-03 | 2006-08-22 | Chartered Semiconductor Manufacturing Ltd | Structure and method of liner air gap formation |
| US7332428B2 (en) * | 2005-02-28 | 2008-02-19 | Infineon Technologies Ag | Metal interconnect structure and method |
| US20060205204A1 (en) * | 2005-03-14 | 2006-09-14 | Michael Beck | Method of making a semiconductor interconnect with a metal cap |
-
2005
- 2005-04-15 US US11/107,074 patent/US7335588B2/en not_active Expired - Fee Related
-
2006
- 2006-04-04 TW TW095112007A patent/TWI389252B/zh not_active IP Right Cessation
- 2006-04-07 WO PCT/US2006/013179 patent/WO2006113186A2/en not_active Ceased
- 2006-04-07 CN CN2006800120492A patent/CN101390203B/zh active Active
- 2006-04-07 JP JP2008506549A patent/JP5089575B2/ja active Active
- 2006-04-07 AT AT06740771T patent/ATE535013T1/de active
- 2006-04-07 EP EP06740771A patent/EP1869700B1/en active Active
-
2007
- 2007-09-25 US US11/860,602 patent/US7563710B2/en not_active Expired - Fee Related
- 2007-09-25 US US11/860,590 patent/US7528493B2/en not_active Expired - Lifetime
-
2008
- 2008-06-17 US US12/140,352 patent/US7598616B2/en not_active Expired - Fee Related
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