TWI473233B - 具有銅插塞的半導體元件 - Google Patents

具有銅插塞的半導體元件 Download PDF

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Publication number
TWI473233B
TWI473233B TW99133361A TW99133361A TWI473233B TW I473233 B TWI473233 B TW I473233B TW 99133361 A TW99133361 A TW 99133361A TW 99133361 A TW99133361 A TW 99133361A TW I473233 B TWI473233 B TW I473233B
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Taiwan
Prior art keywords
layer
copper plug
copper
opening
semiconductor device
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TW99133361A
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English (en)
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TW201130100A (en
Inventor
Mukta G Farooq
Emily R Kinser
Ian D Melville
Krystyna W Semkow
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Ibm
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Publication of TW201130100A publication Critical patent/TW201130100A/zh
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Publication of TWI473233B publication Critical patent/TWI473233B/zh

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    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Description

具有銅插塞的半導體元件
本發明係有關於一半導體元件，並尤其有關於一適用於覆晶結合至一封裝且具有一銅插塞之一半導體元件。
所稱的覆晶封裝通常用於將半導體元件結合至一封裝，使其與傳統導線封裝相較之下具有多個優點。這些優點包括高集積度、耐用度(ruggedness)、以及成本。在一用於覆晶結合的半導體元件中，此半導體元件包括一絕緣層以及一最終鈍化層(passivation)，其中有一介層窗開口以接收球限金屬(ball limiting metallurgy)(有時亦稱為凸塊下金屬(underbump metallurgy)以及一定量之銲錫。絕緣層材料可為，舉例而言，一氮化矽或氧化矽，而最終鈍化層材料可為，舉例而言，一聚亞醯胺(polyimide)或一光敏聚亞醯胺。
所完成的半導體晶片包括此球限金屬以及銲錫，而可被置於與一封裝(例如一印刷電路板或陶瓷基板)接觸，接著加熱以使得銲錫再次流動並將半導體晶片結合至此封裝。
本發明係利用結構中的絕緣層中的銅插塞而取代目前用於半導體元件中的最終鋁層。本發明的實施例係解決了目前使用最終鋁層的半導體設計中，電子漂移與結構的問題。
如上所述的本發明各目的與優點，根據本發明之第一面向，可藉由提供如下之半導體元件而達成，此半導體元件包括：一半導體基板，該半導體基板具有複數個導線層，其中最終導線層包括一導電材料；一絕緣層，形成於此最終導線層之上，此絕緣層中形成一介層窗(via)開口，以將此最終導線層之此導電材料外露；一障礙層，形成於此介層窗開口中；以及一銅插塞，形成於此障礙層之上且填滿此介層窗開口。
根據本發明之第二面向，係提供一半導體元件，該半導體元件包括：一半導體基板，該半導體基板具有一最終導線層，且該最終導線層包括一導電材料；一絕緣層，形成於此最終導線層之上，此絕緣層中形成一介層窗開口，以外露出此最終導線層中之此導電材料；以及一銅插塞，形成於此介層窗開口中並填滿此介層窗開口。
根據本發明之第三面向，係提供一種形成一半導體元件之方法，包括：獲得一半導體基板，該半導體基板具有複數個導線層，其中最終導線層包括一導電材料；於該最終導電層之上形成一絕緣層；於該絕緣層中形成一介層窗開口，以外露該最終導電層中之該導電材料；於該介層窗開口中形成一障礙層；以及於該障礙層之上形成一銅插塞且填滿該介層窗開口。
根據本發明之第四面向，係提供一種形成一半導體元件之方法，包括：在一半導體元件之一最終導線層之上形成一絕緣層；在絕緣層中形成一介層窗開口以外露最終導線層中之一導電材料；以及在介層窗開口中形成一銅插塞並將介層窗開口填滿。
更詳細地參照至圖示，且特別參照至圖1，其係顯示本發明第一實施例之剖面。半導體元件10包括一半導體基板12，其包括半導體材料、前段製程特徵如電晶體、以及後段製程導線層。為了清楚起見，在圖1中僅顯示最終導線層14。最終導線層14包括一介電材料16以及金屬導線18。金屬導線18的成份不限於任何特定冶金(metallurgy)；舉例而言，鋁、鋁銅合金、銅、銅合金、或其他熟悉該項技藝者所知的導電材料等，均可用作為金屬導線18。半導體材料可為任何半導體材料，包括但不限於第IV族半導體如矽、矽鍺、或鍺、一III-V族化合物半導體、或一II-VI族化合物半導體。
金屬導線18的金屬較佳係為銅，因為其電氣性質較為理想。使用銅亦有先天的問題，包括電子漂移問題，而可能影響可靠度。同時，銅必須與大氣隔絕，以避免氧化以及形成電阻介金屬副產物其對電子漂移速率有負面影響。
因此，本發明之發明人提出了使用銅插塞於絕緣層的構想，而銅插塞則作為提供晶圓完成之一導電材料、以及後續球限金屬沈積製程的一平坦表面。此銅插塞也避免了對於其下銅導線層的破壞。
繼續參照至圖1，半導體元件10包括一絕緣層20其可更包括一個或多個個別子層。在一較佳實施例中，絕緣層20包括一NBLoK(NBLoK係為應用材料公司之商標)子層22(NBLoK係為一經氮摻雜之碳化矽)、一二氧化矽子層24、以及一氮化矽子層26。氮化矽可用以取代NBLoK子層22作為一替代方案。其他材料亦可用於絕緣層20之中。在另一實施例中，可在子層22與子層24之間包括另一氮化物子層(未示)。此絕緣層20可包括任何一種或多種介電材料其作用為一電氣絕緣層。作為說明且非限制性地，此一介電材料可為一低介電材料例如一SiCOH成份。包括於絕緣層20之中的是一銅插塞28，且較佳地係有一由如鉭與氮化鉭所構成之一障礙層30。其他材料也可用於障礙層30之中，例如鈦、鈦鎢、氮化鈦或氮化鉭。最佳地，半導體元件10也包括一覆蓋層32以保護銅插塞28不受氧化。覆蓋層32可為一如NBLoK之氮化物，但其他如氮化矽、氮化鉭、或氮化鈦等材料亦可用於覆蓋層32中。
參照至圖2，係揭露本發明一第二實施例。半導體元件110係實質上相似於半導體元件10(圖1)，除了半導體元件110現在包括了一鈍化層34(passivation)，其中則形成有一介層窗36(via)。在使用時，球限金屬(ball limiting metallurgy)(未示於圖2中)會被沈積，以準備接受一定量的銲錫以接合至一封裝。鈍化層34可由聚亞醯胺、光敏聚亞醯胺、氟化聚亞醯胺、苯並環丁烯(BCB,benzocyclobutene)、聚四氟乙烯(polytetrafluoroethylene)、氧化矽、氮氧化矽、或其他介電材料。
參照至圖9，其係揭露本發明第三實施例。半導體元件120包括一半導體基板12其包括半導體材料、前段製程特徵如電晶體等、以及導線層的後段製程。為了清楚起見，在圖9中僅顯示最終導線層14。最終導線層14包括一介電材料16以及金屬導線18。半導體基板以及最終導線層14的材料係與圖1所示之第一實施例10中所討論者相同。第三實施例半導體元件120亦可包括絕緣層20其包括子層22,24,26，如上所述。半導體元件120可更包括一鋁層50其接觸至絕緣層20。鋁層50的一部份也可延伸至絕緣層20的上表面40，如圖9所示。之後，半導體元件120更包括一較佳障礙層30以及銅插塞28。銅插塞28的厚度可基於性能與製成需求而調整。接著，由鈷、鈷/鎢/磷或其他鈷合金所構成之一選擇性覆蓋層52可利用如電鍍等方式沈積於銅插塞之上。在後續製程中，可清潔銅插塞28的表面，使得選擇性覆蓋層52非必要，且不須被沈積。如前所述，最終鋁層有電子漂移的問題，但本發明之銅插塞28則改善了半導體元件120的電子漂移問題。
參照至圖10，其係揭露本發明第四實施例。半導體元件130係實質上類似於圖9中所示之半導體元件120，但半導體元件130則包括了一鈍化層34，其中形成有一介層窗36。在使用中，一球限金屬(未示)會被沈積以準備接受一定量的銲錫，以接合至封裝。鈍化層的材料可以與圖2中的半導體元件110的鈍化層34的材料相同。
請參照至圖3-8，其係討論用以形成圖1與圖2中的半導體元件10與110的製程步驟。參照至圖3，其係顯示半導體基板12其包括半導體材料、前段製程特徵如電晶體等、以及後段製程導線層。為了清楚起見，圖3中僅繪出最終導線層14。最終導線層14包括一介電材料16以及金屬導線18。在金屬導線18中的金屬較佳係為銅，因為其電氣性質較理想，但也可以是上述任何導電材料之一。在半導體基板12之上，係形成一絕緣層20。絕緣層20可由一個或多個子層所構成。在一較佳實施例中，絕緣層20包括一NBLoK(NBLoK係為應用材料公司之商標)子層22(NBLoK係為一經氮摻雜之碳化矽)、一二氧化矽子層24、以及一氮化矽子層26。若有需要，氮化矽可用以取代NBLoK子層22。其他材料亦可用於絕緣層20之中，如前所述。在另一較佳實施例中，在子層22與24之間可有另一氮化物層(未示)。每一子層22,24,26可由習知的方式進行沈積，例如電漿增強化學氣相沈積(plasma enhanced chemical vapor deposition)。作為說明而非限制，NBLoK子層22的厚度可為1000埃(angstrom)，而二氧化矽子層24與氮化矽子層26的加總厚度則為8500埃。同時，作為說明而非限制，二氧化矽子層24的厚度可為4500埃，而氮化矽子層26的厚度可為4000埃。
請參照圖4，一開口38係形成於絕緣層20之中。開口38可以由習知方法形成，例如反應性離子蝕刻。如圖所示，開口38的側壁最佳並非垂直，而是向外傾斜。開口38的側壁應以相對於水平之一角度α傾斜，以求銅插塞28有最佳的電流分散應用，角度α係介於45至75度之間，最佳係為60度。開口38的側壁的傾斜角度α也可見於圖9中，其中介層窗開口的側壁對於水平而言是傾斜的。若子層22為NBLoK層，則蝕刻穿過子層22的步驟可能需要與蝕刻穿過子層24與26的步驟不同。此一不同的蝕刻步驟可為反應性離子蝕刻，其使用了如CHF3、CH2F2、或CH3F等氟化碳氫化合物。理想情況下可包括一反應性離子蝕刻後的清理步驟，例如灰化(ashing)或濕式清潔。在形成開口38之後，銅導線18即被外露。由於銅導線18易於氧化的特性，必須在上述製程中採取必要步驟以將銅導線18維持於非氧化環境中。任何殘餘的氧化銅會在進行後續製程之前先移除。
請參照圖5，在一較佳實施例中，係以一習知方法，例如化學氣相沈積、物理氣相沈積、濺鍍或電鍍，而沈積障礙層30，以至少在絕緣層20中所形成的開口38的側壁與底部形成襯底。障礙層30可為前述任一障礙層材料。僅作為舉例而非限制，障礙層30的厚度可為1000埃。接著在障礙層30的側壁與底部沈積銅而形成銅插塞28。應沈積足夠量的銅，以至少填滿開口38，而較佳係過度填充。較佳係形成過度覆蓋(overburden)的銅，舉例而言，過度填充5000至10000埃。僅作為說明而非限制，在一較佳實施例中，銅插塞28的厚度為8500埃。應注意的是，銅插塞28的厚度8500埃與障礙層30的厚度1000埃，加總之後的厚度為9500埃，其係等於絕緣層20的總厚度。在另一較佳實施例中，可不需要障礙層，而銅插塞28的厚度則須增加，以彌補先前由障礙層30所佔據的空間。
前述各層的尺寸與特徵，僅為說明用而非限制本發明。目前與未來的半導體設計可能會需要各層與各特徵的厚度更薄或更厚，以達成該等設計的設計需求。因此，上述各層與各特徵的更厚與更薄厚度，均仍屬於本發明之範疇。
銅插塞28可以利用下列任一方法進行沈積，包括電鍍(electroplating)、濺鍍、或鍍(plating)。由於障礙層30以及銅插塞28可以一毯覆薄膜(blanket film)方式沈積，此等材料必須從絕緣層20的表面40上移除。在一較佳實施例中，多餘材料係以化學機械研磨(chemical mechanical polishing)方式移除，使得障礙層30與銅插塞28僅留在先前絕緣層20內的開口38之中，如圖5所示。
在本發明一較佳實施例中，穿透電鍍(through plating)可用以沈積銅插塞28的銅。在沈積障礙層30之後，將沈積一光阻並以光微影(photolithography)方式進行圖案化，以在開口38之上的光阻之中形成一開口。之後，穿過光阻的開口而將銅鍍於其中。當沈積了足夠的銅之後，將光阻剝除，並以化學機械研磨製程移除任何多餘材料。或者，一選擇性蝕刻製程可用以移除在此場區域中的任何多餘的銅，包括濕式與乾式蝕刻、並選擇性地加入特製成份其可與待移除的障礙層冶金(metallurgy)與填充材料反應。
在本發明一替代方法中，障礙層30的材料可被沈積，接著從上表面40以化學機械研磨製程移除多餘材料，接著沈積銅插塞28的銅，再接著進行另一化學機械研磨步驟。此種接續進行化學機械研磨的替代方法較不理想，因為使用了額外的化學機械研磨步驟。
請參照至圖6，其係說明本發明一較佳實施例之一步驟。藉由如電漿增強化學氣相沈積等方法，而在絕緣層20、障礙層30以及銅插塞28之上沈積一覆蓋層42。覆蓋層42可為一氮化物層，例如一NBLoK層或氮化矽層，且其沈積厚度係為500埃或以下。覆蓋層42係為選擇性，但較佳係包括此層以避免銅插塞28的氧化。覆蓋層42的較佳材料與厚度僅是作為說明而非限制本發明。
在此時的製程中，已經完成了圖1中的半導體元件10。
請參照圖7，一鈍化層34係以一如旋轉塗佈法(spin apply method)之習知方法而沈積。接著，此鈍化層34係以光微影方式進行圖案化與蝕刻，例如反應性離子蝕刻，而形成開口36。
在此時的製程中，已經完成了圖2中的半導體元件110。
請參照圖8，覆蓋層42位於開口38內的部份，係以反應性離子蝕刻而被蝕刻打開，接著沈積習知的球限金屬44。接著，一定量的銲錫(未示)會被沈積在球限金屬44之上、位於開口38之內的部份，以利將半導體元件110接合至一封裝(未示)。
用以製造半導體元件120(圖9)的製程係類似於半導體元件10,110，除了外加上鋁層50與覆蓋層52以外。可利用習知的方法沈積並圖案化鋁層。較佳係以穿透電鍍而沈積銅至理想厚度。銅插塞28不需要與鋁層50同平面(flush)。如果銅插塞28具有一覆蓋層52，則覆蓋層52不需要與鋁層50同平面。
用以製造半導體元件130(圖10)的製程係類似於半導體元件120，除了一鈍化層34可利用上述方式沈積以外。鈍化層34可以微影方式圖案化，接著若有需要則沈積球限金屬。
上述用以製造半導體元件110的製程可經變更，而在沈積銅插塞28之前沈積鈍化層34。在此變更製程中，可形成開口38並接著沈積鈍化層34。可利用光微影方式圖案化鈍化層以形成開口36，並同時從開口38之中移除任何鈍化材料。之後，可利用覆蓋沈積方式沈積障礙層30，接著以由下往上的電鍍製程、以穿透電鍍方式生成銅插塞28。之後若有需要，可沈積球限金屬。
上述用以製造具有鈍化層34之半導體元件130的製程可經變更，而在沈積銅插塞28之前沈積一鈍化層34。在此變更製程中，可在絕緣層20之中形成一開口，接著沈積鋁層50、再接著沈積鈍化層34。可以光微影方式而在鈍化層中形成一開口36，並同時從絕緣層20開口中任何鈍化材料。之後，可利用覆蓋沈積方式沈積障礙層30，接著以由下往上的電鍍製程、以穿透電鍍方式生成銅插塞28。之後若有需要，可沈積球限金屬。
熟悉該項技藝者可思及本說明書所述之實施例與其他本發明之變化，而不背離本發明之精神。因此，該些變化亦屬於本發明的範疇，而本發明之範疇僅由申請專利範圍所界定。
10．．．半導體元件
12．．．半導體基板
14．．．最終導線層
16．．．介電材料
18．．．金屬導線
20．．．絕緣層
22,24,26．．．子層
28．．．銅插塞
30．．．障礙層
32．．．覆蓋層
34．．．鈍化層
36．．．介層窗
40．．．上表面
42．．．覆蓋層
44．．．球限金屬
50．．．鋁層
52．．．覆蓋層
110,120,130．．．半導體元件
本發明的特徵咸信為新穎，且本發明的元素特徵係在申請專利範圍中詳細描述。各圖示僅為說明用且並未按照比例繪製。本發明無論在組織與操作方法上，則可藉由本說明書以及相關圖示而獲得最佳瞭解。
圖1係為本發明第一實施例之剖面圖，其具有一絕緣層與一銅插塞。
圖2係為本發明第二實施例之剖面圖，其具有一絕緣層、一銅插塞與一鈍化層。
圖3至8係為剖面圖，描繪用以形成本發明第一與第二實施例之各步驟。
圖9係為本發明第三實施例之剖面圖，其具有一絕緣層、一鋁層及一銅插塞。
圖10係為本發明第四實施例之剖面圖，其具有一絕緣層、一鋁層、一銅插塞及一鈍化層。
12．．．半導體基板
14．．．最終導線層
16．．．介電材料
18．．．金屬導線
20．．．絕緣層
22、24、26．．．子層
28．．．銅插塞
30．．．障礙層
34．．．鈍化層
50．．．鋁層
52．．．覆蓋層
130．．．半導體元件

Claims (19)

  1. 一種半導體元件，包括：一半導體基板，具有複數個導線層，其中最終導線層包括一導電材料；一絕緣層，形成於該最終導線層之上，該絕緣層中形成一介層窗(via)開口，以將該最終導線層之該導電材料外露；一障礙層，形成於該介層窗開口中；一銅插塞，形成於該障礙層之上且填滿該介層窗開口，該銅插塞僅延伸至絕緣層的頂部；以及更包含一介電層，形成於該絕緣層之上且具有一開口對齊且露出該銅插塞，該介電層中的該開口缺乏該銅插塞及一鋁層。
  2. 如申請專利範圍第1項所述之半導體元件，其中該障礙層接觸該最終導線層中之該導電材料。
  3. 如申請專利範圍第1項所述之半導體元件，其中該障礙層係選自由鉭/氮化鉭、鈦、鈦鎢、氮化鈦、以及氮化鎢所構成的一群組。
  4. 如申請專利範圍第1項所述之半導體元件，更包括一球限金屬(ball limiting metallurgy)層，形成於該介電層之上以及該開口之中且直接與該銅插塞接觸，該球限金屬層與該銅插塞差異且更包括多量的焊料直接在該球限金屬層之上。
  5. 如申請專利範圍第1項所述之半導體元件，其中該銅插塞具有一側壁，該側壁與該最後導線層之間有一介於45至75度之夾 角。
  6. 如申請專利範圍第1項所述之半導體元件，更包括一覆蓋層介於該絕緣層與該介電層之間。
  7. 如申請專利範圍第6項所述之半導體元件，其中該覆蓋層為一氮化物層。
  8. 一種半導體元件，包括：一半導體基板，具有一最終導線層，該最終導線層包括一導電材料；一絕緣層，形成於該最終導線層之上，該絕緣層中形成一介層窗開口，以外露該最終導線層中之該導電材料；一銅插塞，形成於該介層窗開口中並填滿該介層窗開口，該銅插塞僅延伸至絕緣層的頂部；以及更包含一介電層，形成於該絕緣層之上且具有一開口對齊且露出該銅插塞，該介電層中的該開口缺乏該銅插塞及一鋁層。
  9. 如申請專利範圍第8項所述之半導體元件，更包括一球限金屬(ball limiting metallurgy)層，形成於該介電層之上以及該開口之中且直接與該銅插塞接觸，該球限金屬層與該銅插塞差異且更包括多量的焊料直接在該球限金屬層之上。
  10. 如申請專利範圍第8項所述之半導體元件，其中該銅插塞具有一側壁，該側壁與該最後導線層之間有一介於45至75度之夾角。
  11. 如申請專利範圍第8項所述之半導體元件，更包括一覆蓋層介於該絕緣層與該介電層之間。
  12. 如申請專利範圍第11項所述之半導體元件，其中該覆蓋層為一氮化物層。
  13. 一種形成一半導體元件之方法，包括：獲得一半導體基板，該半導體基板具有複數個導線層，其中最終導線層包括一導電材料；於該最終導電層之上形成一絕緣層；於該絕緣層中形成一介層窗開口，以外露該最終導電層中之該導電材料；於該介層窗開口中形成一障礙層；於該障礙層之上形成一銅插塞且填滿該介層窗開口，其中該銅插塞具有一側壁，該側壁與該最後導線層之間有一介於45至75度之夾角；在該銅插塞之上形成一覆蓋層且直接地覆蓋該銅插塞以避免該銅插塞中的銅氧化，該覆蓋層直接與該側壁接觸；以及直接在該覆蓋層之上形成一介電層，該介電層具有與該銅插塞對齊之一開口，該開口大於該銅插塞致使覆蓋該銅插塞的該覆蓋層露出且額外地使未覆蓋該銅插塞的部分該覆蓋層露出。
  14. 如申請專利範圍第13項所述之方法，其中該障礙層係接觸該最終障礙層中之該導電材料。
  15. 如申請專利範圍第13項所述之方法，其中該覆蓋層為一氮化 物層。
  16. 如申請專利範圍第13項所述之方法，其中該銅插塞為一終端墊。
  17. 一種形成一半導體元件之方法，包括：在該絕緣層之中形成一介層窗開口，以外露該最後導線層中之一導電材料；在該介層窗開口中形成一銅插塞並填滿該介層窗開口，其中該銅插塞具有一側壁，該側壁與該最後導線層之間有一介於45至75度之夾角；在該銅插塞之上形成一覆蓋層且直接地覆蓋該銅插塞以避免該銅插塞中的銅氧化，該覆蓋層直接與該側壁接觸；以及直接在該覆蓋層之上形成一介電層，該介電層具有與該銅插塞對齊之一開口，該開口大於該銅插塞致使覆蓋該銅插塞的該覆蓋層露出且額外地使未覆蓋該銅插塞的部分該覆蓋層露出。
  18. 如申請專利範圍第17項所述之方法，其中該覆蓋層為一氮化物層。
  19. 如申請專利範圍第17項所述之方法，其中該銅插塞為一終端墊。
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