JP2009509319A - 金属相互接続構造体 - Google Patents
金属相互接続構造体 Download PDFInfo
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- JP2009509319A JP2009509319A JP2008530486A JP2008530486A JP2009509319A JP 2009509319 A JP2009509319 A JP 2009509319A JP 2008530486 A JP2008530486 A JP 2008530486A JP 2008530486 A JP2008530486 A JP 2008530486A JP 2009509319 A JP2009509319 A JP 2009509319A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
【解決手段】 相互接続構造体及びその製造方法が提供される。相互接続構造体は、パターン形成された開口部を有する誘電体層と、パターン形成された開口部内に配置された金属構造と、金属構造の上に重なる誘電体キャップとを含む。誘電体キャップは、内部引張応力を有し、この応力は、特に金属ラインが引張応力を有する場合に、金属ラインから離れる方向のエレクトロマイグレーションが発生することを回避するのに役立つ。
【選択図】 図4
Description
本発明の実施形態によれば、1つの目的は、チップの金属ラインから外向き方向の、銅の所望されない輸送を低減することである。別の目的は、ビアと金属ラインとの間の界面における空隙の発生を回避又は低減することである。
101:金属充填材
102、302:層間誘電体層(ILD)
103、119:拡散障壁層
105:開口部
108:主表面
110:活性半導体層
112:活性領域
115、315:金属ライン
118、318:導電性ビア
122:金属シリサイド
215、226、236、415、426、436:誘電体キャップ層
310:厚い誘電体キャップ層
410:金属キャッピング層
Claims (20)
- パターン形成された開口部を有する誘電体層と、
前記パターン形成された開口部内に配置された金属構造と、
前記金属構造の上に重なる誘電体キャップとを備え、前記誘電体キャップが内部引張応力を有する、相互接続構造体。 - 前記金属構造が、アルミニウム、銅、タングステン、銀、金及びニッケルから成る群から選択される少なくとも1つの金属を含む、請求項1に記載の相互接続構造体。
- 前記金属構造が、前記開口部内に、前記パターン形成された開口部の壁及び底部をライニングする拡散障壁層と、前記拡散障壁層の上に重なる銅の充填材とを含む、請求項1に記載の相互接続構造体。
- 前記誘電体層の上面が主表面を画定し、前記パターン形成された開口部が前記主表面と平行な方向に配向された第1のパターン形成された開口部であり、前記金属構造が第1の金属構造であり、前記誘電体層がさらに、前記第1のパターン形成された開口部に対して位置合わせされ、且つ前記主表面に交差する方向に配向された第2のパターン形成された開口部を備え、前記相互接続構造体がさらに、前記第2のパターン形成された開口部内に配置された第2の金属構造を備え、前記第2の金属構造が前記第1の金属構造に導電的に接続されている、請求項1に記載の相互接続構造体。
- 前記誘電体キャップが、二酸化シリコン(SiO2)、Si3N4、並びにx、y及びzが可変の百分率であるSiCxNyHzから成る群から選択される少なくとも1つの材料を含む、請求項1に記載の相互接続構造体。
- 前記誘電体キャップが、積層配置として連続的に形成される複数の誘電体キャップ層を含み、前記誘電体キャップ層の各々が内部引張応力を有する、請求項1に記載の相互接続構造体。
- 前記複数の誘電体キャップ層が、少なくとも3つの前記誘電体キャップ層を含み、該誘電体キャップ層の各々が、5オングストロームと50オングストロームとの間の厚さを有する、請求項6に記載の相互接続構造体。
- 前記金属構造の上に重なり、且つ前記複数の誘電体キャップ層の下に重なる誘電体下層をさらに備え、前記誘電体下層が、実質的に50オングストロームを超える厚さを有する、請求項7に記載の相互接続構造体。
- 前記金属構造に対して位置合わせされ、且つ前記金属構造と接触する拡散障壁層をさらに備え、前記誘電体キャップが、前記拡散障壁層の上に重なる、請求項1に記載の相互接続構造体。
- 前記拡散障壁層が、10オングストロームと500オングストロームとの間の厚さを有する、請求項9に記載の相互接続構造体。
- 前記金属構造の上面に接触する金属拡散障壁層をさらに備え、前記金属拡散障壁がコバルト合金を含む、請求項1に記載の相互接続構造体。
- 請求項1から請求項11までのいずれか1項に記載の相互接続構造体を備える、集積回路。
- 相互接続構造体を形成する方法であって、
誘電体層内で開口部をパターン形成するステップと、
前記パターン形成された開口部内に金属構造を形成するステップと、
前記金属構造の上に誘電体キャップを形成するステップとを含み、前記誘電体キャップが内部引張応力を有する、方法。 - 前記誘電体キャップが、誘電体材料を含む層を堆積し、前記堆積された層をプラズマ処理するステップによって形成される、請求項13に記載の方法。
- 前記金属構造が、アルミニウム、銅、タングステン、銀、金、及びニッケルから成る群から選択される少なくとも1つの金属を含む、請求項14に記載の方法。
- 前記金属構造を形成する前記ステップが、前記パターン形成された開口部の壁及び底部をライニングする拡散障壁層を堆積してライニングされた開口部を形成するステップと、前記ライニングされた開口部を銅で充填するステップとを含む、請求項14に記載の方法。
- 前記誘電体層の上面が主表面を画定し、前記パターン形成された開口部が前記主表面と平行な第1の方向に配向された第1のパターン開口部であり、前記金属構造が第1の金属構造であり、前記方法が、前記第1のパターン形成された開口部に位置合わせされた第2の開口部をパターン形成するステップをさらに含み、前記第2の開口部は前記第1の方向に交差する第2の方向に配向され、前記金属構造を形成する前記ステップが、前記第2のパターン形成された開口部内に第2の金属構造を形成するステップを含み、前記第2の金属構造が前記第1の金属構造に導電的に接続される、請求項16に記載の方法。
- 前記誘電体キャップを形成する前記ステップが、複数の誘電体キャップ層の各々を堆積させるステップと、前記誘電体キャップ層の各々が内部引張応力を有するように、後続の各誘電体キャップ層を堆積する前に前記誘電体キャップ層をプラズマ処理するステップとを含む、請求項14に記載の方法。
- 前記の複数の誘電体キャップ層を形成する前に、前記金属構造の上に誘電体下層を形成するステップをさらに含む、請求項18に記載の方法。
- 前記誘電体キャップを形成する前に、前記金属構造の上面に接触する金属障壁層を選択的に堆積させるステップをさらに含む、請求項14に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US11/162,666 | 2005-09-19 | ||
US11/162,666 US7563704B2 (en) | 2005-09-19 | 2005-09-19 | Method of forming an interconnect including a dielectric cap having a tensile stress |
PCT/EP2006/066077 WO2007039385A1 (en) | 2005-09-19 | 2006-09-06 | Metal interconnect structure for a microelectronic element |
Publications (3)
Publication Number | Publication Date |
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JP2009509319A true JP2009509319A (ja) | 2009-03-05 |
JP2009509319A5 JP2009509319A5 (ja) | 2009-04-16 |
JP5261647B2 JP5261647B2 (ja) | 2013-08-14 |
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JP2008530486A Active JP5261647B2 (ja) | 2005-09-19 | 2006-09-06 | 金属相互接続構造体 |
Country Status (7)
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US (1) | US7563704B2 (ja) |
EP (1) | EP1943675B1 (ja) |
JP (1) | JP5261647B2 (ja) |
KR (1) | KR20080047383A (ja) |
CN (1) | CN100583427C (ja) |
TW (1) | TWI397149B (ja) |
WO (1) | WO2007039385A1 (ja) |
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US9224643B2 (en) * | 2011-09-19 | 2015-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for tunable interconnect scheme |
US8981466B2 (en) * | 2013-03-11 | 2015-03-17 | International Business Machines Corporation | Multilayer dielectric structures for semiconductor nano-devices |
KR102122593B1 (ko) * | 2013-10-22 | 2020-06-15 | 삼성전자주식회사 | 반도체 소자 |
US9299605B2 (en) * | 2014-03-07 | 2016-03-29 | Applied Materials, Inc. | Methods for forming passivation protection for an interconnection structure |
US11756828B2 (en) | 2018-11-20 | 2023-09-12 | Applied Materials, Inc. | Cluster processing system for forming a transition metal material |
JP7280455B1 (ja) | 2022-11-01 | 2023-05-23 | ヤマザキマザック株式会社 | 加工シミュレーション装置、数値制御旋盤、工作機械システム、ワーク加工方法、および、プログラム |
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2005
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2006
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- 2006-09-06 EP EP06793278A patent/EP1943675B1/en active Active
- 2006-09-06 JP JP2008530486A patent/JP5261647B2/ja active Active
- 2006-09-06 KR KR1020087006150A patent/KR20080047383A/ko active IP Right Grant
- 2006-09-06 CN CN200680034290A patent/CN100583427C/zh active Active
- 2006-09-19 TW TW095134663A patent/TWI397149B/zh not_active IP Right Cessation
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CN101268549A (zh) | 2008-09-17 |
CN100583427C (zh) | 2010-01-20 |
TWI397149B (zh) | 2013-05-21 |
US20070063348A1 (en) | 2007-03-22 |
KR20080047383A (ko) | 2008-05-28 |
US7563704B2 (en) | 2009-07-21 |
TW200729400A (en) | 2007-08-01 |
EP1943675A1 (en) | 2008-07-16 |
JP5261647B2 (ja) | 2013-08-14 |
EP1943675B1 (en) | 2013-03-20 |
WO2007039385A1 (en) | 2007-04-12 |
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