ATE501523T1 - Selektive bildung einer verbindung, die ein halbleitermaterial und ein metallmaterial in einem substrat enthält, mit hilfe einer germaniumoxydschicht - Google Patents

Selektive bildung einer verbindung, die ein halbleitermaterial und ein metallmaterial in einem substrat enthält, mit hilfe einer germaniumoxydschicht

Info

Publication number
ATE501523T1
ATE501523T1 AT08354062T AT08354062T ATE501523T1 AT E501523 T1 ATE501523 T1 AT E501523T1 AT 08354062 T AT08354062 T AT 08354062T AT 08354062 T AT08354062 T AT 08354062T AT E501523 T1 ATE501523 T1 AT E501523T1
Authority
AT
Austria
Prior art keywords
germanium oxide
oxide layer
substrate
layer
compound containing
Prior art date
Application number
AT08354062T
Other languages
English (en)
Inventor
Fabrice Nemouchi
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE501523T1 publication Critical patent/ATE501523T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H10D30/0213—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation providing different silicide thicknesses on gate electrodes and on source regions or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
AT08354062T 2007-10-02 2008-09-24 Selektive bildung einer verbindung, die ein halbleitermaterial und ein metallmaterial in einem substrat enthält, mit hilfe einer germaniumoxydschicht ATE501523T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0706902A FR2921750B1 (fr) 2007-10-02 2007-10-02 Formation selective d'un compose comprenant un materiau semi-conducteur et un materiau metallique dans un substrat, a travers une couche d'oxyde de germanium

Publications (1)

Publication Number Publication Date
ATE501523T1 true ATE501523T1 (de) 2011-03-15

Family

ID=39167430

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08354062T ATE501523T1 (de) 2007-10-02 2008-09-24 Selektive bildung einer verbindung, die ein halbleitermaterial und ein metallmaterial in einem substrat enthält, mit hilfe einer germaniumoxydschicht

Country Status (6)

Country Link
US (1) US7842612B2 (de)
EP (1) EP2045837B1 (de)
JP (1) JP2009135435A (de)
AT (1) ATE501523T1 (de)
DE (1) DE602008005382D1 (de)
FR (1) FR2921750B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102227001B (zh) * 2011-06-23 2013-03-06 北京大学 一种锗基nmos器件及其制备方法
KR102061265B1 (ko) * 2013-07-23 2019-12-31 삼성전자주식회사 반도체 장치 및 그 제조방법
US9722026B2 (en) * 2013-08-30 2017-08-01 Japan Science And Technology Agency Semiconductor structure in which film including germanium oxide is provided on germanium layer, and method for manufacturing semiconductor structure
US10763115B2 (en) * 2017-06-16 2020-09-01 Nxp Usa, Inc. Substrate treatment method for semiconductor device fabrication
US10388755B1 (en) 2018-06-04 2019-08-20 International Business Machines Corporation Stacked nanosheets with self-aligned inner spacers and metallic source/drain
US10504794B1 (en) * 2018-06-25 2019-12-10 International Business Machines Corporation Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor
FR3088483B1 (fr) * 2018-11-14 2022-01-14 Commissariat Energie Atomique Transistor a blocs de source et de drain siliciures proches du canal

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6399467B1 (en) * 2000-12-08 2002-06-04 Advanced Micro Devices Method of salicide formation
US6872610B1 (en) * 2003-11-18 2005-03-29 Texas Instruments Incorporated Method for preventing polysilicon mushrooming during selective epitaxial processing
US7148143B2 (en) * 2004-03-24 2006-12-12 Texas Instruments Incorporated Semiconductor device having a fully silicided gate electrode and method of manufacture therefor
FR2892856A1 (fr) 2005-11-02 2007-05-04 St Microelectronics Crolles 2 Formation de zones de siliciure dans un dispositif semiconducteur

Also Published As

Publication number Publication date
FR2921750B1 (fr) 2014-07-25
US20090087985A1 (en) 2009-04-02
FR2921750A1 (fr) 2009-04-03
EP2045837A1 (de) 2009-04-08
EP2045837B1 (de) 2011-03-09
US7842612B2 (en) 2010-11-30
JP2009135435A (ja) 2009-06-18
DE602008005382D1 (de) 2011-04-21

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