DE602008005382D1 - Selektive Bildung einer Verbindung, die ein Halbleitermaterial und ein Metallmaterial in einem Substrat enthält, mit Hilfe einer Germaniumoxydschicht - Google Patents
Selektive Bildung einer Verbindung, die ein Halbleitermaterial und ein Metallmaterial in einem Substrat enthält, mit Hilfe einer GermaniumoxydschichtInfo
- Publication number
- DE602008005382D1 DE602008005382D1 DE602008005382T DE602008005382T DE602008005382D1 DE 602008005382 D1 DE602008005382 D1 DE 602008005382D1 DE 602008005382 T DE602008005382 T DE 602008005382T DE 602008005382 T DE602008005382 T DE 602008005382T DE 602008005382 D1 DE602008005382 D1 DE 602008005382D1
- Authority
- DE
- Germany
- Prior art keywords
- germanium oxide
- oxide layer
- substrate
- layer
- compound containing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000007769 metal material Substances 0.000 title abstract 4
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 title abstract 3
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 title abstract 3
- 239000000463 material Substances 0.000 title abstract 2
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 title abstract 2
- 230000015572 biosynthetic process Effects 0.000 title 1
- 150000001875 compounds Chemical class 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000000137 annealing Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Chemical Vapour Deposition (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0706902A FR2921750B1 (fr) | 2007-10-02 | 2007-10-02 | Formation selective d'un compose comprenant un materiau semi-conducteur et un materiau metallique dans un substrat, a travers une couche d'oxyde de germanium |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602008005382D1 true DE602008005382D1 (de) | 2011-04-21 |
Family
ID=39167430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602008005382T Active DE602008005382D1 (de) | 2007-10-02 | 2008-09-24 | Selektive Bildung einer Verbindung, die ein Halbleitermaterial und ein Metallmaterial in einem Substrat enthält, mit Hilfe einer Germaniumoxydschicht |
Country Status (6)
Country | Link |
---|---|
US (1) | US7842612B2 (de) |
EP (1) | EP2045837B1 (de) |
JP (1) | JP2009135435A (de) |
AT (1) | ATE501523T1 (de) |
DE (1) | DE602008005382D1 (de) |
FR (1) | FR2921750B1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102227001B (zh) * | 2011-06-23 | 2013-03-06 | 北京大学 | 一种锗基nmos器件及其制备方法 |
KR102061265B1 (ko) * | 2013-07-23 | 2019-12-31 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
KR101786439B1 (ko) * | 2013-08-30 | 2017-10-18 | 고쿠리츠켄큐카이하츠호진 카가쿠기쥬츠신코키코 | 게르마늄층 상에 산화 게르마늄을 포함하는 막을 구비하는 반도체 구조 및 그 제조방법 |
US10763115B2 (en) * | 2017-06-16 | 2020-09-01 | Nxp Usa, Inc. | Substrate treatment method for semiconductor device fabrication |
US10388755B1 (en) | 2018-06-04 | 2019-08-20 | International Business Machines Corporation | Stacked nanosheets with self-aligned inner spacers and metallic source/drain |
US10504794B1 (en) | 2018-06-25 | 2019-12-10 | International Business Machines Corporation | Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor |
FR3088483B1 (fr) * | 2018-11-14 | 2022-01-14 | Commissariat Energie Atomique | Transistor a blocs de source et de drain siliciures proches du canal |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6399467B1 (en) * | 2000-12-08 | 2002-06-04 | Advanced Micro Devices | Method of salicide formation |
US6872610B1 (en) * | 2003-11-18 | 2005-03-29 | Texas Instruments Incorporated | Method for preventing polysilicon mushrooming during selective epitaxial processing |
US7148143B2 (en) * | 2004-03-24 | 2006-12-12 | Texas Instruments Incorporated | Semiconductor device having a fully silicided gate electrode and method of manufacture therefor |
FR2892856A1 (fr) | 2005-11-02 | 2007-05-04 | St Microelectronics Crolles 2 | Formation de zones de siliciure dans un dispositif semiconducteur |
-
2007
- 2007-10-02 FR FR0706902A patent/FR2921750B1/fr not_active Expired - Fee Related
-
2008
- 2008-09-24 EP EP08354062A patent/EP2045837B1/de not_active Not-in-force
- 2008-09-24 DE DE602008005382T patent/DE602008005382D1/de active Active
- 2008-09-24 AT AT08354062T patent/ATE501523T1/de not_active IP Right Cessation
- 2008-09-29 US US12/285,068 patent/US7842612B2/en not_active Expired - Fee Related
- 2008-10-02 JP JP2008257690A patent/JP2009135435A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US20090087985A1 (en) | 2009-04-02 |
EP2045837B1 (de) | 2011-03-09 |
US7842612B2 (en) | 2010-11-30 |
ATE501523T1 (de) | 2011-03-15 |
FR2921750A1 (fr) | 2009-04-03 |
EP2045837A1 (de) | 2009-04-08 |
FR2921750B1 (fr) | 2014-07-25 |
JP2009135435A (ja) | 2009-06-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602008005382D1 (de) | Selektive Bildung einer Verbindung, die ein Halbleitermaterial und ein Metallmaterial in einem Substrat enthält, mit Hilfe einer Germaniumoxydschicht | |
WO2004079796A3 (en) | Atomic layer deposited dielectric layers | |
JP2006210555A5 (de) | ||
JP2008505486A5 (de) | ||
WO2007117718A3 (en) | Simplified pitch doubling process flow | |
WO2007117805A3 (en) | Method of separating semiconductor dies | |
ATE491227T1 (de) | Verfahren zur herstellung von interkonnektverbindungen für halbleiterkomponenten | |
DE602008000830D1 (de) | Herstellungsverfahren einer Mikrofluid-Komponente, die mindestens einen mit Nanostrukturen gefüllten Mikrokanal umfasst | |
WO2006057826A3 (en) | Topotactic anion exchange oxide films and method of producing the same | |
EP1435649A3 (de) | Methoden zur Herstellung eines Transistor-Gates | |
WO2010138811A3 (en) | Method of providing a flexible semiconductor device at high temperatures and flexible semiconductor device thereof | |
TW200738907A (en) | Thermal barrier coatings and processes for applying same | |
WO2005010964A3 (en) | Silicon crystallization using self-assembled monolayers | |
TW200746262A (en) | Method of manufacturing nitride semiconductor substrate and composite material substrate | |
WO2008141158A3 (en) | Substrate surface structures and processes for forming the same | |
WO2005116286A3 (en) | Method for forming a hardened surface on a substrate | |
EP2533305A3 (de) | Verfahren zur blasenfreien Passivierung einer Siliziumoberfläche | |
JP2006237371A5 (de) | ||
WO2008099246A3 (en) | Multilayer structure and its fabrication process | |
WO2005122254A3 (en) | Gate stack and gate stack etch sequence for metal gate integration | |
FR2912259B1 (fr) | Procede de fabrication d'un substrat du type "silicium sur isolant". | |
EP1605499A3 (de) | Verfahren zur Herstellung einer kristallinen Siliziumschicht | |
WO2016060455A3 (ko) | 박막 트랜지스터 제조 방법 및 박막 트랜지스터 | |
DE502005009420D1 (de) | Verfahren zur herstellung einer bereichsweisen metallisierung sowie transferfolie und deren verwendung | |
TW200603255A (en) | Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method |