JP2010040772A5 - - Google Patents

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Publication number
JP2010040772A5
JP2010040772A5 JP2008202139A JP2008202139A JP2010040772A5 JP 2010040772 A5 JP2010040772 A5 JP 2010040772A5 JP 2008202139 A JP2008202139 A JP 2008202139A JP 2008202139 A JP2008202139 A JP 2008202139A JP 2010040772 A5 JP2010040772 A5 JP 2010040772A5
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JP
Japan
Prior art keywords
film
forming
groove
etching stopper
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008202139A
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Japanese (ja)
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JP2010040772A (en
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Publication date
Application filed filed Critical
Priority to JP2008202139A priority Critical patent/JP2010040772A/en
Priority claimed from JP2008202139A external-priority patent/JP2010040772A/en
Priority to US12/535,665 priority patent/US8039390B2/en
Publication of JP2010040772A publication Critical patent/JP2010040772A/en
Publication of JP2010040772A5 publication Critical patent/JP2010040772A5/ja
Pending legal-status Critical Current

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Claims (5)

ＳｉおよびＯを含む絶縁材料からなる絶縁層に溝を形成する溝形成工程と、
スパッタ法により、前記溝の側面および底面に、ＣｕおよびＭｎを含む合金材料からなる合金膜を被着させる合金膜被着工程と、
前記合金膜における前記溝の底面に被着された部分を薄くする薄化工程と、
前記薄化工程後、前記溝内に、Ｃｕを主成分とする金属材料からなるＣｕ配線を形成する配線形成工程と、
熱処理により、前記Ｃｕ配線と前記絶縁層との間に、Ｍｎ
ｘ Ｓｉ ｙ Ｏ ｚ （ｘ，ｙ，ｚ：零よりも大きい数）からなるバリア膜を形成するバリア膜形成工程とを含む、半導体装置の製造方法。 A groove forming step of forming a groove in an insulating layer made of an insulating material containing Si and O;
An alloy film deposition step of depositing an alloy film made of an alloy material containing Cu and Mn on the side and bottom surfaces of the groove by sputtering;
A thinning step of thinning a portion of the alloy film deposited on the bottom surface of the groove;
After the thinning step, a wiring forming step of forming a Cu wiring made of a metal material mainly composed of Cu in the groove;
By heat treatment, Mn is formed between the Cu wiring and the insulating layer.
and a barrier film forming step of forming a barrier film made of x Si y O z (x, y, z: a number greater than zero). 前記薄化工程では、逆スパッタ法が用いられ、
前記配線形成工程は、
スパッタ法により、前記薄化工程後の前記合金膜上にＣｕを主成分とする金属材料からなるシード膜を形成する工程と、
めっき法により、前記シード膜上にＣｕからなるめっき層を形成する工程とを含む、請求項１に記載の半導体装置の製造方法。 In the thinning step, a reverse sputtering method is used,
The wiring formation step includes
Forming a seed film made of a metal material mainly composed of Cu on the alloy film after the thinning process by a sputtering method;
The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a plating layer made of Cu on the seed film by a plating method. 第１絶縁層中に形成されＣｕを主成分とする金属材料からなる下配線上に形成され、表面に溝が形成されたＳｉおよびＯを含む絶縁材料からなる第２絶縁層と、  A second insulating layer made of an insulating material containing Si and O, formed on a lower wiring made of a metal material mainly composed of Cu formed in the first insulating layer, and having grooves formed on the surface;
前記溝の内面上に形成されたＭｎMn formed on the inner surface of the groove
ｘ Ｓｉ ｙ Ｏ ｚ （ｘ，ｙ，ｚ：零よりも大きい数）からなるバリア膜と、a barrier film made of x Si y O z (x, y, z: a number greater than zero);
前記バリア膜上に形成されたＣｕを主成分とする金属材料からなるＣｕ配線とを含む、半導体装置であって、A semiconductor device including a Cu wiring made of a metal material mainly composed of Cu formed on the barrier film,
第２絶縁層は、第１絶縁層上に積層された第１エッチングストッパ膜と、その上方に積層された第１層間絶縁膜と、その上方に積層された第２のエッチングストッパ膜と、その上方に積層された第２層間絶縁膜とを有することを特長とする半導体装置。The second insulating layer includes a first etching stopper film laminated on the first insulating layer, a first interlayer insulating film laminated thereon, a second etching stopper film laminated thereon, and A semiconductor device comprising a second interlayer insulating film stacked above. 第１のエッチングストッパ膜と第２のエッチングストッパ膜とは同じ組成である、請求項３に記載の半導体装置。  The semiconductor device according to claim 3, wherein the first etching stopper film and the second etching stopper film have the same composition. 第１のエッチングストッパ膜の長さは、第２のエッチングストッパ膜の長さよりも長い、請求項３に記載の半導体装置。  4. The semiconductor device according to claim 3, wherein the length of the first etching stopper film is longer than the length of the second etching stopper film.
JP2008202139A 2008-08-05 2008-08-05 Method of manufacturing semiconductor device Pending JP2010040772A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008202139A JP2010040772A (en) 2008-08-05 2008-08-05 Method of manufacturing semiconductor device
US12/535,665 US8039390B2 (en) 2008-08-05 2009-08-04 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008202139A JP2010040772A (en) 2008-08-05 2008-08-05 Method of manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JP2010040772A JP2010040772A (en) 2010-02-18
JP2010040772A5 true JP2010040772A5 (en) 2011-09-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008202139A Pending JP2010040772A (en) 2008-08-05 2008-08-05 Method of manufacturing semiconductor device

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JP (1) JP2010040772A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8531033B2 (en) 2009-09-07 2013-09-10 Advanced Interconnect Materials, Llc Contact plug structure, semiconductor device, and method for forming contact plug
JP2021136271A (en) * 2020-02-25 2021-09-13 キオクシア株式会社 Semiconductor device and method for manufacturing the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6949461B2 (en) * 2002-12-11 2005-09-27 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure
JP2006216787A (en) * 2005-02-03 2006-08-17 Renesas Technology Corp Semiconductor device and its fabrication process
JP2007027347A (en) * 2005-07-15 2007-02-01 Sony Corp Semiconductor device and manufacturing method thereof
JP2007059660A (en) * 2005-08-25 2007-03-08 Sony Corp Semiconductor device and manufacturing method thereof
JP2007081113A (en) * 2005-09-14 2007-03-29 Sony Corp Method for manufacturing semiconductor device
JP2007173511A (en) * 2005-12-22 2007-07-05 Sony Corp Method for fabricating a semiconductor device
JP5076482B2 (en) * 2006-01-20 2012-11-21 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP5076452B2 (en) * 2006-11-13 2012-11-21 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
JP5010265B2 (en) * 2006-12-18 2012-08-29 株式会社東芝 Manufacturing method of semiconductor device
JP5103914B2 (en) * 2007-01-31 2012-12-19 富士通セミコンダクター株式会社 Semiconductor device manufacturing method and semiconductor device
JP5141761B2 (en) * 2008-02-27 2013-02-13 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof

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