JP2010010634A - リードフレーム及び半導体装置の製造方法 - Google Patents

リードフレーム及び半導体装置の製造方法 Download PDF

Info

Publication number
JP2010010634A
JP2010010634A JP2008171682A JP2008171682A JP2010010634A JP 2010010634 A JP2010010634 A JP 2010010634A JP 2008171682 A JP2008171682 A JP 2008171682A JP 2008171682 A JP2008171682 A JP 2008171682A JP 2010010634 A JP2010010634 A JP 2010010634A
Authority
JP
Japan
Prior art keywords
lead frame
resin
lead
die pad
tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008171682A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010010634A5 (enExample
Inventor
Naoki Yamabe
直樹 山辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008171682A priority Critical patent/JP2010010634A/ja
Publication of JP2010010634A publication Critical patent/JP2010010634A/ja
Publication of JP2010010634A5 publication Critical patent/JP2010010634A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP2008171682A 2008-06-30 2008-06-30 リードフレーム及び半導体装置の製造方法 Pending JP2010010634A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008171682A JP2010010634A (ja) 2008-06-30 2008-06-30 リードフレーム及び半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008171682A JP2010010634A (ja) 2008-06-30 2008-06-30 リードフレーム及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2010010634A true JP2010010634A (ja) 2010-01-14
JP2010010634A5 JP2010010634A5 (enExample) 2011-05-12

Family

ID=41590722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008171682A Pending JP2010010634A (ja) 2008-06-30 2008-06-30 リードフレーム及び半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2010010634A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011087119A1 (ja) * 2010-01-18 2011-07-21 ローム株式会社 半導体装置およびその製造方法
JP2016048784A (ja) * 2014-08-27 2016-04-07 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP2016105432A (ja) * 2014-12-01 2016-06-09 Ｓｈマテリアル株式会社 リードフレームの製造方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150059U (enExample) * 1975-05-26 1976-12-01
JPS55133561A (en) * 1979-04-03 1980-10-17 Dainippon Printing Co Ltd Method of fabricating lead frame for semiconductor
JPS6347960A (ja) * 1986-08-18 1988-02-29 Toppan Printing Co Ltd 半導体装置用リードフレームの製造方法
JPH059756A (ja) * 1991-07-04 1993-01-19 Kyodo Printing Co Ltd エツチング方法
JPH09237863A (ja) * 1996-02-28 1997-09-09 Samsung Aerospace Ind Ltd 半導体リードフレーム及び半導体パッケージ方法
JP2002076228A (ja) * 2000-09-04 2002-03-15 Dainippon Printing Co Ltd 樹脂封止型半導体装置
WO2003094232A1 (fr) * 2002-04-30 2003-11-13 Renesas Technology Corp. Appareil a semiconducteurs et appareil electronique
JP2003324177A (ja) * 2002-04-26 2003-11-14 Matsushita Electric Ind Co Ltd リードフレームの製造方法および半導体装置
JP2004165565A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd リードフレームおよび半導体装置の製造方法
JP2006229139A (ja) * 2005-02-21 2006-08-31 Nitto Denko Corp 半導体装置の製造方法、及びそれに用いる耐熱性粘着テープ
JP2006310397A (ja) * 2005-04-26 2006-11-09 Dainippon Printing Co Ltd 回路部材、回路部材の製造方法、半導体装置、及び回路部材表面の積層構造
WO2007011767A1 (en) * 2005-07-18 2007-01-25 Qualcomm Incorporated Integrated circuit packaging

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51150059U (enExample) * 1975-05-26 1976-12-01
JPS55133561A (en) * 1979-04-03 1980-10-17 Dainippon Printing Co Ltd Method of fabricating lead frame for semiconductor
JPS6347960A (ja) * 1986-08-18 1988-02-29 Toppan Printing Co Ltd 半導体装置用リードフレームの製造方法
JPH059756A (ja) * 1991-07-04 1993-01-19 Kyodo Printing Co Ltd エツチング方法
JPH09237863A (ja) * 1996-02-28 1997-09-09 Samsung Aerospace Ind Ltd 半導体リードフレーム及び半導体パッケージ方法
JP2002076228A (ja) * 2000-09-04 2002-03-15 Dainippon Printing Co Ltd 樹脂封止型半導体装置
JP2003324177A (ja) * 2002-04-26 2003-11-14 Matsushita Electric Ind Co Ltd リードフレームの製造方法および半導体装置
WO2003094232A1 (fr) * 2002-04-30 2003-11-13 Renesas Technology Corp. Appareil a semiconducteurs et appareil electronique
JP2004165565A (ja) * 2002-11-15 2004-06-10 Matsushita Electric Ind Co Ltd リードフレームおよび半導体装置の製造方法
JP2006229139A (ja) * 2005-02-21 2006-08-31 Nitto Denko Corp 半導体装置の製造方法、及びそれに用いる耐熱性粘着テープ
JP2006310397A (ja) * 2005-04-26 2006-11-09 Dainippon Printing Co Ltd 回路部材、回路部材の製造方法、半導体装置、及び回路部材表面の積層構造
WO2007011767A1 (en) * 2005-07-18 2007-01-25 Qualcomm Incorporated Integrated circuit packaging

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011087119A1 (ja) * 2010-01-18 2011-07-21 ローム株式会社 半導体装置およびその製造方法
CN102714164A (zh) * 2010-01-18 2012-10-03 罗姆股份有限公司 半导体装置和其制造方法
US8779569B2 (en) 2010-01-18 2014-07-15 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
TWI447825B (zh) * 2010-01-18 2014-08-01 羅姆電子股份有限公司 Semiconductor device and manufacturing method thereof
US9142494B2 (en) 2010-01-18 2015-09-22 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US9406591B2 (en) 2010-01-18 2016-08-02 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US9859194B2 (en) 2010-01-18 2018-01-02 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
JP2016048784A (ja) * 2014-08-27 2016-04-07 大日本印刷株式会社 リードフレームおよびその製造方法、ならびに半導体装置およびその製造方法
JP2016105432A (ja) * 2014-12-01 2016-06-09 Ｓｈマテリアル株式会社 リードフレームの製造方法

Similar Documents

Publication Publication Date Title
US6208020B1 (en) Leadframe for use in manufacturing a resin-molded semiconductor device
US7790500B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
JP3062192B1 (ja) リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法
US8236612B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
KR20030031412A (ko) 리드 프레임과 그 제조 방법 및 그를 이용한 반도체장치의 제조 방법
JP2002134676A (ja) リードフレーム及びそれを備えた半導体パッケージ、並びにその半導体パッケージの製造方法
JP5278037B2 (ja) 樹脂封止型半導体装置
KR101674537B1 (ko) 리드프레임 제조방법과 그에 따른 리드프레임 및 반도체 패키지 제조방법과 그에 따른 반도체 패키지
JP3535760B2 (ja) 樹脂封止型半導体装置，その製造方法及びリードフレーム
JP2010010634A (ja) リードフレーム及び半導体装置の製造方法
JP2011142337A (ja) 半導体装置の製造方法
US8829685B2 (en) Circuit device having funnel shaped lead and method for manufacturing the same
JP2008113021A (ja) 半導体装置の製造方法
JP2003197663A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2017038051A (ja) 半導体パッケージ及びその製造方法
JP3915337B2 (ja) リードフレームとそれを用いた樹脂封止型半導体装置の製造方法
JP5420737B2 (ja) 半導体装置の製造方法
JP3503502B2 (ja) 樹脂封止型半導体装置およびその製造方法
TWI623076B (zh) 導線架製作方法
JP2011176030A (ja) 樹脂封止型半導体装置、リードフレーム、および樹脂封止型半導体装置の製造方法
JP2001077285A (ja) リードフレームとそれを用いた樹脂封止型半導体装置の製造方法
JP5622128B2 (ja) 樹脂封止型半導体装置、多面付樹脂封止型半導体装置、リードフレーム、および樹脂封止型半導体装置の製造方法
JP2001077275A (ja) リードフレームとそれを用いた樹脂封止型半導体装置の製造方法
JP2002164496A (ja) 半導体装置およびその製造方法
JP5910950B2 (ja) 樹脂封止型半導体装置、多面付樹脂封止型半導体装置、リードフレーム、および樹脂封止型半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110325

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110325

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120229

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120313

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120508

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130205

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130806